From 297375cf51e449ebd4a11aa05b0011016e40f72f Mon Sep 17 00:00:00 2001
From: root <root@no.no.james.local>
Date: Thu, 17 May 2018 17:44:58 +0100
Subject: working 3 detectors with parity checks

---
 Makefile     |   4 +-
 detector.vhd | 146 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 divider.vhd  |  57 +++++++++++++++++++++++
 3 files changed, 206 insertions(+), 1 deletion(-)
 create mode 100644 detector.vhd
 create mode 100644 divider.vhd

diff --git a/Makefile b/Makefile
index d3b7732..b73ea37 100644
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,9 @@
 PROJ=spdif
 
 SRCS=$(wildcard *.vhd *.v *.qsf *.qpf )
-TIDY_SRC= bmc_decoder.vhd ccd.vhd silence_detector.vhd counter.vhd dflipflop.vhd spdif_decoder.vhd spdif.vhd
+S1=${SRCS:pll100.vhd=}
+S2=${S1:pll200.vhd=}
+TIDY_SRC=${S2}
 
 SOF=output_files/${PROJ}.sof
 POF=${PROJ}.pof
diff --git a/detector.vhd b/detector.vhd
new file mode 100644
index 0000000..b6e598f
--- /dev/null
+++ b/detector.vhd
@@ -0,0 +1,146 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.numeric_std.all;
+
+entity detector is
+    port (
+	clk_in	:	in std_logic;
+	spdif_in:	in std_logic;
+        n_reset   : in std_logic;
+	divisor : in integer;
+        silent_thresh : in integer;
+	valid_divisor: in integer;
+        valid_thresh : in integer;
+	mute : out std_logic;
+	dbg:out std_logic_vector(7 downto 0)
+        );
+end detector;
+
+
+architecture rtl of detector is
+    component ccd is
+        port
+            (
+                n_reset : in  std_logic;
+                clk     : in  std_logic;
+                d       : in  std_logic;
+                q       : out std_logic
+                );
+    end component;
+
+    component divider is
+        port
+            (
+                divisor : in  integer;
+                clk     : in  std_logic;
+                n_reset : in  std_logic;
+                clk_out : out std_logic
+                );
+    end component;
+
+    component spdif_decoder is
+port (
+	n_reset:in std_logic;
+	spdif:in std_logic;
+	clk:in std_logic;
+
+    bmc_ready: out std_logic;
+    bmc_e: out std_logic;
+    bmc_l: out std_logic;
+    bmc_d : out std_logic;
+	
+	d : out std_logic_vector(26 downto 0);
+	ready: out std_logic;
+	sof: out std_logic;
+	bna: out std_logic;
+	sos: out std_logic
+);
+	
+
+
+
+
+    end component;
+
+
+    component silence_detector is
+    port
+        (
+            silent_thresh : in  integer;
+            valid_thresh : in  integer;
+	    valid_divisor : in integer;
+
+            clk       : in  std_logic;
+	    sos		: in std_logic;
+            d         : in  std_logic_vector(23 downto 0);
+            n_reset   : in  std_logic;
+            silent    : out std_logic;
+            valid    : out std_logic;
+	dbg:out std_logic
+            );
+    end component;
+
+    signal spdif :
+        std_logic;
+    signal clk :
+        std_logic;
+    signal d     : std_logic_vector(26 downto 0);
+    signal sos   : std_logic;
+    signal valid : std_logic;
+    signal silent:std_logic;
+    signal mute_buf:std_logic;
+
+begin
+    div1 : divider port map (
+        n_reset => n_reset,
+        clk     => clk_in,
+        divisor => divisor,
+        clk_out => clk
+        );
+
+    b :
+        ccd port map (
+            n_reset => n_reset,
+            clk     => clk,
+            d       => spdif_in,
+            q       => spdif
+            );
+
+    dec : spdif_decoder port map (
+        n_reset   => n_reset,
+        clk       => clk,
+        spdif     => spdif,
+        d         => d,
+	sos	  => sos,
+	bmc_ready => dbg(2)
+        );
+
+    sd : silence_detector port map(
+        n_reset   => n_reset,
+        clk       => clk,
+        sos	  => sos,
+        d         => d(26 downto 3),
+
+        silent_thresh => silent_thresh,
+        valid_thresh  => valid_thresh,
+	valid_divisor => valid_divisor,
+
+        silent    => silent,
+	valid	  => valid,
+        dbg     => dbg(7)
+        );
+
+
+    dbg(0) <= clk;
+    dbg(1) <= spdif;
+    dbg(3) <= sos;
+    dbg(4) <= silent;
+    dbg(5) <= valid;
+    dbg(6) <= mute_buf;
+
+    mute_buf <= silent or (not valid);
+
+    mute <= mute_buf;
+
+end rtl;
diff --git a/divider.vhd b/divider.vhd
new file mode 100644
index 0000000..26280bf
--- /dev/null
+++ b/divider.vhd
@@ -0,0 +1,57 @@
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.numeric_std.all;
+
+entity divider is
+    port
+        (
+            divisor : in  integer;
+            clk     : in  std_logic;
+            n_reset : in  std_logic;
+            clk_out : out std_logic
+            );
+end divider;
+
+
+architecture rtl of divider is
+
+component counter is
+    port
+        (
+            divisor : in  integer;
+            clk     : in  std_logic;
+            n_reset : in  std_logic;
+            pulse_out : out std_logic
+            );
+end component;
+
+
+    signal pulse: std_logic;
+    signal q :
+        std_logic;
+begin
+
+    clk_out <= q;
+
+    c1:counter port map (
+	divisor => divisor,
+	clk => clk,
+	n_reset => n_reset,
+	pulse_out => pulse
+    );
+
+
+    process (clk, pulse, n_reset)
+    begin
+        if n_reset = '0' then
+            q <= '0';
+        elsif RISING_EDGE(clk) and pulse='1' then
+            q <= not q;
+        end if;
+    end process;
+
+end rtl;
+
-- 
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