From 1dc7d758f96dd2b9bd7b03f01ca032d68b696cf0 Mon Sep 17 00:00:00 2001
From: root
Date: Sun, 2 Nov 2014 10:14:39 +0000
Subject: fish
---
libopencm3/.gitignore | 38 +
libopencm3/COPYING.GPL3 | 676 ++
libopencm3/COPYING.LGPL3 | 165 +
libopencm3/HACKING | 82 +
libopencm3/HACKING_COMMON_DOC | 76 +
libopencm3/Makefile | 131 +
libopencm3/README | 159 +
libopencm3/doc/Doxyfile | 21 +
libopencm3/doc/Doxyfile_common | 1809 +++++
libopencm3/doc/DoxygenLayout.xml | 195 +
libopencm3/doc/HACKING | 114 +
libopencm3/doc/Makefile | 145 +
libopencm3/doc/README | 34 +
libopencm3/doc/cm3/Doxyfile | 24 +
libopencm3/doc/cm3/DoxygenLayout_cm3.xml | 205 +
libopencm3/doc/efm32g/Doxyfile | 30 +
libopencm3/doc/efm32g/Doxyfile_latex | 32 +
libopencm3/doc/efm32g/DoxygenLayout_efm32g.xml | 206 +
libopencm3/doc/efm32g/header_efm32g.tex | 61 +
libopencm3/doc/efm32gg/Doxyfile | 30 +
libopencm3/doc/efm32gg/Doxyfile_latex | 32 +
libopencm3/doc/efm32gg/DoxygenLayout_efm32gg.xml | 206 +
libopencm3/doc/efm32gg/header_efm32gg.tex | 61 +
libopencm3/doc/efm32lg/Doxyfile | 30 +
libopencm3/doc/efm32lg/Doxyfile_latex | 32 +
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libopencm3/doc/efm32tg/DoxygenLayout_efm32tg.xml | 206 +
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libopencm3/doc/lm3s/Doxyfile | 28 +
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libopencm3/doc/lpc13xx/header_lpc13xx.tex | 61 +
libopencm3/doc/lpc17xx/Doxyfile | 28 +
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libopencm3/doc/lpc17xx/DoxygenLayout_lpc17xx.xml | 205 +
libopencm3/doc/lpc17xx/header_lpc17xx.tex | 61 +
libopencm3/doc/lpc43xx/Doxyfile | 28 +
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libopencm3/doc/lpc43xx/DoxygenLayout_lpc43xx.xml | 205 +
libopencm3/doc/lpc43xx/header_lpc43xx.tex | 61 +
libopencm3/doc/sam3a/Doxyfile | 37 +
libopencm3/doc/sam3a/Doxyfile_latex | 39 +
libopencm3/doc/sam3a/DoxygenLayout_sam3a.xml | 206 +
libopencm3/doc/sam3a/header_sam3a.tex | 61 +
libopencm3/doc/sam3n/Doxyfile | 37 +
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libopencm3/doc/sam3n/header_sam3a.tex | 61 +
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libopencm3/doc/sam3s/DoxygenLayout_sam3s.xml | 206 +
libopencm3/doc/sam3s/header_sam3a.tex | 61 +
libopencm3/doc/sam3u/Doxyfile | 37 +
libopencm3/doc/sam3u/Doxyfile_latex | 39 +
libopencm3/doc/sam3u/DoxygenLayout_sam3u.xml | 206 +
libopencm3/doc/sam3u/header_sam3a.tex | 61 +
libopencm3/doc/sam3x/Doxyfile | 37 +
libopencm3/doc/sam3x/Doxyfile_latex | 39 +
libopencm3/doc/sam3x/DoxygenLayout_sam3x.xml | 206 +
libopencm3/doc/sam3x/header_sam3a.tex | 61 +
libopencm3/doc/stm32f0/Doxyfile | 38 +
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libopencm3/doc/stm32f1/Doxyfile | 39 +
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libopencm3/doc/stm32f2/Doxyfile | 38 +
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libopencm3/doc/stm32f2/header_stm32f2.tex | 61 +
libopencm3/doc/stm32f2/index.html | 8 +
libopencm3/doc/stm32f3/Doxyfile | 33 +
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libopencm3/doc/stm32f3/header_stm32f3.tex | 61 +
libopencm3/doc/stm32f3/index.html | 8 +
libopencm3/doc/stm32f4/Doxyfile | 38 +
libopencm3/doc/stm32f4/Doxyfile_latex | 37 +
libopencm3/doc/stm32f4/DoxygenLayout_stm32f4.xml | 206 +
libopencm3/doc/stm32f4/header_stm32f4.tex | 61 +
libopencm3/doc/stm32f4/index.html | 8 +
libopencm3/doc/stm32l1/Doxyfile | 43 +
libopencm3/doc/stm32l1/Doxyfile_latex | 40 +
libopencm3/doc/stm32l1/DoxygenLayout_stm32l1.xml | 206 +
libopencm3/doc/stm32l1/header_stm32l1.tex | 61 +
libopencm3/doc/stm32l1/index.html | 8 +
libopencm3/doc/usb/Doxyfile | 31 +
libopencm3/doc/usb/Doxyfile_latex | 40 +
libopencm3/doc/usb/DoxygenLayout_usb.xml | 206 +
libopencm3/doc/usb/header_usb.tex | 61 +
libopencm3/include/libopencm3/cm3/assert.h | 137 +
libopencm3/include/libopencm3/cm3/common.h | 96 +
libopencm3/include/libopencm3/cm3/cortex.h | 278 +
libopencm3/include/libopencm3/cm3/doc-cm3.h | 22 +
libopencm3/include/libopencm3/cm3/dwt.h | 152 +
libopencm3/include/libopencm3/cm3/fpb.h | 87 +
libopencm3/include/libopencm3/cm3/itm.h | 88 +
libopencm3/include/libopencm3/cm3/memorymap.h | 87 +
libopencm3/include/libopencm3/cm3/mpu.h | 110 +
libopencm3/include/libopencm3/cm3/scb.h | 444 ++
libopencm3/include/libopencm3/cm3/scs.h | 350 +
libopencm3/include/libopencm3/cm3/sync.h | 54 +
libopencm3/include/libopencm3/cm3/systick.h | 134 +
libopencm3/include/libopencm3/cm3/tpiu.h | 97 +
libopencm3/include/libopencm3/cm3/vector.h | 64 +
libopencm3/include/libopencm3/docmain.dox | 21 +
.../include/libopencm3/efm32/efm32g/doc-efm32g.h | 32 +
.../include/libopencm3/efm32/efm32g/irq.json | 38 +
.../include/libopencm3/efm32/efm32gg/doc-efm32gg.h | 32 +
.../include/libopencm3/efm32/efm32gg/irq.json | 46 +
.../include/libopencm3/efm32/efm32lg/doc-efm32lg.h | 33 +
.../include/libopencm3/efm32/efm32lg/irq.json | 46 +
.../include/libopencm3/efm32/efm32tg/doc-efm32tg.h | 32 +
.../include/libopencm3/efm32/efm32tg/irq.json | 31 +
.../include/libopencm3/efm32/efm32tg/memorymap.h | 76 +
libopencm3/include/libopencm3/efm32/memorymap.h | 37 +
libopencm3/include/libopencm3/ethernet/mac.h | 46 +
.../include/libopencm3/ethernet/mac_stm32fxx7.h | 752 +++
libopencm3/include/libopencm3/ethernet/phy.h | 91 +
.../include/libopencm3/ethernet/phy_ksz8051mll.h | 60 +
libopencm3/include/libopencm3/license.dox | 16 +
libopencm3/include/libopencm3/lm3s/doc-lm3s.h | 32 +
libopencm3/include/libopencm3/lm3s/gpio.h | 99 +
libopencm3/include/libopencm3/lm3s/irq.json | 126 +
libopencm3/include/libopencm3/lm3s/memorymap.h | 47 +
libopencm3/include/libopencm3/lm3s/systemcontrol.h | 81 +
libopencm3/include/libopencm3/lm4f/doc-lm4f.h | 32 +
libopencm3/include/libopencm3/lm4f/gpio.h | 380 ++
libopencm3/include/libopencm3/lm4f/memorymap.h | 71 +
libopencm3/include/libopencm3/lm4f/rcc.h | 133 +
libopencm3/include/libopencm3/lm4f/ssi.h | 118 +
libopencm3/include/libopencm3/lm4f/systemcontrol.h | 743 ++
libopencm3/include/libopencm3/lm4f/uart.h | 550 ++
libopencm3/include/libopencm3/lm4f/usb.h | 422 ++
.../include/libopencm3/lpc13xx/doc-lpc13xx.h | 32 +
libopencm3/include/libopencm3/lpc13xx/gpio.h | 124 +
libopencm3/include/libopencm3/lpc13xx/irq.json | 63 +
libopencm3/include/libopencm3/lpc13xx/memorymap.h | 58 +
.../include/libopencm3/lpc17xx/doc-lpc17xx.h | 32 +
libopencm3/include/libopencm3/lpc17xx/gpio.h | 160 +
libopencm3/include/libopencm3/lpc17xx/irq.json | 42 +
libopencm3/include/libopencm3/lpc17xx/memorymap.h | 65 +
libopencm3/include/libopencm3/lpc43xx/adc.h | 113 +
libopencm3/include/libopencm3/lpc43xx/atimer.h | 70 +
libopencm3/include/libopencm3/lpc43xx/ccu.h | 402 ++
libopencm3/include/libopencm3/lpc43xx/cgu.h | 964 +++
libopencm3/include/libopencm3/lpc43xx/creg.h | 354 +
.../include/libopencm3/lpc43xx/doc-lpc43xx.h | 32 +
.../include/libopencm3/lpc43xx/eventrouter.h | 70 +
libopencm3/include/libopencm3/lpc43xx/gima.h | 137 +
libopencm3/include/libopencm3/lpc43xx/gpdma.h | 552 ++
libopencm3/include/libopencm3/lpc43xx/gpio.h | 784 +++
libopencm3/include/libopencm3/lpc43xx/i2c.h | 164 +
libopencm3/include/libopencm3/lpc43xx/i2s.h | 122 +
libopencm3/include/libopencm3/lpc43xx/ipc.h | 30 +
libopencm3/include/libopencm3/lpc43xx/m0/irq.json | 36 +
libopencm3/include/libopencm3/lpc43xx/m4/irq.json | 54 +
libopencm3/include/libopencm3/lpc43xx/memorymap.h | 138 +
libopencm3/include/libopencm3/lpc43xx/rgu.h | 1206 ++++
libopencm3/include/libopencm3/lpc43xx/ritimer.h | 59 +
libopencm3/include/libopencm3/lpc43xx/scu.h | 780 +++
libopencm3/include/libopencm3/lpc43xx/sdio.h | 151 +
libopencm3/include/libopencm3/lpc43xx/sgpio.h | 691 ++
libopencm3/include/libopencm3/lpc43xx/ssp.h | 209 +
libopencm3/include/libopencm3/lpc43xx/timer.h | 270 +
libopencm3/include/libopencm3/lpc43xx/uart.h | 438 ++
libopencm3/include/libopencm3/lpc43xx/usb.h | 1337 ++++
libopencm3/include/libopencm3/lpc43xx/wwdt.h | 65 +
libopencm3/include/libopencm3/sam/3a/irq.json | 52 +
libopencm3/include/libopencm3/sam/3a/memorymap.h | 77 +
libopencm3/include/libopencm3/sam/3n/irq.json | 39 +
libopencm3/include/libopencm3/sam/3n/memorymap.h | 60 +
libopencm3/include/libopencm3/sam/3s/irq.json | 42 +
libopencm3/include/libopencm3/sam/3s/memorymap.h | 66 +
libopencm3/include/libopencm3/sam/3u/irq.json | 37 +
libopencm3/include/libopencm3/sam/3u/memorymap.h | 63 +
libopencm3/include/libopencm3/sam/3x/irq.json | 52 +
libopencm3/include/libopencm3/sam/3x/memorymap.h | 78 +
libopencm3/include/libopencm3/sam/eefc.h | 83 +
libopencm3/include/libopencm3/sam/gpio.h | 51 +
libopencm3/include/libopencm3/sam/memorymap.h | 39 +
libopencm3/include/libopencm3/sam/pio.h | 96 +
libopencm3/include/libopencm3/sam/pmc.h | 146 +
libopencm3/include/libopencm3/sam/pwm.h | 109 +
libopencm3/include/libopencm3/sam/tc.h | 52 +
libopencm3/include/libopencm3/sam/uart.h | 85 +
libopencm3/include/libopencm3/sam/usart.h | 217 +
libopencm3/include/libopencm3/sam/wdt.h | 57 +
libopencm3/include/libopencm3/stm32/adc.h | 36 +
libopencm3/include/libopencm3/stm32/can.h | 679 ++
libopencm3/include/libopencm3/stm32/cec.h | 28 +
.../libopencm3/stm32/common/adc_common_v1.h | 410 ++
.../libopencm3/stm32/common/crc_common_all.h | 118 +
.../libopencm3/stm32/common/crypto_common_f24.h | 290 +
.../libopencm3/stm32/common/dac_common_all.h | 422 ++
.../libopencm3/stm32/common/dma_common_f24.h | 626 ++
.../libopencm3/stm32/common/dma_common_l1f013.h | 425 ++
.../libopencm3/stm32/common/exti_common_all.h | 87 +
.../libopencm3/stm32/common/exti_common_l1f24.h | 45 +
.../libopencm3/stm32/common/flash_common_f01.h | 130 +
.../libopencm3/stm32/common/flash_common_f234.h | 93 +
.../libopencm3/stm32/common/flash_common_f24.h | 148 +
.../libopencm3/stm32/common/gpio_common_all.h | 91 +
.../libopencm3/stm32/common/gpio_common_f234.h | 272 +
.../libopencm3/stm32/common/gpio_common_f24.h | 111 +
.../libopencm3/stm32/common/hash_common_f24.h | 181 +
.../libopencm3/stm32/common/i2c_common_all.h | 401 ++
.../libopencm3/stm32/common/i2c_common_f24.h | 51 +
.../libopencm3/stm32/common/iwdg_common_all.h | 121 +
.../libopencm3/stm32/common/pwr_common_all.h | 132 +
.../libopencm3/stm32/common/rcc_common_all.h | 61 +
.../libopencm3/stm32/common/rng_common_f24.h | 71 +
.../libopencm3/stm32/common/rtc_common_l1f024.h | 347 +
.../libopencm3/stm32/common/spi_common_all.h | 405 ++
.../libopencm3/stm32/common/spi_common_f03.h | 124 +
.../libopencm3/stm32/common/spi_common_f24.h | 66 +
.../libopencm3/stm32/common/spi_common_l1f124.h | 65 +
.../libopencm3/stm32/common/syscfg_common_l1f234.h | 61 +
.../libopencm3/stm32/common/timer_common_all.h | 1129 ++++
.../libopencm3/stm32/common/timer_common_f24.h | 114 +
.../libopencm3/stm32/common/usart_common_all.h | 141 +
.../libopencm3/stm32/common/usart_common_f124.h | 288 +
.../libopencm3/stm32/common/usart_common_f24.h | 98 +
libopencm3/include/libopencm3/stm32/comparator.h | 28 +
libopencm3/include/libopencm3/stm32/crc.h | 38 +
libopencm3/include/libopencm3/stm32/crs.h | 28 +
libopencm3/include/libopencm3/stm32/crypto.h | 30 +
libopencm3/include/libopencm3/stm32/dac.h | 38 +
libopencm3/include/libopencm3/stm32/dbgmcu.h | 72 +
libopencm3/include/libopencm3/stm32/desig.h | 57 +
libopencm3/include/libopencm3/stm32/dma.h | 38 +
libopencm3/include/libopencm3/stm32/ethernet.h | 27 +
libopencm3/include/libopencm3/stm32/exti.h | 40 +
libopencm3/include/libopencm3/stm32/f0/adc.h | 352 +
libopencm3/include/libopencm3/stm32/f0/cec.h | 125 +
.../include/libopencm3/stm32/f0/comparator.h | 124 +
libopencm3/include/libopencm3/stm32/f0/crc.h | 89 +
libopencm3/include/libopencm3/stm32/f0/crs.h | 131 +
libopencm3/include/libopencm3/stm32/f0/dac.h | 117 +
libopencm3/include/libopencm3/stm32/f0/dma.h | 37 +
.../include/libopencm3/stm32/f0/doc-stm32f0.h | 32 +
libopencm3/include/libopencm3/stm32/f0/exti.h | 40 +
libopencm3/include/libopencm3/stm32/f0/flash.h | 116 +
libopencm3/include/libopencm3/stm32/f0/gpio.h | 75 +
libopencm3/include/libopencm3/stm32/f0/i2c.h | 256 +
libopencm3/include/libopencm3/stm32/f0/irq.json | 39 +
libopencm3/include/libopencm3/stm32/f0/iwdg.h | 70 +
libopencm3/include/libopencm3/stm32/f0/memorymap.h | 116 +
libopencm3/include/libopencm3/stm32/f0/pwr.h | 67 +
libopencm3/include/libopencm3/stm32/f0/rcc.h | 524 ++
libopencm3/include/libopencm3/stm32/f0/rtc.h | 36 +
libopencm3/include/libopencm3/stm32/f0/spi.h | 36 +
libopencm3/include/libopencm3/stm32/f0/syscfg.h | 110 +
libopencm3/include/libopencm3/stm32/f0/timer.h | 37 +
libopencm3/include/libopencm3/stm32/f0/tsc.h | 159 +
libopencm3/include/libopencm3/stm32/f0/usart.h | 343 +
libopencm3/include/libopencm3/stm32/f1/adc.h | 420 ++
libopencm3/include/libopencm3/stm32/f1/bkp.h | 205 +
libopencm3/include/libopencm3/stm32/f1/crc.h | 38 +
libopencm3/include/libopencm3/stm32/f1/dac.h | 37 +
libopencm3/include/libopencm3/stm32/f1/dma.h | 37 +
.../include/libopencm3/stm32/f1/doc-stm32f1.h | 32 +
libopencm3/include/libopencm3/stm32/f1/ethernet.h | 210 +
libopencm3/include/libopencm3/stm32/f1/exti.h | 41 +
libopencm3/include/libopencm3/stm32/f1/flash.h | 120 +
libopencm3/include/libopencm3/stm32/f1/gpio.h | 955 +++
libopencm3/include/libopencm3/stm32/f1/i2c.h | 37 +
libopencm3/include/libopencm3/stm32/f1/irq.json | 75 +
libopencm3/include/libopencm3/stm32/f1/iwdg.h | 39 +
libopencm3/include/libopencm3/stm32/f1/memorymap.h | 127 +
libopencm3/include/libopencm3/stm32/f1/pwr.h | 37 +
libopencm3/include/libopencm3/stm32/f1/rcc.h | 718 ++
libopencm3/include/libopencm3/stm32/f1/rtc.h | 170 +
libopencm3/include/libopencm3/stm32/f1/spi.h | 37 +
libopencm3/include/libopencm3/stm32/f1/timer.h | 56 +
libopencm3/include/libopencm3/stm32/f1/usart.h | 37 +
libopencm3/include/libopencm3/stm32/f2/crc.h | 38 +
libopencm3/include/libopencm3/stm32/f2/crypto.h | 36 +
libopencm3/include/libopencm3/stm32/f2/dac.h | 37 +
libopencm3/include/libopencm3/stm32/f2/dma.h | 37 +
.../include/libopencm3/stm32/f2/doc-stm32f2.h | 33 +
libopencm3/include/libopencm3/stm32/f2/exti.h | 41 +
libopencm3/include/libopencm3/stm32/f2/flash.h | 37 +
libopencm3/include/libopencm3/stm32/f2/gpio.h | 37 +
libopencm3/include/libopencm3/stm32/f2/hash.h | 36 +
libopencm3/include/libopencm3/stm32/f2/i2c.h | 37 +
libopencm3/include/libopencm3/stm32/f2/irq.json | 88 +
libopencm3/include/libopencm3/stm32/f2/iwdg.h | 39 +
libopencm3/include/libopencm3/stm32/f2/memorymap.h | 141 +
libopencm3/include/libopencm3/stm32/f2/pwr.h | 59 +
libopencm3/include/libopencm3/stm32/f2/rcc.h | 756 +++
libopencm3/include/libopencm3/stm32/f2/rng.h | 23 +
libopencm3/include/libopencm3/stm32/f2/rtc.h | 36 +
libopencm3/include/libopencm3/stm32/f2/spi.h | 37 +
libopencm3/include/libopencm3/stm32/f2/syscfg.h | 44 +
libopencm3/include/libopencm3/stm32/f2/timer.h | 39 +
libopencm3/include/libopencm3/stm32/f2/usart.h | 37 +
libopencm3/include/libopencm3/stm32/f3/adc.h | 939 +++
libopencm3/include/libopencm3/stm32/f3/crc.h | 70 +
libopencm3/include/libopencm3/stm32/f3/dac.h | 37 +
libopencm3/include/libopencm3/stm32/f3/dma.h | 37 +
.../include/libopencm3/stm32/f3/doc-stm32f3.h | 32 +
libopencm3/include/libopencm3/stm32/f3/exti.h | 51 +
libopencm3/include/libopencm3/stm32/f3/flash.h | 73 +
libopencm3/include/libopencm3/stm32/f3/gpio.h | 38 +
libopencm3/include/libopencm3/stm32/f3/i2c.h | 443 ++
libopencm3/include/libopencm3/stm32/f3/irq.json | 88 +
libopencm3/include/libopencm3/stm32/f3/iwdg.h | 53 +
libopencm3/include/libopencm3/stm32/f3/memorymap.h | 129 +
libopencm3/include/libopencm3/stm32/f3/pwr.h | 69 +
libopencm3/include/libopencm3/stm32/f3/rcc.h | 602 ++
libopencm3/include/libopencm3/stm32/f3/rtc.h | 42 +
libopencm3/include/libopencm3/stm32/f3/spi.h | 36 +
libopencm3/include/libopencm3/stm32/f3/syscfg.h | 41 +
libopencm3/include/libopencm3/stm32/f3/timer.h | 39 +
libopencm3/include/libopencm3/stm32/f3/usart.h | 527 ++
libopencm3/include/libopencm3/stm32/f4/adc.h | 586 ++
libopencm3/include/libopencm3/stm32/f4/crc.h | 38 +
libopencm3/include/libopencm3/stm32/f4/crypto.h | 97 +
libopencm3/include/libopencm3/stm32/f4/dac.h | 37 +
libopencm3/include/libopencm3/stm32/f4/dma.h | 37 +
.../include/libopencm3/stm32/f4/doc-stm32f4.h | 32 +
libopencm3/include/libopencm3/stm32/f4/exti.h | 41 +
libopencm3/include/libopencm3/stm32/f4/flash.h | 37 +
libopencm3/include/libopencm3/stm32/f4/fmc.h | 247 +
libopencm3/include/libopencm3/stm32/f4/gpio.h | 37 +
libopencm3/include/libopencm3/stm32/f4/hash.h | 36 +
libopencm3/include/libopencm3/stm32/f4/i2c.h | 37 +
libopencm3/include/libopencm3/stm32/f4/irq.json | 98 +
libopencm3/include/libopencm3/stm32/f4/iwdg.h | 39 +
libopencm3/include/libopencm3/stm32/f4/memorymap.h | 155 +
libopencm3/include/libopencm3/stm32/f4/pwr.h | 86 +
libopencm3/include/libopencm3/stm32/f4/rcc.h | 784 +++
libopencm3/include/libopencm3/stm32/f4/rng.h | 23 +
libopencm3/include/libopencm3/stm32/f4/rtc.h | 45 +
libopencm3/include/libopencm3/stm32/f4/spi.h | 37 +
libopencm3/include/libopencm3/stm32/f4/syscfg.h | 41 +
libopencm3/include/libopencm3/stm32/f4/timer.h | 39 +
libopencm3/include/libopencm3/stm32/f4/usart.h | 37 +
libopencm3/include/libopencm3/stm32/flash.h | 38 +
libopencm3/include/libopencm3/stm32/fsmc.h | 308 +
libopencm3/include/libopencm3/stm32/gpio.h | 38 +
libopencm3/include/libopencm3/stm32/hash.h | 30 +
libopencm3/include/libopencm3/stm32/i2c.h | 38 +
libopencm3/include/libopencm3/stm32/iwdg.h | 38 +
libopencm3/include/libopencm3/stm32/l1/adc.h | 227 +
libopencm3/include/libopencm3/stm32/l1/crc.h | 38 +
libopencm3/include/libopencm3/stm32/l1/dac.h | 37 +
libopencm3/include/libopencm3/stm32/l1/dma.h | 42 +
.../include/libopencm3/stm32/l1/doc-stm32l1.h | 32 +
libopencm3/include/libopencm3/stm32/l1/exti.h | 41 +
libopencm3/include/libopencm3/stm32/l1/flash.h | 156 +
libopencm3/include/libopencm3/stm32/l1/gpio.h | 263 +
libopencm3/include/libopencm3/stm32/l1/i2c.h | 37 +
libopencm3/include/libopencm3/stm32/l1/irq.json | 64 +
libopencm3/include/libopencm3/stm32/l1/iwdg.h | 39 +
libopencm3/include/libopencm3/stm32/l1/lcd.h | 231 +
libopencm3/include/libopencm3/stm32/l1/memorymap.h | 126 +
libopencm3/include/libopencm3/stm32/l1/pwr.h | 111 +
libopencm3/include/libopencm3/stm32/l1/rcc.h | 612 ++
libopencm3/include/libopencm3/stm32/l1/rtc.h | 36 +
libopencm3/include/libopencm3/stm32/l1/spi.h | 37 +
libopencm3/include/libopencm3/stm32/l1/syscfg.h | 41 +
libopencm3/include/libopencm3/stm32/l1/timer.h | 89 +
libopencm3/include/libopencm3/stm32/l1/usart.h | 37 +
libopencm3/include/libopencm3/stm32/memorymap.h | 39 +
libopencm3/include/libopencm3/stm32/otg_fs.h | 350 +
libopencm3/include/libopencm3/stm32/otg_hs.h | 398 ++
libopencm3/include/libopencm3/stm32/pwr.h | 38 +
libopencm3/include/libopencm3/stm32/rcc.h | 38 +
libopencm3/include/libopencm3/stm32/rtc.h | 36 +
libopencm3/include/libopencm3/stm32/sdio.h | 425 ++
libopencm3/include/libopencm3/stm32/spi.h | 38 +
libopencm3/include/libopencm3/stm32/syscfg.h | 36 +
libopencm3/include/libopencm3/stm32/timer.h | 40 +
libopencm3/include/libopencm3/stm32/tools.h | 65 +
libopencm3/include/libopencm3/stm32/tsc.h | 28 +
libopencm3/include/libopencm3/stm32/usart.h | 38 +
libopencm3/include/libopencm3/stm32/usb.h | 303 +
libopencm3/include/libopencm3/stm32/usb_desc.h | 101 +
libopencm3/include/libopencm3/stm32/wwdg.h | 83 +
libopencm3/include/libopencm3/usb/cdc.h | 162 +
libopencm3/include/libopencm3/usb/dfu.h | 102 +
libopencm3/include/libopencm3/usb/doc-usb.h | 32 +
libopencm3/include/libopencm3/usb/hid.h | 59 +
libopencm3/include/libopencm3/usb/msc.h | 93 +
libopencm3/include/libopencm3/usb/usbd.h | 120 +
libopencm3/include/libopencm3/usb/usbstd.h | 255 +
libopencm3/include/libopencmsis/core_cm3.h | 183 +
.../include/libopencmsis/dispatch/irqhandlers.h | 50 +
libopencm3/ld/Makefile.example | 46 +
libopencm3/ld/Makefile.linker | 71 +
libopencm3/ld/README | 157 +
libopencm3/ld/devices.data | 389 ++
libopencm3/ld/linker.ld.S | 193 +
libopencm3/ld/tests/dash.data | 1 +
libopencm3/ld/tests/dash.result | 1 +
libopencm3/ld/tests/longline.data | 2 +
libopencm3/ld/tests/longline.result | 1 +
libopencm3/ld/tests/single.data | 1 +
libopencm3/ld/tests/single.result | 1 +
libopencm3/ld/tests/tree1.data | 2 +
libopencm3/ld/tests/tree1.result | 1 +
libopencm3/ld/tests/tree5.data | 5 +
libopencm3/ld/tests/tree5.result | 1 +
libopencm3/ld/tests/twomatch.data | 4 +
libopencm3/ld/tests/twomatch.result | 1 +
libopencm3/lib/Makefile.include | 52 +
libopencm3/lib/cm3/assert.c | 34 +
libopencm3/lib/cm3/dwt.c | 77 +
libopencm3/lib/cm3/nvic.c | 199 +
libopencm3/lib/cm3/scb.c | 47 +
libopencm3/lib/cm3/sync.c | 73 +
libopencm3/lib/cm3/systick.c | 203 +
libopencm3/lib/cm3/vector.c | 121 +
libopencm3/lib/dispatch/vector_chipset.c | 12 +
libopencm3/lib/efm32/efm32g/Makefile | 43 +
libopencm3/lib/efm32/efm32g/libopencm3_efm32g.ld | 106 +
.../lib/efm32/efm32g/libopencm3_efm32g880f128.ld | 15 +
libopencm3/lib/efm32/efm32gg/Makefile | 43 +
libopencm3/lib/efm32/efm32gg/libopencm3_efm32gg.ld | 106 +
.../efm32/efm32gg/libopencm3_efm32gg990f1024.ld | 15 +
libopencm3/lib/efm32/efm32lg/Makefile | 43 +
libopencm3/lib/efm32/efm32lg/libopencm3_efm32lg.ld | 106 +
libopencm3/lib/efm32/efm32tg/Makefile | 43 +
libopencm3/lib/efm32/efm32tg/libopencm3_efm32tg.ld | 106 +
.../lib/efm32/efm32tg/libopencm3_efm32tg840f32.ld | 15 +
libopencm3/lib/ethernet/mac.c | 43 +
libopencm3/lib/ethernet/mac_stm32fxx7.c | 378 ++
libopencm3/lib/ethernet/phy.c | 64 +
libopencm3/lib/ethernet/phy_ksz8051mll.c | 89 +
libopencm3/lib/lm3s/Makefile | 40 +
libopencm3/lib/lm3s/gpio.c | 52 +
libopencm3/lib/lm3s/libopencm3_lm3s.ld | 106 +
libopencm3/lib/lm4f/Makefile | 43 +
libopencm3/lib/lm4f/gpio.c | 598 ++
libopencm3/lib/lm4f/libopencm3_lm4f.ld | 2 +
libopencm3/lib/lm4f/rcc.c | 499 ++
libopencm3/lib/lm4f/systemcontrol.c | 40 +
libopencm3/lib/lm4f/uart.c | 627 ++
libopencm3/lib/lm4f/usb_lm4f.c | 651 ++
libopencm3/lib/lpc13xx/Makefile | 40 +
libopencm3/lib/lpc13xx/gpio.c | 42 +
libopencm3/lib/lpc13xx/libopencm3_lpc13xx.ld | 106 +
libopencm3/lib/lpc17xx/Makefile | 40 +
libopencm3/lib/lpc17xx/gpio.c | 48 +
libopencm3/lib/lpc17xx/libopencm3_lpc17xx.ld | 106 +
libopencm3/lib/lpc43xx/gpio.c | 53 +
libopencm3/lib/lpc43xx/i2c.c | 102 +
libopencm3/lib/lpc43xx/ipc.c | 58 +
libopencm3/lib/lpc43xx/m0/Makefile | 43 +
libopencm3/lib/lpc43xx/m0/libopencm3_lpc43xx_m0.ld | 0
.../lpc43xx/m0/libopencm3_lpc43xx_ram_only_m0.ld | 96 +
libopencm3/lib/lpc43xx/m4/Makefile | 50 +
libopencm3/lib/lpc43xx/m4/libopencm3_lpc43xx.ld | 127 +
.../lib/lpc43xx/m4/libopencm3_lpc43xx_ram_only.ld | 139 +
.../lpc43xx/m4/libopencm3_lpc43xx_rom_to_ram.ld | 128 +
libopencm3/lib/lpc43xx/m4/vector_chipset.c | 48 +
libopencm3/lib/lpc43xx/scu.c | 52 +
libopencm3/lib/lpc43xx/ssp.c | 140 +
libopencm3/lib/lpc43xx/timer.c | 72 +
libopencm3/lib/lpc43xx/uart.c | 243 +
libopencm3/lib/sam/3a/Makefile | 37 +
libopencm3/lib/sam/3a/libopencm3_sam3a.ld | 106 +
libopencm3/lib/sam/3n/Makefile | 37 +
libopencm3/lib/sam/3n/libopencm3_sam3n.ld | 106 +
libopencm3/lib/sam/3s/Makefile | 38 +
libopencm3/lib/sam/3s/libopencm3_sam3s.ld | 106 +
libopencm3/lib/sam/3u/Makefile | 38 +
libopencm3/lib/sam/3u/libopencm3_sam3u.ld | 106 +
libopencm3/lib/sam/3x/Makefile | 37 +
libopencm3/lib/sam/3x/libopencm3_sam3x.ld | 106 +
libopencm3/lib/sam/common/gpio.c | 64 +
libopencm3/lib/sam/common/pmc.c | 97 +
libopencm3/lib/sam/common/usart.c | 110 +
libopencm3/lib/stm32/can.c | 557 ++
libopencm3/lib/stm32/common/adc_common_v1.c | 755 +++
libopencm3/lib/stm32/common/crc_common_all.c | 81 +
libopencm3/lib/stm32/common/crypto_common_f24.c | 175 +
libopencm3/lib/stm32/common/dac_common_all.c | 503 ++
libopencm3/lib/stm32/common/dma_common_f24.c | 794 +++
libopencm3/lib/stm32/common/dma_common_l1f013.c | 435 ++
libopencm3/lib/stm32/common/exti_common_all.c | 154 +
libopencm3/lib/stm32/common/flash_common_f01.c | 235 +
libopencm3/lib/stm32/common/flash_common_f234.c | 121 +
libopencm3/lib/stm32/common/flash_common_f24.c | 416 ++
libopencm3/lib/stm32/common/gpio_common_all.c | 151 +
libopencm3/lib/stm32/common/gpio_common_f0234.c | 206 +
libopencm3/lib/stm32/common/hash_common_f24.c | 163 +
libopencm3/lib/stm32/common/i2c_common_all.c | 419 ++
libopencm3/lib/stm32/common/iwdg_common_all.c | 149 +
libopencm3/lib/stm32/common/pwr_common_all.c | 205 +
libopencm3/lib/stm32/common/rcc_common_all.c | 188 +
libopencm3/lib/stm32/common/rtc_common_l1f024.c | 123 +
libopencm3/lib/stm32/common/spi_common_all.c | 710 ++
libopencm3/lib/stm32/common/spi_common_f03.c | 177 +
libopencm3/lib/stm32/common/spi_common_l1f124.c | 137 +
libopencm3/lib/stm32/common/timer_common_all.c | 2177 ++++++
libopencm3/lib/stm32/common/timer_common_f234.c | 58 +
libopencm3/lib/stm32/common/timer_common_f24.c | 53 +
libopencm3/lib/stm32/common/usart_common_all.c | 367 +
libopencm3/lib/stm32/common/usart_common_f124.c | 143 +
libopencm3/lib/stm32/desig.c | 54 +
libopencm3/lib/stm32/f0/Makefile | 49 +
libopencm3/lib/stm32/f0/adc.c | 835 +++
libopencm3/lib/stm32/f0/comparator.c | 64 +
libopencm3/lib/stm32/f0/crc.c | 31 +
libopencm3/lib/stm32/f0/crs.c | 32 +
libopencm3/lib/stm32/f0/dac.c | 31 +
libopencm3/lib/stm32/f0/dma.c | 31 +
libopencm3/lib/stm32/f0/flash.c | 157 +
libopencm3/lib/stm32/f0/gpio.c | 31 +
libopencm3/lib/stm32/f0/i2c.c | 32 +
libopencm3/lib/stm32/f0/iwdg.c | 31 +
libopencm3/lib/stm32/f0/libopencm3_stm32f0.ld | 106 +
libopencm3/lib/stm32/f0/pwr.c | 38 +
libopencm3/lib/stm32/f0/rcc.c | 665 ++
libopencm3/lib/stm32/f0/rtc.c | 31 +
libopencm3/lib/stm32/f0/spi.c | 31 +
libopencm3/lib/stm32/f0/syscfg.c | 31 +
libopencm3/lib/stm32/f0/timer.c | 34 +
libopencm3/lib/stm32/f0/usart.c | 429 ++
libopencm3/lib/stm32/f1/Makefile | 53 +
libopencm3/lib/stm32/f1/adc.c | 452 ++
libopencm3/lib/stm32/f1/crc.c | 31 +
libopencm3/lib/stm32/f1/dac.c | 31 +
libopencm3/lib/stm32/f1/dma.c | 31 +
libopencm3/lib/stm32/f1/ethernet.c | 52 +
libopencm3/lib/stm32/f1/flash.c | 306 +
libopencm3/lib/stm32/f1/gpio.c | 194 +
libopencm3/lib/stm32/f1/i2c.c | 31 +
libopencm3/lib/stm32/f1/iwdg.c | 31 +
libopencm3/lib/stm32/f1/libopencm3_stm32f1.ld | 106 +
libopencm3/lib/stm32/f1/pwr.c | 43 +
libopencm3/lib/stm32/f1/rcc.c | 1106 +++
libopencm3/lib/stm32/f1/rtc.c | 305 +
libopencm3/lib/stm32/f1/spi.c | 31 +
libopencm3/lib/stm32/f1/stm32f100x4.ld | 31 +
libopencm3/lib/stm32/f1/stm32f100x6.ld | 31 +
libopencm3/lib/stm32/f1/stm32f100x8.ld | 31 +
libopencm3/lib/stm32/f1/stm32f100xb.ld | 31 +
libopencm3/lib/stm32/f1/stm32f100xc.ld | 31 +
libopencm3/lib/stm32/f1/stm32f100xd.ld | 31 +
libopencm3/lib/stm32/f1/stm32f100xe.ld | 31 +
libopencm3/lib/stm32/f1/timer.c | 57 +
libopencm3/lib/stm32/f1/usart.c | 31 +
libopencm3/lib/stm32/f2/Makefile | 52 +
libopencm3/lib/stm32/f2/crc.c | 33 +
libopencm3/lib/stm32/f2/crypto.c | 31 +
libopencm3/lib/stm32/f2/dac.c | 31 +
libopencm3/lib/stm32/f2/dma.c | 31 +
libopencm3/lib/stm32/f2/flash.c | 53 +
libopencm3/lib/stm32/f2/gpio.c | 31 +
libopencm3/lib/stm32/f2/hash.c | 31 +
libopencm3/lib/stm32/f2/i2c.c | 33 +
libopencm3/lib/stm32/f2/iwdg.c | 31 +
libopencm3/lib/stm32/f2/libopencm3_stm32f2.ld | 106 +
libopencm3/lib/stm32/f2/pwr.c | 39 +
libopencm3/lib/stm32/f2/rcc.c | 417 ++
libopencm3/lib/stm32/f2/rtc.c | 31 +
libopencm3/lib/stm32/f2/spi.c | 31 +
libopencm3/lib/stm32/f2/timer.c | 38 +
libopencm3/lib/stm32/f2/usart.c | 31 +
libopencm3/lib/stm32/f3/Makefile | 50 +
libopencm3/lib/stm32/f3/adc.c | 1150 ++++
libopencm3/lib/stm32/f3/crc.c | 33 +
libopencm3/lib/stm32/f3/dac.c | 31 +
libopencm3/lib/stm32/f3/dma.c | 31 +
libopencm3/lib/stm32/f3/flash.c | 63 +
libopencm3/lib/stm32/f3/i2c.c | 486 ++
libopencm3/lib/stm32/f3/iwdg.c | 31 +
libopencm3/lib/stm32/f3/libopencm3_stm32f3.ld | 106 +
libopencm3/lib/stm32/f3/pwr.c | 40 +
libopencm3/lib/stm32/f3/rcc.c | 465 ++
libopencm3/lib/stm32/f3/rtc.c | 38 +
libopencm3/lib/stm32/f3/spi.c | 31 +
libopencm3/lib/stm32/f3/timer.c | 33 +
libopencm3/lib/stm32/f3/usart.c | 140 +
libopencm3/lib/stm32/f3/vector_chipset.c | 27 +
libopencm3/lib/stm32/f4/Makefile | 59 +
libopencm3/lib/stm32/f4/adc.c | 437 ++
libopencm3/lib/stm32/f4/crc.c | 33 +
libopencm3/lib/stm32/f4/crypto.c | 66 +
libopencm3/lib/stm32/f4/dac.c | 31 +
libopencm3/lib/stm32/f4/dma.c | 31 +
libopencm3/lib/stm32/f4/flash.c | 53 +
libopencm3/lib/stm32/f4/fmc.c | 99 +
libopencm3/lib/stm32/f4/gpio.c | 31 +
libopencm3/lib/stm32/f4/hash.c | 31 +
libopencm3/lib/stm32/f4/i2c.c | 31 +
libopencm3/lib/stm32/f4/iwdg.c | 31 +
libopencm3/lib/stm32/f4/libopencm3_stm32f4.ld | 106 +
libopencm3/lib/stm32/f4/pwr.c | 46 +
libopencm3/lib/stm32/f4/rcc.c | 539 ++
libopencm3/lib/stm32/f4/rtc.c | 97 +
libopencm3/lib/stm32/f4/spi.c | 31 +
libopencm3/lib/stm32/f4/stm32f405x6.ld | 33 +
libopencm3/lib/stm32/f4/timer.c | 38 +
libopencm3/lib/stm32/f4/usart.c | 31 +
libopencm3/lib/stm32/f4/vector_chipset.c | 27 +
libopencm3/lib/stm32/l1/Makefile | 52 +
libopencm3/lib/stm32/l1/adc.c | 201 +
libopencm3/lib/stm32/l1/crc.c | 33 +
libopencm3/lib/stm32/l1/dac.c | 31 +
libopencm3/lib/stm32/l1/dma.c | 31 +
libopencm3/lib/stm32/l1/flash.c | 208 +
libopencm3/lib/stm32/l1/gpio.c | 31 +
libopencm3/lib/stm32/l1/i2c.c | 31 +
libopencm3/lib/stm32/l1/iwdg.c | 31 +
libopencm3/lib/stm32/l1/lcd.c | 154 +
libopencm3/lib/stm32/l1/libopencm3_stm32l1.ld | 106 +
libopencm3/lib/stm32/l1/pwr.c | 58 +
libopencm3/lib/stm32/l1/rcc.c | 534 ++
libopencm3/lib/stm32/l1/rtc.c | 31 +
libopencm3/lib/stm32/l1/spi.c | 31 +
libopencm3/lib/stm32/l1/stm32l15xx6.ld | 32 +
libopencm3/lib/stm32/l1/stm32l15xx8.ld | 32 +
libopencm3/lib/stm32/l1/stm32l15xxb.ld | 32 +
libopencm3/lib/stm32/l1/stm32l15xxc.ld | 32 +
libopencm3/lib/stm32/l1/stm32l15xxd.ld | 32 +
libopencm3/lib/stm32/l1/timer.c | 59 +
libopencm3/lib/stm32/l1/usart.c | 31 +
libopencm3/lib/usb/usb.c | 175 +
libopencm3/lib/usb/usb_control.c | 288 +
libopencm3/lib/usb/usb_f103.c | 346 +
libopencm3/lib/usb/usb_f107.c | 91 +
libopencm3/lib/usb/usb_f207.c | 91 +
libopencm3/lib/usb/usb_fx07_common.c | 338 +
libopencm3/lib/usb/usb_fx07_common.h | 39 +
libopencm3/lib/usb/usb_msc.c | 814 +++
libopencm3/lib/usb/usb_private.h | 163 +
libopencm3/lib/usb/usb_standard.c | 532 ++
libopencm3/locm3.sublime-project | 35 +
libopencm3/mk/README | 119 +
libopencm3/mk/gcc-config.mk | 37 +
libopencm3/mk/gcc-rules.mk | 56 +
libopencm3/mk/genlink-config.mk | 34 +
libopencm3/mk/genlink-rules.mk | 25 +
libopencm3/scripts/black_magic_probe_debug.scr | 4 +
libopencm3/scripts/black_magic_probe_flash.scr | 4 +
libopencm3/scripts/checkpatch.pl | 3731 +++++++++++
libopencm3/scripts/data/lpc43xx/README | 23 +
libopencm3/scripts/data/lpc43xx/adc.yaml | 607 ++
libopencm3/scripts/data/lpc43xx/atimer.yaml | 71 +
libopencm3/scripts/data/lpc43xx/ccu.yaml | 2391 +++++++
libopencm3/scripts/data/lpc43xx/cgu.yaml | 937 +++
libopencm3/scripts/data/lpc43xx/creg.yaml | 312 +
libopencm3/scripts/data/lpc43xx/csv2yaml.py | 37 +
libopencm3/scripts/data/lpc43xx/eventrouter.yaml | 959 +++
libopencm3/scripts/data/lpc43xx/gen.py | 29 +
libopencm3/scripts/data/lpc43xx/gima.yaml | 961 +++
libopencm3/scripts/data/lpc43xx/gpdma.yaml | 1498 +++++
libopencm3/scripts/data/lpc43xx/gpio.yaml | 4926 ++++++++++++++
libopencm3/scripts/data/lpc43xx/i2c.yaml | 415 ++
libopencm3/scripts/data/lpc43xx/i2s.yaml | 619 ++
libopencm3/scripts/data/lpc43xx/rgu.yaml | 1199 ++++
libopencm3/scripts/data/lpc43xx/ritimer.yaml | 51 +
libopencm3/scripts/data/lpc43xx/scu.yaml | 7063 ++++++++++++++++++++
libopencm3/scripts/data/lpc43xx/sgpio.yaml | 1953 ++++++
libopencm3/scripts/data/lpc43xx/ssp.yaml | 445 ++
libopencm3/scripts/data/lpc43xx/usb.yaml | 1416 ++++
libopencm3/scripts/data/lpc43xx/yaml_odict.py | 81 +
libopencm3/scripts/genlink.awk | 65 +
libopencm3/scripts/genlinktest.sh | 39 +
libopencm3/scripts/irq2nvic_h | 174 +
libopencm3/scripts/lpcvtcksum | 51 +
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create mode 100644 libopencm3/lib/stm32/f0/timer.c
create mode 100644 libopencm3/lib/stm32/f0/usart.c
create mode 100644 libopencm3/lib/stm32/f1/Makefile
create mode 100644 libopencm3/lib/stm32/f1/adc.c
create mode 100644 libopencm3/lib/stm32/f1/crc.c
create mode 100644 libopencm3/lib/stm32/f1/dac.c
create mode 100644 libopencm3/lib/stm32/f1/dma.c
create mode 100644 libopencm3/lib/stm32/f1/ethernet.c
create mode 100644 libopencm3/lib/stm32/f1/flash.c
create mode 100644 libopencm3/lib/stm32/f1/gpio.c
create mode 100644 libopencm3/lib/stm32/f1/i2c.c
create mode 100644 libopencm3/lib/stm32/f1/iwdg.c
create mode 100644 libopencm3/lib/stm32/f1/libopencm3_stm32f1.ld
create mode 100644 libopencm3/lib/stm32/f1/pwr.c
create mode 100644 libopencm3/lib/stm32/f1/rcc.c
create mode 100644 libopencm3/lib/stm32/f1/rtc.c
create mode 100644 libopencm3/lib/stm32/f1/spi.c
create mode 100644 libopencm3/lib/stm32/f1/stm32f100x4.ld
create mode 100644 libopencm3/lib/stm32/f1/stm32f100x6.ld
create mode 100644 libopencm3/lib/stm32/f1/stm32f100x8.ld
create mode 100644 libopencm3/lib/stm32/f1/stm32f100xb.ld
create mode 100644 libopencm3/lib/stm32/f1/stm32f100xc.ld
create mode 100644 libopencm3/lib/stm32/f1/stm32f100xd.ld
create mode 100644 libopencm3/lib/stm32/f1/stm32f100xe.ld
create mode 100644 libopencm3/lib/stm32/f1/timer.c
create mode 100644 libopencm3/lib/stm32/f1/usart.c
create mode 100644 libopencm3/lib/stm32/f2/Makefile
create mode 100644 libopencm3/lib/stm32/f2/crc.c
create mode 100644 libopencm3/lib/stm32/f2/crypto.c
create mode 100644 libopencm3/lib/stm32/f2/dac.c
create mode 100644 libopencm3/lib/stm32/f2/dma.c
create mode 100644 libopencm3/lib/stm32/f2/flash.c
create mode 100644 libopencm3/lib/stm32/f2/gpio.c
create mode 100644 libopencm3/lib/stm32/f2/hash.c
create mode 100644 libopencm3/lib/stm32/f2/i2c.c
create mode 100644 libopencm3/lib/stm32/f2/iwdg.c
create mode 100644 libopencm3/lib/stm32/f2/libopencm3_stm32f2.ld
create mode 100644 libopencm3/lib/stm32/f2/pwr.c
create mode 100644 libopencm3/lib/stm32/f2/rcc.c
create mode 100644 libopencm3/lib/stm32/f2/rtc.c
create mode 100644 libopencm3/lib/stm32/f2/spi.c
create mode 100644 libopencm3/lib/stm32/f2/timer.c
create mode 100644 libopencm3/lib/stm32/f2/usart.c
create mode 100644 libopencm3/lib/stm32/f3/Makefile
create mode 100644 libopencm3/lib/stm32/f3/adc.c
create mode 100644 libopencm3/lib/stm32/f3/crc.c
create mode 100644 libopencm3/lib/stm32/f3/dac.c
create mode 100644 libopencm3/lib/stm32/f3/dma.c
create mode 100644 libopencm3/lib/stm32/f3/flash.c
create mode 100644 libopencm3/lib/stm32/f3/i2c.c
create mode 100644 libopencm3/lib/stm32/f3/iwdg.c
create mode 100644 libopencm3/lib/stm32/f3/libopencm3_stm32f3.ld
create mode 100644 libopencm3/lib/stm32/f3/pwr.c
create mode 100644 libopencm3/lib/stm32/f3/rcc.c
create mode 100644 libopencm3/lib/stm32/f3/rtc.c
create mode 100644 libopencm3/lib/stm32/f3/spi.c
create mode 100644 libopencm3/lib/stm32/f3/timer.c
create mode 100644 libopencm3/lib/stm32/f3/usart.c
create mode 100644 libopencm3/lib/stm32/f3/vector_chipset.c
create mode 100644 libopencm3/lib/stm32/f4/Makefile
create mode 100644 libopencm3/lib/stm32/f4/adc.c
create mode 100644 libopencm3/lib/stm32/f4/crc.c
create mode 100644 libopencm3/lib/stm32/f4/crypto.c
create mode 100644 libopencm3/lib/stm32/f4/dac.c
create mode 100644 libopencm3/lib/stm32/f4/dma.c
create mode 100644 libopencm3/lib/stm32/f4/flash.c
create mode 100644 libopencm3/lib/stm32/f4/fmc.c
create mode 100644 libopencm3/lib/stm32/f4/gpio.c
create mode 100644 libopencm3/lib/stm32/f4/hash.c
create mode 100644 libopencm3/lib/stm32/f4/i2c.c
create mode 100644 libopencm3/lib/stm32/f4/iwdg.c
create mode 100644 libopencm3/lib/stm32/f4/libopencm3_stm32f4.ld
create mode 100644 libopencm3/lib/stm32/f4/pwr.c
create mode 100644 libopencm3/lib/stm32/f4/rcc.c
create mode 100644 libopencm3/lib/stm32/f4/rtc.c
create mode 100644 libopencm3/lib/stm32/f4/spi.c
create mode 100644 libopencm3/lib/stm32/f4/stm32f405x6.ld
create mode 100644 libopencm3/lib/stm32/f4/timer.c
create mode 100644 libopencm3/lib/stm32/f4/usart.c
create mode 100644 libopencm3/lib/stm32/f4/vector_chipset.c
create mode 100644 libopencm3/lib/stm32/l1/Makefile
create mode 100644 libopencm3/lib/stm32/l1/adc.c
create mode 100644 libopencm3/lib/stm32/l1/crc.c
create mode 100644 libopencm3/lib/stm32/l1/dac.c
create mode 100644 libopencm3/lib/stm32/l1/dma.c
create mode 100644 libopencm3/lib/stm32/l1/flash.c
create mode 100644 libopencm3/lib/stm32/l1/gpio.c
create mode 100644 libopencm3/lib/stm32/l1/i2c.c
create mode 100644 libopencm3/lib/stm32/l1/iwdg.c
create mode 100644 libopencm3/lib/stm32/l1/lcd.c
create mode 100644 libopencm3/lib/stm32/l1/libopencm3_stm32l1.ld
create mode 100644 libopencm3/lib/stm32/l1/pwr.c
create mode 100644 libopencm3/lib/stm32/l1/rcc.c
create mode 100644 libopencm3/lib/stm32/l1/rtc.c
create mode 100644 libopencm3/lib/stm32/l1/spi.c
create mode 100644 libopencm3/lib/stm32/l1/stm32l15xx6.ld
create mode 100644 libopencm3/lib/stm32/l1/stm32l15xx8.ld
create mode 100644 libopencm3/lib/stm32/l1/stm32l15xxb.ld
create mode 100644 libopencm3/lib/stm32/l1/stm32l15xxc.ld
create mode 100644 libopencm3/lib/stm32/l1/stm32l15xxd.ld
create mode 100644 libopencm3/lib/stm32/l1/timer.c
create mode 100644 libopencm3/lib/stm32/l1/usart.c
create mode 100644 libopencm3/lib/usb/usb.c
create mode 100644 libopencm3/lib/usb/usb_control.c
create mode 100644 libopencm3/lib/usb/usb_f103.c
create mode 100644 libopencm3/lib/usb/usb_f107.c
create mode 100644 libopencm3/lib/usb/usb_f207.c
create mode 100644 libopencm3/lib/usb/usb_fx07_common.c
create mode 100644 libopencm3/lib/usb/usb_fx07_common.h
create mode 100644 libopencm3/lib/usb/usb_msc.c
create mode 100644 libopencm3/lib/usb/usb_private.h
create mode 100644 libopencm3/lib/usb/usb_standard.c
create mode 100644 libopencm3/locm3.sublime-project
create mode 100644 libopencm3/mk/README
create mode 100644 libopencm3/mk/gcc-config.mk
create mode 100644 libopencm3/mk/gcc-rules.mk
create mode 100644 libopencm3/mk/genlink-config.mk
create mode 100644 libopencm3/mk/genlink-rules.mk
create mode 100644 libopencm3/scripts/black_magic_probe_debug.scr
create mode 100644 libopencm3/scripts/black_magic_probe_flash.scr
create mode 100755 libopencm3/scripts/checkpatch.pl
create mode 100644 libopencm3/scripts/data/lpc43xx/README
create mode 100644 libopencm3/scripts/data/lpc43xx/adc.yaml
create mode 100644 libopencm3/scripts/data/lpc43xx/atimer.yaml
create mode 100644 libopencm3/scripts/data/lpc43xx/ccu.yaml
create mode 100644 libopencm3/scripts/data/lpc43xx/cgu.yaml
create mode 100644 libopencm3/scripts/data/lpc43xx/creg.yaml
create mode 100755 libopencm3/scripts/data/lpc43xx/csv2yaml.py
create mode 100644 libopencm3/scripts/data/lpc43xx/eventrouter.yaml
create mode 100755 libopencm3/scripts/data/lpc43xx/gen.py
create mode 100644 libopencm3/scripts/data/lpc43xx/gima.yaml
create mode 100644 libopencm3/scripts/data/lpc43xx/gpdma.yaml
create mode 100644 libopencm3/scripts/data/lpc43xx/gpio.yaml
create mode 100644 libopencm3/scripts/data/lpc43xx/i2c.yaml
create mode 100644 libopencm3/scripts/data/lpc43xx/i2s.yaml
create mode 100644 libopencm3/scripts/data/lpc43xx/rgu.yaml
create mode 100644 libopencm3/scripts/data/lpc43xx/ritimer.yaml
create mode 100644 libopencm3/scripts/data/lpc43xx/scu.yaml
create mode 100644 libopencm3/scripts/data/lpc43xx/sgpio.yaml
create mode 100644 libopencm3/scripts/data/lpc43xx/ssp.yaml
create mode 100644 libopencm3/scripts/data/lpc43xx/usb.yaml
create mode 100644 libopencm3/scripts/data/lpc43xx/yaml_odict.py
create mode 100644 libopencm3/scripts/genlink.awk
create mode 100644 libopencm3/scripts/genlinktest.sh
create mode 100755 libopencm3/scripts/irq2nvic_h
create mode 100755 libopencm3/scripts/lpcvtcksum
(limited to 'libopencm3')
diff --git a/libopencm3/.gitignore b/libopencm3/.gitignore
new file mode 100644
index 0000000..b13d129
--- /dev/null
+++ b/libopencm3/.gitignore
@@ -0,0 +1,38 @@
+*.d
+*.o
+*.bin
+*.hex
+*.list
+*.srec
+*.a
+*.elf
+lib/*.ld
+*.stylecheck
+*.swp
+\#*
+.\#*
+*~
+*.map
+*.log
+html/
+latex/
+*.pdf
+*.tag
+.DS_Store
+# These are generated
+include/libopencm3/**/nvic.h
+include/libopencm3/**/**/nvic.h
+lib/**/vector_nvic.c
+lib/**/**/vector_nvic.c
+include/libopencmsis/efm32/
+include/libopencmsis/lm3s/
+include/libopencmsis/lpc13xx/
+include/libopencmsis/lpc17xx/
+include/libopencmsis/lpc43xx/
+include/libopencmsis/sam/
+include/libopencmsis/stm32/
+
+# netbeans, intellij, eclipse project files
+netbeans
+.idea/
+.project
diff --git a/libopencm3/COPYING.GPL3 b/libopencm3/COPYING.GPL3
new file mode 100644
index 0000000..4432540
--- /dev/null
+++ b/libopencm3/COPYING.GPL3
@@ -0,0 +1,676 @@
+
+ GNU GENERAL PUBLIC LICENSE
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+ You should also get your employer (if you work as a programmer) or school,
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diff --git a/libopencm3/COPYING.LGPL3 b/libopencm3/COPYING.LGPL3
new file mode 100644
index 0000000..65c5ca8
--- /dev/null
+++ b/libopencm3/COPYING.LGPL3
@@ -0,0 +1,165 @@
+ GNU LESSER GENERAL PUBLIC LICENSE
+ Version 3, 29 June 2007
+
+ Copyright (C) 2007 Free Software Foundation, Inc.
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+
+ This version of the GNU Lesser General Public License incorporates
+the terms and conditions of version 3 of the GNU General Public
+License, supplemented by the additional permissions listed below.
+
+ 0. Additional Definitions.
+
+ As used herein, "this License" refers to version 3 of the GNU Lesser
+General Public License, and the "GNU GPL" refers to version 3 of the GNU
+General Public License.
+
+ "The Library" refers to a covered work governed by this License,
+other than an Application or a Combined Work as defined below.
+
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+received it does not specify a version number of the GNU Lesser
+General Public License, you may choose any version of the GNU Lesser
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+
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+Library.
diff --git a/libopencm3/HACKING b/libopencm3/HACKING
new file mode 100644
index 0000000..d5a24ee
--- /dev/null
+++ b/libopencm3/HACKING
@@ -0,0 +1,82 @@
+------------------------------------------------------------------------------
+HACKING
+------------------------------------------------------------------------------
+
+Coding style
+------------
+
+The whole library is programmed using the Linux kernel coding style, see
+http://lxr.linux.no/linux/Documentation/CodingStyle for details.
+
+Please use the same style for any code contributions, thanks!
+
+Amendments to the Linux kernel coding style
+-------------------------------------------
+
+1) We use the stdint types. The linux kernel accepts the abbreviated types (u8,
+ s8, u16 and so on) for legacy reasons. We should in general not introduce
+ things like types ourselves as long as they are not necessary to make our
+ job possible of refining the hardware and make it easier to be used. stdint
+ is a standard and it is not in the scope of our project to introduce a new
+ type standard.
+
+2) Based on the same logic as in (1) we do not use __packed and __aligned
+ definitions, it is not our job to add compiler extensions. If we need to
+ deal with compiler incompatibility we will do that the same way we are
+ dealing with the depricated attribute by introducing a normal macro that is
+ not in the compiler reserved keyword space.
+
+3) We accept to write an empty body busy waiting while loop like this:
+ while (1);
+ there is no need to put the colon on the next line as per linux kernel
+ style.
+
+4) We always add brackets around bodies of if, while and for statements, even
+ if the body contains only one expression. It is dangerous to not have them
+ as it easily happens that one adds a second expression and is hunting for
+ hours why the code is not working just because of a missing bracket pair.
+
+Development guidelines
+----------------------
+
+ - Every new file added must have the usual license header, see the
+ existing files for examples.
+
+ - In general, please try to keep the register and bit naming as close
+ as possible to the official vendor datasheets. Among other reasons, this
+ makes it easier for users to find what they're looking for in the
+ datasheets, programming manuals, and application notes.
+
+ - All register definitions should follow the following naming conventions:
+
+ - The #define names should be all-caps, parts are separated by
+ an underscore.
+
+ - The name should be of the form SUBSYSTEM_REGISTER_BIT, e.g.
+ ADC_CR2_DMA, where ADC is the subsystem name, CR2 is the register NAME,
+ and DMA is the name of the bit in the register that is defined.
+
+ - All subsystem-specific function names should be prefixed with the
+ subsystem name. For example, gpio_set_mode() or rcc_osc_on().
+
+ - Please consistently use the stdint types.
+
+ - Variables that are used to store register values read from registers or
+ to be stored in a register should be named reg8, reg16, reg32 etc.
+
+ - For examples on using libopencm3 see the libopencm3-examples repository.
+
+Tips and tricks
+---------------
+
+SublimeText users:
+
+ - The project contains a sublime project description file with some basic
+ settings provided to make hacking on libopencm3 easier.
+
+ - Recommended SublimeText plugins when hacking on libopencm3:
+
+ - TrailingSpaces: Show and trim trailing line spaces.
+
+ - SublimeLinter: Run checkpatch.pl in the background while you write your
+ code and indicate possible coding style issues on the fly.
diff --git a/libopencm3/HACKING_COMMON_DOC b/libopencm3/HACKING_COMMON_DOC
new file mode 100644
index 0000000..b0fa4b3
--- /dev/null
+++ b/libopencm3/HACKING_COMMON_DOC
@@ -0,0 +1,76 @@
+Files for each peripheral (examples given for STM32 GPIO)
+---------------------------------------------------------
+
+In include/libopencm3/stm32.
+A "dispatch" header to point to the subfamily header (gpio.h)
+
+In include/libopencm3/stm32/f*
+A file with defines that are specific to the subfamily, and an include of
+needed common header files (gpio.h).
+
+In include/libopencm3/stm32/common
+A file with defines common to all subfamilies. Includes the cm3 common header
+(gpio_common_all.h).
+
+In include/libopencm3/stm32/common
+May be one other file with defines common to a subgroup of devices.
+This includes the file common to all (gpio_common_f24.h).
+
+In lib/stm32/f*
+A file with functions specific to the subfamily. Includes the "dispatch" header
+and any common headers needed (gpio.c).
+
+In lib/stm32/common
+Has functions common to all subfamilies. Includes the "dispatch" header
+(gpio_common_all.c).
+
+In lib/stm32/common
+May be one other file with functions common to a group of subfamilies. Includes
+the "dispatch" header and the file common to all (gpio_common_f24.h).
+
+Makefiles in lib/stm32/f? have the common object files added and the
+common directory added to VPATH.
+
+NOTE: The common source files MUST have the "dispatch" header so that
+compilation will use the specific defines for the subfamily being compiled.
+These can differ between subfamilies.
+
+NOTE: The common source files must have a line of the form
+
+#ifdef LIBOPENCM3_xxx_H
+
+where xxx is the associated peripheral name. This prevents the common files
+from being included accidentally into a user's application. This however
+causes doxygen to skip processing of the remainder of the file. Thus a
+
+@cond ... @endcond
+
+directive must be placed around the statement to prevent doxygen from
+processing it. This works only for doxygen 1.8.4 or later. At the present
+time most distros have an earlier buggy version.
+
+Documentation
+-------------
+
+In include/libopencm3/stm32/f*
+A file doc-stm32f*.h contains a definition of the particular family grouping.
+This grouping will appear in the main index of the resulting document with all
+documentation under it.
+
+All header files for a peripheral (common or otherwise) will subgroup under a
+name which is the same in all families (such as gpio_defines). The peripheral
+header file in include/libopencm3/stm32/f* will then include this group as a
+subgroup under the specific family group. Doxygen is run separately for each
+family so there is no danger of accidentally including the wrong stuff.
+
+Similarly for the source files for a peripheral which will subgroup under a
+same name (such as gpio_files). The peripheral source file in lib/stm32/f*
+will include this as a subgroup under the specific family group.
+
+DOXYFILE for a particular family will list the family specific and common files
+(headers and source) that are to be included. The result (in the long run) will
+be that all peripherals will appear under the same family grouping in the
+documentation, even if they are identical over a number of families. That is
+probably most useful to end users who only need to see the documentation for
+one family.
+
diff --git a/libopencm3/Makefile b/libopencm3/Makefile
new file mode 100644
index 0000000..0edf3f7
--- /dev/null
+++ b/libopencm3/Makefile
@@ -0,0 +1,131 @@
+##
+## This file is part of the libopencm3 project.
+##
+## Copyright (C) 2009 Uwe Hermann
+##
+## This library is free software: you can redistribute it and/or modify
+## it under the terms of the GNU Lesser General Public License as published by
+## the Free Software Foundation, either version 3 of the License, or
+## (at your option) any later version.
+##
+## This library is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU Lesser General Public License for more details.
+##
+## You should have received a copy of the GNU Lesser General Public License
+## along with this library. If not, see .
+##
+
+PREFIX ?= arm-none-eabi
+#PREFIX ?= arm-elf
+
+STYLECHECK := scripts/checkpatch.pl
+STYLECHECKFLAGS := --no-tree -f --terse --mailback
+
+DESTDIR ?= /usr/local
+
+INCDIR := $(DESTDIR)/$(PREFIX)/include
+LIBDIR := $(DESTDIR)/$(PREFIX)/lib
+SHAREDIR := $(DESTDIR)/$(PREFIX)/share/libopencm3/scripts
+INSTALL := install
+
+space:=
+space+=
+SRCLIBDIR:= $(subst $(space),\$(space),$(realpath lib))
+
+TARGETS:= stm32/f0 stm32/f1 stm32/f2 stm32/f3 stm32/f4 stm32/l1 lpc13xx lpc17xx \
+ lpc43xx/m4 lpc43xx/m0 lm3s lm4f \
+ efm32/efm32tg efm32/efm32g efm32/efm32lg efm32/efm32gg \
+ sam/3a sam/3n sam/3s sam/3u sam/3x
+
+# Be silent per default, but 'make V=1' will show all compiler calls.
+ifneq ($(V),1)
+Q := @
+# Do not print "Entering directory ...".
+MAKEFLAGS += --no-print-directory
+endif
+
+IRQ_DEFN_FILES := $(shell find . -name 'irq.json')
+STYLECHECKFILES := $(shell find . -name '*.[ch]')
+
+all: build
+
+build: lib
+
+%.genhdr:
+ @printf " GENHDR $*\n";
+ @./scripts/irq2nvic_h ./$*;
+
+%.cleanhdr:
+ @printf " CLNHDR $*\n";
+ @./scripts/irq2nvic_h --remove ./$*
+
+LIB_DIRS:=$(wildcard $(addprefix lib/,$(TARGETS)))
+$(LIB_DIRS): $(IRQ_DEFN_FILES:=.genhdr)
+ @printf " BUILD $@\n";
+ $(Q)$(MAKE) --directory=$@ SRCLIBDIR="$(SRCLIBDIR)"
+
+lib: $(LIB_DIRS)
+ $(Q)true
+
+install: lib
+ @printf " INSTALL headers\n"
+ $(Q)$(INSTALL) -d $(INCDIR)/libopencm3
+ $(Q)$(INSTALL) -d $(INCDIR)/libopencmsis
+ $(Q)$(INSTALL) -d $(LIBDIR)
+ $(Q)$(INSTALL) -d $(SHAREDIR)
+ $(Q)cp -r include/libopencm3/* $(INCDIR)/libopencm3
+ $(Q)cp -r include/libopencmsis/* $(INCDIR)/libopencmsis
+ @printf " INSTALL libs\n"
+ $(Q)$(INSTALL) -m 0644 lib/*.a $(LIBDIR)
+ @printf " INSTALL ldscripts\n"
+ $(Q)$(INSTALL) -m 0644 lib/*.ld $(LIBDIR)
+ $(Q)$(INSTALL) -m 0644 lib/efm32/*/*.ld $(LIBDIR)
+ @printf " INSTALL scripts\n"
+ $(Q)$(INSTALL) -m 0644 scripts/*.scr $(SHAREDIR)
+
+
+html doc:
+ $(Q)$(MAKE) -C doc html
+
+clean: $(IRQ_DEFN_FILES:=.cleanhdr) $(LIB_DIRS:=.clean) $(EXAMPLE_DIRS:=.clean) doc.clean styleclean
+
+%.clean:
+ $(Q)if [ -d $* ]; then \
+ printf " CLEAN $*\n"; \
+ $(MAKE) -C $* clean SRCLIBDIR="$(SRCLIBDIR)" || exit $?; \
+ fi;
+
+
+stylecheck: $(STYLECHECKFILES:=.stylecheck)
+styleclean: $(STYLECHECKFILES:=.styleclean)
+
+# the cat is due to multithreaded nature - we like to have consistent chunks of text on the output
+%.stylecheck: %
+ $(Q)if ! grep -q "* It was generated by the irq2nvic_h script." $* ; then \
+ $(STYLECHECK) $(STYLECHECKFLAGS) $* > $*.stylecheck; \
+ if [ -s $*.stylecheck ]; then \
+ cat $*.stylecheck; \
+ else \
+ rm -f $*.stylecheck; \
+ fi; \
+ fi;
+
+%.styleclean:
+ $(Q)rm -f $*.stylecheck;
+
+
+LDTESTS :=$(wildcard ld/tests/*.data)
+
+genlinktests: $(LDTESTS:.data=.ldtest)
+
+%.ldtest:
+ @if ./scripts/genlinktest.sh $* >/dev/null; then\
+ printf " TEST OK : $*\n"; \
+ else \
+ printf " TEST FAIL : $*\n"; \
+ fi;
+
+
+.PHONY: build lib $(LIB_DIRS) install doc clean generatedheaders cleanheaders stylecheck genlinktests
diff --git a/libopencm3/README b/libopencm3/README
new file mode 100644
index 0000000..7323a76
--- /dev/null
+++ b/libopencm3/README
@@ -0,0 +1,159 @@
+------------------------------------------------------------------------------
+README
+------------------------------------------------------------------------------
+
+The libopencm3 project aims to create an open-source firmware library for
+various ARM Cortex-M3 microcontrollers.
+
+Currently (at least partly) supported microcontrollers:
+
+ - ST STM32F0xx/F1xx/F2xx/F30x/F37x/F4xx/L1xx series
+ - Atmel SAM3A/3N/3S/3U/3X series
+ - NXP LPC1311/13/42/43
+ - Stellaris LM3S series (discontinued, without replacement)
+ - TI (Tiva) LM4F series (continuing as TM4F, pin and peripheral compatible)
+ - EFM32 Gecko series (only core support)
+
+The library is written completely from scratch based on the vendor datasheets,
+programming manuals, and application notes. The code is meant to be used
+with a GCC toolchain for ARM (arm-elf or arm-none-eabi), flashing of the
+code to a microcontroller can be done using the OpenOCD ARM JTAG software.
+
+
+Status and API
+--------------
+
+The libopencm3 project is currently work in progress. Not all subsystems
+of the microcontrollers are supported, yet.
+
+IMPORTANT: The API of the library is NOT yet considered stable! Please do
+ not rely on it, yet! Changes to function names, macro names etc.
+ can happen at any time without prior notice!
+
+TIP: Include this repository as a GIT submodule in your project. To make sure
+ your users get the right version of the library to compile your project.
+ For how that can be done refer to the libopencm3-examples repository.
+
+Prerequisites
+-------------
+
+Building requires python. (Some code is generated)
+
+For Ubuntu/Fedora
+ An arm-none-eabi/arm-elf toolchain.
+
+For Windows
+ Download and install:
+ msys - sourceforge.net/projects/mingw/files/MSYS/Base/msys-core/msys-1.0.11/MSYS-1.0.11.exe
+ Python - http://www.python.org/ftp/python/2.7/python-2.7.msi (any 2.7 release)
+ arm-none-eabi/arm-elf toolchain
+
+ - for example this one https://launchpad.net/gcc-arm-embedded
+ Run msys shell and set the path without standard Windows paths, so Windows programs such as 'find' won't interfere:
+ export PATH="/c//Python27:/c/ARMToolchain/bin:/usr/local/bin:/usr/bin:/bin"
+ After that you can navigate to the folder where you've extracted libopencm3 and build it.
+
+Toolchain
+---------
+
+The most heavily tested toolchain is gcc-arm-embedded
+https://launchpad.net/gcc-arm-embedded
+
+Other toolchains _should_ work, but have not been nearly as well tested.
+Toolchains targetting linux, such as "gcc-arm-linux-gnu" or the like are
+_not_ appropriate.
+
+Building
+--------
+
+ $ make
+
+If your have an arm-elf toolchain (uncommon) you may want to override the
+toolchain prefix (arm-none-eabi is the default)
+
+ $ PREFIX=arm-elf make
+
+For a more verbose build you can use
+
+ $ make V=1
+
+Fine-tuning the build
+---------------------
+
+The build may be fine-tuned with a limited number of parameters, by specifying
+them as environment variables, for example:
+
+ $ VARIABLE=value make
+
+* FP_FLAGS - Control the floating-point ABI
+ If the Cortex-M core supports a hard float ABI, it will be compiled with
+ floating-point support by default. In cases where this is not desired, the
+ behavior can be specified by setting FP_FLAGS. Currently, M4F cores default
+ to "-mfloat-abi=hard -mfpu=fpv4-sp-d16" and others to no FP flags
+ Examples:
+ $ FP_FLAGS="-mfloat-abi=soft" make # No hardfloat
+ $ FP_FLAGS="-mfloat-abi=hard -mfpu=magic" make # New FPU we don't know of
+
+Example projects
+----------------
+
+The libopencm3 community has written and is maintaining a huge collection of
+examples, displaying the capabilities and uses of the library. You can find all
+of them in the libopencm3-examples repository:
+
+https://github.com/libopencm3/libopencm3-examples
+
+Installation
+------------
+
+ $ make install
+
+This will install the library into /usr/local. (permissions permitting)
+
+If you want to install it elsewhere, use the following syntax:
+
+ $ make DESTDIR=/opt/libopencm3 install
+
+It is strongly advised that you do not attempt to install this library to any
+path inside your toolchain itself. While this means you don't have to include
+any -I or -L flags in your projects, it is _very_ easy to confuse a multilib
+linker from picking the right versions of libraries. Common symptoms are
+hardfaults caused by branches into arm code. You can use arm-none-eabi-objdump
+to check for this in your final elf. You have been warned.
+
+
+Coding style and development guidelines
+---------------------------------------
+
+See HACKING.
+
+
+License
+-------
+
+The libopencm3 code is released under the terms of the GNU Lesser General
+Public License (LGPL), version 3 or later.
+
+See COPYING.GPL3 and COPYING.LGPL3 for details.
+
+IRC
+---
+
+ * You can reach us in #libopencm3 on the freenode IRC network.
+
+Mailing lists
+-------------
+
+ * Developer mailing list (for patches and discussions):
+ https://lists.sourceforge.net/lists/listinfo/libopencm3-devel
+
+ * Commits mailing list (receives one mail per 'git push'):
+ https://lists.sourceforge.net/lists/listinfo/libopencm3-commits
+
+
+Website
+-------
+
+ http://libopencm3.org
+ http://sourceforge.net/projects/libopencm3/
+
diff --git a/libopencm3/doc/Doxyfile b/libopencm3/doc/Doxyfile
new file mode 100644
index 0000000..f9c0a5a
--- /dev/null
+++ b/libopencm3/doc/Doxyfile
@@ -0,0 +1,21 @@
+# Doxygen include file to generate top level entry document
+
+# 14 September 2012
+# (C) Ken Sarkies
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ./Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+INPUT = ../include/libopencm3/docmain.dox
+
+LAYOUT_FILE = DoxygenLayout.xml
+
+GENERATE_LATEX = NO
+
diff --git a/libopencm3/doc/Doxyfile_common b/libopencm3/doc/Doxyfile_common
new file mode 100644
index 0000000..a36a2c1
--- /dev/null
+++ b/libopencm3/doc/Doxyfile_common
@@ -0,0 +1,1809 @@
+# Doxyfile 1.8.2
+
+# This file describes the settings to be used by the documentation system
+# doxygen (www.doxygen.org) for a project.
+#
+# All text after a hash (#) is considered a comment and will be ignored.
+# The format is:
+# TAG = value [value, ...]
+# For lists items can also be appended using:
+# TAG += value [value, ...]
+# Values that contain spaces should be placed between quotes (" ").
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+
+# This tag specifies the encoding used for all characters in the config file
+# that follow. The default is UTF-8 which is also the encoding used for all
+# text before the first occurrence of this tag. Doxygen uses libiconv (or the
+# iconv built into libc) for the transcoding. See
+# http://www.gnu.org/software/libiconv for the list of possible encodings.
+
+DOXYFILE_ENCODING = UTF-8
+
+# The PROJECT_NAME tag is a single word (or sequence of words) that should
+# identify the project. Note that if you do not use Doxywizard you need
+# to put quotes around the project name if it contains spaces.
+
+PROJECT_NAME = libopencm3
+
+# The PROJECT_NUMBER tag can be used to enter a project or revision number.
+# This could be handy for archiving the generated documentation or
+# if some version control system is used.
+
+PROJECT_NUMBER =
+
+# Using the PROJECT_BRIEF tag one can provide an optional one line description
+# for a project that appears at the top of each page and should give viewer
+# a quick idea about the purpose of the project. Keep the description short.
+
+PROJECT_BRIEF = "A free/libre/open-source firmware library for various ARM Cortex-M3 microcontrollers."
+
+# With the PROJECT_LOGO tag one can specify an logo or icon that is
+# included in the documentation. The maximum height of the logo should not
+# exceed 55 pixels and the maximum width should not exceed 200 pixels.
+# Doxygen will copy the logo to the output directory.
+
+PROJECT_LOGO =
+
+# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute)
+# base path where the generated documentation will be put.
+# If a relative path is entered, it will be relative to the location
+# where doxygen was started. If left blank the current directory will be used.
+
+OUTPUT_DIRECTORY =
+
+# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create
+# 4096 sub-directories (in 2 levels) under the output directory of each output
+# format and will distribute the generated files over these directories.
+# Enabling this option can be useful when feeding doxygen a huge amount of
+# source files, where putting all generated files in the same directory would
+# otherwise cause performance problems for the file system.
+
+CREATE_SUBDIRS = NO
+
+# The OUTPUT_LANGUAGE tag is used to specify the language in which all
+# documentation generated by doxygen is written. Doxygen will use this
+# information to generate all constant output in the proper language.
+# The default language is English, other supported languages are:
+# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional,
+# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German,
+# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English
+# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian,
+# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrillic, Slovak,
+# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese.
+
+OUTPUT_LANGUAGE = English
+
+# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will
+# include brief member descriptions after the members that are listed in
+# the file and class documentation (similar to JavaDoc).
+# Set to NO to disable this.
+
+BRIEF_MEMBER_DESC = YES
+
+# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend
+# the brief description of a member or function before the detailed description.
+# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the
+# brief descriptions will be completely suppressed.
+
+REPEAT_BRIEF = YES
+
+# This tag implements a quasi-intelligent brief description abbreviator
+# that is used to form the text in various listings. Each string
+# in this list, if found as the leading text of the brief description, will be
+# stripped from the text and the result after processing the whole list, is
+# used as the annotated text. Otherwise, the brief description is used as-is.
+# If left blank, the following values are used ("$name" is automatically
+# replaced with the name of the entity): "The $name class" "The $name widget"
+# "The $name file" "is" "provides" "specifies" "contains"
+# "represents" "a" "an" "the"
+
+ABBREVIATE_BRIEF =
+
+# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then
+# Doxygen will generate a detailed section even if there is only a brief
+# description.
+
+ALWAYS_DETAILED_SEC = NO
+
+# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all
+# inherited members of a class in the documentation of that class as if those
+# members were ordinary class members. Constructors, destructors and assignment
+# operators of the base classes will not be shown.
+
+INLINE_INHERITED_MEMB = NO
+
+# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full
+# path before files name in the file list and in the header files. If set
+# to NO the shortest path that makes the file name unique will be used.
+
+FULL_PATH_NAMES = NO
+
+# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag
+# can be used to strip a user-defined part of the path. Stripping is
+# only done if one of the specified strings matches the left-hand part of
+# the path. The tag can be used to show relative paths in the file list.
+# If left blank the directory from which doxygen is run is used as the
+# path to strip. Note that you specify absolute paths here, but also
+# relative paths, which will be relative from the directory where doxygen is
+# started.
+
+STRIP_FROM_PATH =
+
+# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of
+# the path mentioned in the documentation of a class, which tells
+# the reader which header file to include in order to use a class.
+# If left blank only the name of the header file containing the class
+# definition is used. Otherwise one should specify the include paths that
+# are normally passed to the compiler using the -I flag.
+
+STRIP_FROM_INC_PATH =
+
+# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter
+# (but less readable) file names. This can be useful if your file system
+# doesn't support long names like on DOS, Mac, or CD-ROM.
+
+SHORT_NAMES = NO
+
+# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen
+# will interpret the first line (until the first dot) of a JavaDoc-style
+# comment as the brief description. If set to NO, the JavaDoc
+# comments will behave just like regular Qt-style comments
+# (thus requiring an explicit @brief command for a brief description.)
+
+JAVADOC_AUTOBRIEF = YES
+
+# If the QT_AUTOBRIEF tag is set to YES then Doxygen will
+# interpret the first line (until the first dot) of a Qt-style
+# comment as the brief description. If set to NO, the comments
+# will behave just like regular Qt-style comments (thus requiring
+# an explicit \brief command for a brief description.)
+
+QT_AUTOBRIEF = NO
+
+# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen
+# treat a multi-line C++ special comment block (i.e. a block of //! or ///
+# comments) as a brief description. This used to be the default behaviour.
+# The new default is to treat a multi-line C++ comment block as a detailed
+# description. Set this tag to YES if you prefer the old behaviour instead.
+
+MULTILINE_CPP_IS_BRIEF = NO
+
+# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented
+# member inherits the documentation from any documented member that it
+# re-implements.
+
+INHERIT_DOCS = YES
+
+# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce
+# a new page for each member. If set to NO, the documentation of a member will
+# be part of the file/class/namespace that contains it.
+
+SEPARATE_MEMBER_PAGES = NO
+
+# The TAB_SIZE tag can be used to set the number of spaces in a tab.
+# Doxygen uses this value to replace tabs by spaces in code fragments.
+
+TAB_SIZE = 8
+
+# This tag can be used to specify a number of aliases that acts
+# as commands in the documentation. An alias has the form "name=value".
+# For example adding "sideeffect=\par Side Effects:\n" will allow you to
+# put the command \sideeffect (or @sideeffect) in the documentation, which
+# will result in a user-defined paragraph with heading "Side Effects:".
+# You can put \n's in the value part of an alias to insert newlines.
+
+ALIASES =
+
+# This tag can be used to specify a number of word-keyword mappings (TCL only).
+# A mapping has the form "name=value". For example adding
+# "class=itcl::class" will allow you to use the command class in the
+# itcl::class meaning.
+
+TCL_SUBST =
+
+# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C
+# sources only. Doxygen will then generate output that is more tailored for C.
+# For instance, some of the names that are used will be different. The list
+# of all members will be omitted, etc.
+
+OPTIMIZE_OUTPUT_FOR_C = YES
+
+# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java
+# sources only. Doxygen will then generate output that is more tailored for
+# Java. For instance, namespaces will be presented as packages, qualified
+# scopes will look different, etc.
+
+OPTIMIZE_OUTPUT_JAVA = NO
+
+# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran
+# sources only. Doxygen will then generate output that is more tailored for
+# Fortran.
+
+OPTIMIZE_FOR_FORTRAN = NO
+
+# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL
+# sources. Doxygen will then generate output that is tailored for
+# VHDL.
+
+OPTIMIZE_OUTPUT_VHDL = NO
+
+# Doxygen selects the parser to use depending on the extension of the files it
+# parses. With this tag you can assign which parser to use for a given
+# extension. Doxygen has a built-in mapping, but you can override or extend it
+# using this tag. The format is ext=language, where ext is a file extension,
+# and language is one of the parsers supported by doxygen: IDL, Java,
+# Javascript, CSharp, C, C++, D, PHP, Objective-C, Python, Fortran, VHDL, C,
+# C++. For instance to make doxygen treat .inc files as Fortran files (default
+# is PHP), and .f files as C (default is Fortran), use: inc=Fortran f=C. Note
+# that for custom extensions you also need to set FILE_PATTERNS otherwise the
+# files are not read by doxygen.
+
+EXTENSION_MAPPING =
+
+# If MARKDOWN_SUPPORT is enabled (the default) then doxygen pre-processes all
+# comments according to the Markdown format, which allows for more readable
+# documentation. See http://daringfireball.net/projects/markdown/ for details.
+# The output of markdown processing is further processed by doxygen, so you
+# can mix doxygen, HTML, and XML commands with Markdown formatting.
+# Disable only in case of backward compatibilities issues.
+
+MARKDOWN_SUPPORT = YES
+
+# When enabled doxygen tries to link words that correspond to documented classes,
+# or namespaces to their corresponding documentation. Such a link can be
+# prevented in individual cases by by putting a % sign in front of the word or
+# globally by setting AUTOLINK_SUPPORT to NO.
+
+AUTOLINK_SUPPORT = YES
+
+# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want
+# to include (a tag file for) the STL sources as input, then you should
+# set this tag to YES in order to let doxygen match functions declarations and
+# definitions whose arguments contain STL classes (e.g. func(std::string); v.s.
+# func(std::string) {}). This also makes the inheritance and collaboration
+# diagrams that involve STL classes more complete and accurate.
+
+BUILTIN_STL_SUPPORT = NO
+
+# If you use Microsoft's C++/CLI language, you should set this option to YES to
+# enable parsing support.
+
+CPP_CLI_SUPPORT = NO
+
+# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only.
+# Doxygen will parse them like normal C++ but will assume all classes use public
+# instead of private inheritance when no explicit protection keyword is present.
+
+SIP_SUPPORT = NO
+
+# For Microsoft's IDL there are propget and propput attributes to indicate getter and setter methods for a property. Setting this option to YES (the default) will make doxygen replace the get and set methods by a property in the documentation. This will only work if the methods are indeed getting or setting a simple type. If this is not the case, or you want to show the methods anyway, you should set this option to NO.
+
+IDL_PROPERTY_SUPPORT = YES
+
+# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC
+# tag is set to YES, then doxygen will reuse the documentation of the first
+# member in the group (if any) for the other members of the group. By default
+# all members of a group must be documented explicitly.
+
+DISTRIBUTE_GROUP_DOC = NO
+
+# Set the SUBGROUPING tag to YES (the default) to allow class member groups of
+# the same type (for instance a group of public functions) to be put as a
+# subgroup of that type (e.g. under the Public Functions section). Set it to
+# NO to prevent subgrouping. Alternatively, this can be done per class using
+# the \nosubgrouping command.
+
+SUBGROUPING = YES
+
+# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and
+# unions are shown inside the group in which they are included (e.g. using
+# @ingroup) instead of on a separate page (for HTML and Man pages) or
+# section (for LaTeX and RTF).
+
+INLINE_GROUPED_CLASSES = NO
+
+# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and
+# unions with only public data fields will be shown inline in the documentation
+# of the scope in which they are defined (i.e. file, namespace, or group
+# documentation), provided this scope is documented. If set to NO (the default),
+# structs, classes, and unions are shown on a separate page (for HTML and Man
+# pages) or section (for LaTeX and RTF).
+
+INLINE_SIMPLE_STRUCTS = NO
+
+# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum
+# is documented as struct, union, or enum with the name of the typedef. So
+# typedef struct TypeS {} TypeT, will appear in the documentation as a struct
+# with name TypeT. When disabled the typedef will appear as a member of a file,
+# namespace, or class. And the struct will be named TypeS. This can typically
+# be useful for C code in case the coding convention dictates that all compound
+# types are typedef'ed and only the typedef is referenced, never the tag name.
+
+TYPEDEF_HIDES_STRUCT = NO
+
+# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to
+# determine which symbols to keep in memory and which to flush to disk.
+# When the cache is full, less often used symbols will be written to disk.
+# For small to medium size projects (<1000 input files) the default value is
+# probably good enough. For larger projects a too small cache size can cause
+# doxygen to be busy swapping symbols to and from disk most of the time
+# causing a significant performance penalty.
+# If the system has enough physical memory increasing the cache will improve the
+# performance by keeping more symbols in memory. Note that the value works on
+# a logarithmic scale so increasing the size by one will roughly double the
+# memory usage. The cache size is given by this formula:
+# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0,
+# corresponding to a cache size of 2^16 = 65536 symbols.
+
+SYMBOL_CACHE_SIZE = 0
+
+# Similar to the SYMBOL_CACHE_SIZE the size of the symbol lookup cache can be
+# set using LOOKUP_CACHE_SIZE. This cache is used to resolve symbols given
+# their name and scope. Since this can be an expensive process and often the
+# same symbol appear multiple times in the code, doxygen keeps a cache of
+# pre-resolved symbols. If the cache is too small doxygen will become slower.
+# If the cache is too large, memory is wasted. The cache size is given by this
+# formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range is 0..9, the default is 0,
+# corresponding to a cache size of 2^16 = 65536 symbols.
+
+LOOKUP_CACHE_SIZE = 0
+
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+
+# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in
+# documentation are documented, even if no documentation was available.
+# Private class members and static file members will be hidden unless
+# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES
+
+EXTRACT_ALL = YES
+
+# If the EXTRACT_PRIVATE tag is set to YES all private members of a class
+# will be included in the documentation.
+
+EXTRACT_PRIVATE = YES
+
+# If the EXTRACT_PACKAGE tag is set to YES all members with package or internal
+# scope will be included in the documentation.
+
+EXTRACT_PACKAGE = NO
+
+# If the EXTRACT_STATIC tag is set to YES all static members of a file
+# will be included in the documentation.
+
+EXTRACT_STATIC = YES
+
+# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs)
+# defined locally in source files will be included in the documentation.
+# If set to NO only classes defined in header files are included.
+
+EXTRACT_LOCAL_CLASSES = YES
+
+# This flag is only useful for Objective-C code. When set to YES local
+# methods, which are defined in the implementation section but not in
+# the interface are included in the documentation.
+# If set to NO (the default) only methods in the interface are included.
+
+EXTRACT_LOCAL_METHODS = NO
+
+# If this flag is set to YES, the members of anonymous namespaces will be
+# extracted and appear in the documentation as a namespace called
+# 'anonymous_namespace{file}', where file will be replaced with the base
+# name of the file that contains the anonymous namespace. By default
+# anonymous namespaces are hidden.
+
+EXTRACT_ANON_NSPACES = NO
+
+# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all
+# undocumented members of documented classes, files or namespaces.
+# If set to NO (the default) these members will be included in the
+# various overviews, but no documentation section is generated.
+# This option has no effect if EXTRACT_ALL is enabled.
+
+HIDE_UNDOC_MEMBERS = NO
+
+# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all
+# undocumented classes that are normally visible in the class hierarchy.
+# If set to NO (the default) these classes will be included in the various
+# overviews. This option has no effect if EXTRACT_ALL is enabled.
+
+HIDE_UNDOC_CLASSES = NO
+
+# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all
+# friend (class|struct|union) declarations.
+# If set to NO (the default) these declarations will be included in the
+# documentation.
+
+HIDE_FRIEND_COMPOUNDS = NO
+
+# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any
+# documentation blocks found inside the body of a function.
+# If set to NO (the default) these blocks will be appended to the
+# function's detailed documentation block.
+
+HIDE_IN_BODY_DOCS = NO
+
+# The INTERNAL_DOCS tag determines if documentation
+# that is typed after a \internal command is included. If the tag is set
+# to NO (the default) then the documentation will be excluded.
+# Set it to YES to include the internal documentation.
+
+INTERNAL_DOCS = NO
+
+# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate
+# file names in lower-case letters. If set to YES upper-case letters are also
+# allowed. This is useful if you have classes or files whose names only differ
+# in case and if your file system supports case sensitive file names. Windows
+# and Mac users are advised to set this option to NO.
+
+CASE_SENSE_NAMES = YES
+
+# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen
+# will show members with their full class and namespace scopes in the
+# documentation. If set to YES the scope will be hidden.
+
+HIDE_SCOPE_NAMES = NO
+
+# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen
+# will put a list of the files that are included by a file in the documentation
+# of that file.
+
+SHOW_INCLUDE_FILES = YES
+
+# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen
+# will list include files with double quotes in the documentation
+# rather than with sharp brackets.
+
+FORCE_LOCAL_INCLUDES = NO
+
+# If the INLINE_INFO tag is set to YES (the default) then a tag [inline]
+# is inserted in the documentation for inline members.
+
+INLINE_INFO = YES
+
+# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen
+# will sort the (detailed) documentation of file and class members
+# alphabetically by member name. If set to NO the members will appear in
+# declaration order.
+
+SORT_MEMBER_DOCS = YES
+
+# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the
+# brief documentation of file, namespace and class members alphabetically
+# by member name. If set to NO (the default) the members will appear in
+# declaration order.
+
+SORT_BRIEF_DOCS = NO
+
+# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen
+# will sort the (brief and detailed) documentation of class members so that
+# constructors and destructors are listed first. If set to NO (the default)
+# the constructors will appear in the respective orders defined by
+# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS.
+# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO
+# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO.
+
+SORT_MEMBERS_CTORS_1ST = NO
+
+# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the
+# hierarchy of group names into alphabetical order. If set to NO (the default)
+# the group names will appear in their defined order.
+
+SORT_GROUP_NAMES = NO
+
+# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be
+# sorted by fully-qualified names, including namespaces. If set to
+# NO (the default), the class list will be sorted only by class name,
+# not including the namespace part.
+# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.
+# Note: This option applies only to the class list, not to the
+# alphabetical list.
+
+SORT_BY_SCOPE_NAME = NO
+
+# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to
+# do proper type resolution of all parameters of a function it will reject a
+# match between the prototype and the implementation of a member function even
+# if there is only one candidate or it is obvious which candidate to choose
+# by doing a simple string match. By disabling STRICT_PROTO_MATCHING doxygen
+# will still accept a match between prototype and implementation in such cases.
+
+STRICT_PROTO_MATCHING = NO
+
+# The GENERATE_TODOLIST tag can be used to enable (YES) or
+# disable (NO) the todo list. This list is created by putting \todo
+# commands in the documentation.
+
+GENERATE_TODOLIST = NO
+
+# The GENERATE_TESTLIST tag can be used to enable (YES) or
+# disable (NO) the test list. This list is created by putting \test
+# commands in the documentation.
+
+GENERATE_TESTLIST = YES
+
+# The GENERATE_BUGLIST tag can be used to enable (YES) or
+# disable (NO) the bug list. This list is created by putting \bug
+# commands in the documentation.
+
+GENERATE_BUGLIST = YES
+
+# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or
+# disable (NO) the deprecated list. This list is created by putting
+# \deprecated commands in the documentation.
+
+GENERATE_DEPRECATEDLIST= NO
+
+# The ENABLED_SECTIONS tag can be used to enable conditional
+# documentation sections, marked by \if sectionname ... \endif.
+
+ENABLED_SECTIONS =
+
+# The MAX_INITIALIZER_LINES tag determines the maximum number of lines
+# the initial value of a variable or macro consists of for it to appear in
+# the documentation. If the initializer consists of more lines than specified
+# here it will be hidden. Use a value of 0 to hide initializers completely.
+# The appearance of the initializer of individual variables and macros in the
+# documentation can be controlled using \showinitializer or \hideinitializer
+# command in the documentation regardless of this setting.
+
+MAX_INITIALIZER_LINES = 30
+
+# Set the SHOW_USED_FILES tag to NO to disable the list of files generated
+# at the bottom of the documentation of classes and structs. If set to YES the
+# list will mention the files that were used to generate the documentation.
+
+SHOW_USED_FILES = YES
+
+# Set the SHOW_FILES tag to NO to disable the generation of the Files page.
+# This will remove the Files entry from the Quick Index and from the
+# Folder Tree View (if specified). The default is YES.
+
+SHOW_FILES = YES
+
+# Set the SHOW_NAMESPACES tag to NO to disable the generation of the
+# Namespaces page.
+# This will remove the Namespaces entry from the Quick Index
+# and from the Folder Tree View (if specified). The default is YES.
+
+SHOW_NAMESPACES = YES
+
+# The FILE_VERSION_FILTER tag can be used to specify a program or script that
+# doxygen should invoke to get the current version for each file (typically from
+# the version control system). Doxygen will invoke the program by executing (via
+# popen()) the command , where is the value of
+# the FILE_VERSION_FILTER tag, and is the name of an input file
+# provided by doxygen. Whatever the program writes to standard output
+# is used as the file version. See the manual for examples.
+
+FILE_VERSION_FILTER =
+
+# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed
+# by doxygen. The layout file controls the global structure of the generated
+# output files in an output format independent way. To create the layout file
+# that represents doxygen's defaults, run doxygen with the -l option.
+# You can optionally specify a file name after the option, if omitted
+# DoxygenLayout.xml will be used as the name of the layout file.
+
+LAYOUT_FILE = DoxygenLayout.xml
+
+# The CITE_BIB_FILES tag can be used to specify one or more bib files
+# containing the references data. This must be a list of .bib files. The
+# .bib extension is automatically appended if omitted. Using this command
+# requires the bibtex tool to be installed. See also
+# http://en.wikipedia.org/wiki/BibTeX for more info. For LaTeX the style
+# of the bibliography can be controlled using LATEX_BIB_STYLE. To use this
+# feature you need bibtex and perl available in the search path.
+
+CITE_BIB_FILES =
+
+#---------------------------------------------------------------------------
+# configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+
+# The QUIET tag can be used to turn on/off the messages that are generated
+# by doxygen. Possible values are YES and NO. If left blank NO is used.
+
+QUIET = NO
+
+# The WARNINGS tag can be used to turn on/off the warning messages that are
+# generated by doxygen. Possible values are YES and NO. If left blank
+# NO is used.
+
+WARNINGS = YES
+
+# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings
+# for undocumented members. If EXTRACT_ALL is set to YES then this flag will
+# automatically be disabled.
+
+WARN_IF_UNDOCUMENTED = YES
+
+# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for
+# potential errors in the documentation, such as not documenting some
+# parameters in a documented function, or documenting parameters that
+# don't exist or using markup commands wrongly.
+
+WARN_IF_DOC_ERROR = YES
+
+# The WARN_NO_PARAMDOC option can be enabled to get warnings for
+# functions that are documented, but have no documentation for their parameters
+# or return value. If set to NO (the default) doxygen will only warn about
+# wrong or incomplete parameter documentation, but not about the absence of
+# documentation.
+
+WARN_NO_PARAMDOC = NO
+
+# The WARN_FORMAT tag determines the format of the warning messages that
+# doxygen can produce. The string should contain the $file, $line, and $text
+# tags, which will be replaced by the file and line number from which the
+# warning originated and the warning text. Optionally the format may contain
+# $version, which will be replaced by the version of the file (if it could
+# be obtained via FILE_VERSION_FILTER)
+
+WARN_FORMAT = "$file:$line: $text"
+
+# The WARN_LOGFILE tag can be used to specify a file to which warning
+# and error messages should be written. If left blank the output is written
+# to stderr.
+
+WARN_LOGFILE = doxygen.log
+
+#---------------------------------------------------------------------------
+# configuration options related to the input files
+#---------------------------------------------------------------------------
+
+# The INPUT tag can be used to specify the files and/or directories that contain
+# documented source files. You may enter file names like "myfile.cpp" or
+# directories like "/usr/src/myproject". Separate the files or directories
+# with spaces.
+
+INPUT =
+
+# This tag can be used to specify the character encoding of the source files
+# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is
+# also the default input encoding. Doxygen uses libiconv (or the iconv built
+# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for
+# the list of possible encodings.
+
+INPUT_ENCODING = UTF-8
+
+# If the value of the INPUT tag contains directories, you can use the
+# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp
+# and *.h) to filter out the source-files in the directories. If left
+# blank the following patterns are tested:
+# *.c *.cc *.cxx *.cpp *.c++ *.d *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh
+# *.hxx *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.dox *.py
+# *.f90 *.f *.for *.vhd *.vhdl
+
+FILE_PATTERNS =
+
+# The RECURSIVE tag can be used to turn specify whether or not subdirectories
+# should be searched for input files as well. Possible values are YES and NO.
+# If left blank NO is used.
+
+RECURSIVE = NO
+
+# The EXCLUDE tag can be used to specify files and/or directories that should be
+# excluded from the INPUT source files. This way you can easily exclude a
+# subdirectory from a directory tree whose root is specified with the INPUT tag.
+# Note that relative paths are relative to the directory from which doxygen is
+# run.
+
+EXCLUDE =
+
+# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or
+# directories that are symbolic links (a Unix file system feature) are excluded
+# from the input.
+
+EXCLUDE_SYMLINKS = NO
+
+# If the value of the INPUT tag contains directories, you can use the
+# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude
+# certain files from those directories. Note that the wildcards are matched
+# against the file with absolute path, so to exclude all test directories
+# for example use the pattern */test/*
+
+EXCLUDE_PATTERNS = */*.d
+
+# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names
+# (namespaces, classes, functions, etc.) that should be excluded from the
+# output. The symbol name can be a fully qualified name, a word, or if the
+# wildcard * is used, a substring. Examples: ANamespace, AClass,
+# AClass::ANamespace, ANamespace::*Test
+
+EXCLUDE_SYMBOLS =
+
+# The EXAMPLE_PATH tag can be used to specify one or more files or
+# directories that contain example code fragments that are included (see
+# the \include command).
+
+EXAMPLE_PATH =
+
+# If the value of the EXAMPLE_PATH tag contains directories, you can use the
+# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp
+# and *.h) to filter out the source-files in the directories. If left
+# blank all files are included.
+
+EXAMPLE_PATTERNS =
+
+# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be
+# searched for input files to be used with the \include or \dontinclude
+# commands irrespective of the value of the RECURSIVE tag.
+# Possible values are YES and NO. If left blank NO is used.
+
+EXAMPLE_RECURSIVE = NO
+
+# The IMAGE_PATH tag can be used to specify one or more files or
+# directories that contain image that are included in the documentation (see
+# the \image command).
+
+IMAGE_PATH =
+
+# The INPUT_FILTER tag can be used to specify a program that doxygen should
+# invoke to filter for each input file. Doxygen will invoke the filter program
+# by executing (via popen()) the command , where
+# is the value of the INPUT_FILTER tag, and is the name of an
+# input file. Doxygen will then use the output that the filter program writes
+# to standard output.
+# If FILTER_PATTERNS is specified, this tag will be
+# ignored.
+
+INPUT_FILTER =
+
+# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern
+# basis.
+# Doxygen will compare the file name with each pattern and apply the
+# filter if there is a match.
+# The filters are a list of the form:
+# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further
+# info on how filters are used. If FILTER_PATTERNS is empty or if
+# non of the patterns match the file name, INPUT_FILTER is applied.
+
+FILTER_PATTERNS =
+
+# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using
+# INPUT_FILTER) will be used to filter the input files when producing source
+# files to browse (i.e. when SOURCE_BROWSER is set to YES).
+
+FILTER_SOURCE_FILES = NO
+
+# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file
+# pattern. A pattern will override the setting for FILTER_PATTERN (if any)
+# and it is also possible to disable source filtering for a specific pattern
+# using *.ext= (so without naming a filter). This option only has effect when
+# FILTER_SOURCE_FILES is enabled.
+
+FILTER_SOURCE_PATTERNS =
+
+#---------------------------------------------------------------------------
+# configuration options related to source browsing
+#---------------------------------------------------------------------------
+
+# If the SOURCE_BROWSER tag is set to YES then a list of source files will
+# be generated. Documented entities will be cross-referenced with these sources.
+# Note: To get rid of all source code in the generated output, make sure also
+# VERBATIM_HEADERS is set to NO.
+
+SOURCE_BROWSER = YES
+
+# Setting the INLINE_SOURCES tag to YES will include the body
+# of functions and classes directly in the documentation.
+
+INLINE_SOURCES = NO
+
+# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct
+# doxygen to hide any special comment blocks from generated source code
+# fragments. Normal C, C++ and Fortran comments will always remain visible.
+
+STRIP_CODE_COMMENTS = NO
+
+# If the REFERENCED_BY_RELATION tag is set to YES
+# then for each documented function all documented
+# functions referencing it will be listed.
+
+REFERENCED_BY_RELATION = YES
+
+# If the REFERENCES_RELATION tag is set to YES
+# then for each documented function all documented entities
+# called/used by that function will be listed.
+
+REFERENCES_RELATION = YES
+
+# If the REFERENCES_LINK_SOURCE tag is set to YES (the default)
+# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from
+# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will
+# link to the source code.
+# Otherwise they will link to the documentation.
+
+REFERENCES_LINK_SOURCE = YES
+
+# If the USE_HTAGS tag is set to YES then the references to source code
+# will point to the HTML generated by the htags(1) tool instead of doxygen
+# built-in source browser. The htags tool is part of GNU's global source
+# tagging system (see http://www.gnu.org/software/global/global.html). You
+# will need version 4.8.6 or higher.
+
+USE_HTAGS = NO
+
+# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen
+# will generate a verbatim copy of the header file for each class for
+# which an include is specified. Set to NO to disable this.
+
+VERBATIM_HEADERS = YES
+
+#---------------------------------------------------------------------------
+# configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+
+# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index
+# of all compounds will be generated. Enable this if the project
+# contains a lot of classes, structs, unions or interfaces.
+
+ALPHABETICAL_INDEX = YES
+
+# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then
+# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns
+# in which this list will be split (can be a number in the range [1..20])
+
+COLS_IN_ALPHA_INDEX = 5
+
+# In case all classes in a project start with a common prefix, all
+# classes will be put under the same header in the alphabetical index.
+# The IGNORE_PREFIX tag can be used to specify one or more prefixes that
+# should be ignored while generating the index headers.
+
+IGNORE_PREFIX =
+
+#---------------------------------------------------------------------------
+# configuration options related to the HTML output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_HTML tag is set to YES (the default) Doxygen will
+# generate HTML output.
+
+GENERATE_HTML = YES
+
+# The HTML_OUTPUT tag is used to specify where the HTML docs will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `html' will be used as the default path.
+
+HTML_OUTPUT = html
+
+# The HTML_FILE_EXTENSION tag can be used to specify the file extension for
+# each generated HTML page (for example: .htm,.php,.asp). If it is left blank
+# doxygen will generate files with .html extension.
+
+HTML_FILE_EXTENSION = .html
+
+# The HTML_HEADER tag can be used to specify a personal HTML header for
+# each generated HTML page. If it is left blank doxygen will generate a
+# standard header. Note that when using a custom header you are responsible
+# for the proper inclusion of any scripts and style sheets that doxygen
+# needs, which is dependent on the configuration options used.
+# It is advised to generate a default header using "doxygen -w html
+# header.html footer.html stylesheet.css YourConfigFile" and then modify
+# that header. Note that the header is subject to change so you typically
+# have to redo this when upgrading to a newer version of doxygen or when
+# changing the value of configuration settings such as GENERATE_TREEVIEW!
+
+HTML_HEADER =
+
+# The HTML_FOOTER tag can be used to specify a personal HTML footer for
+# each generated HTML page. If it is left blank doxygen will generate a
+# standard footer.
+
+HTML_FOOTER =
+
+# The HTML_STYLESHEET tag can be used to specify a user-defined cascading
+# style sheet that is used by each HTML page. It can be used to
+# fine-tune the look of the HTML output. If left blank doxygen will
+# generate a default style sheet. Note that it is recommended to use
+# HTML_EXTRA_STYLESHEET instead of this one, as it is more robust and this
+# tag will in the future become obsolete.
+
+HTML_STYLESHEET =
+
+# The HTML_EXTRA_STYLESHEET tag can be used to specify an additional
+# user-defined cascading style sheet that is included after the standard
+# style sheets created by doxygen. Using this option one can overrule
+# certain style aspects. This is preferred over using HTML_STYLESHEET
+# since it does not replace the standard style sheet and is therefor more
+# robust against future updates. Doxygen will copy the style sheet file to
+# the output directory.
+
+HTML_EXTRA_STYLESHEET =
+
+# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or
+# other source files which should be copied to the HTML output directory. Note
+# that these files will be copied to the base HTML output directory. Use the
+# $relpath$ marker in the HTML_HEADER and/or HTML_FOOTER files to load these
+# files. In the HTML_STYLESHEET file, use the file name only. Also note that
+# the files will be copied as-is; there are no commands or markers available.
+
+HTML_EXTRA_FILES =
+
+# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output.
+# Doxygen will adjust the colors in the style sheet and background images
+# according to this color. Hue is specified as an angle on a colorwheel,
+# see http://en.wikipedia.org/wiki/Hue for more information.
+# For instance the value 0 represents red, 60 is yellow, 120 is green,
+# 180 is cyan, 240 is blue, 300 purple, and 360 is red again.
+# The allowed range is 0 to 359.
+
+HTML_COLORSTYLE_HUE = 220
+
+# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of
+# the colors in the HTML output. For a value of 0 the output will use
+# grayscales only. A value of 255 will produce the most vivid colors.
+
+HTML_COLORSTYLE_SAT = 100
+
+# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to
+# the luminance component of the colors in the HTML output. Values below
+# 100 gradually make the output lighter, whereas values above 100 make
+# the output darker. The value divided by 100 is the actual gamma applied,
+# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2,
+# and 100 does not change the gamma.
+
+HTML_COLORSTYLE_GAMMA = 80
+
+# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML
+# page will contain the date and time when the page was generated. Setting
+# this to NO can help when comparing the output of multiple runs.
+
+HTML_TIMESTAMP = YES
+
+# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML
+# documentation will contain sections that can be hidden and shown after the
+# page has loaded.
+
+HTML_DYNAMIC_SECTIONS = NO
+
+# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of
+# entries shown in the various tree structured indices initially; the user
+# can expand and collapse entries dynamically later on. Doxygen will expand
+# the tree to such a level that at most the specified number of entries are
+# visible (unless a fully collapsed tree already exceeds this amount).
+# So setting the number of entries 1 will produce a full collapsed tree by
+# default. 0 is a special value representing an infinite number of entries
+# and will result in a full expanded tree by default.
+
+HTML_INDEX_NUM_ENTRIES = 100
+
+# If the GENERATE_DOCSET tag is set to YES, additional index files
+# will be generated that can be used as input for Apple's Xcode 3
+# integrated development environment, introduced with OSX 10.5 (Leopard).
+# To create a documentation set, doxygen will generate a Makefile in the
+# HTML output directory. Running make will produce the docset in that
+# directory and running "make install" will install the docset in
+# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find
+# it at startup.
+# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html
+# for more information.
+
+GENERATE_DOCSET = NO
+
+# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the
+# feed. A documentation feed provides an umbrella under which multiple
+# documentation sets from a single provider (such as a company or product suite)
+# can be grouped.
+
+DOCSET_FEEDNAME = "Doxygen generated docs"
+
+# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that
+# should uniquely identify the documentation set bundle. This should be a
+# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen
+# will append .docset to the name.
+
+DOCSET_BUNDLE_ID = org.doxygen.Project
+
+# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely
+# identify the documentation publisher. This should be a reverse domain-name
+# style string, e.g. com.mycompany.MyDocSet.documentation.
+
+DOCSET_PUBLISHER_ID = org.doxygen.Publisher
+
+# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher.
+
+DOCSET_PUBLISHER_NAME = Publisher
+
+# If the GENERATE_HTMLHELP tag is set to YES, additional index files
+# will be generated that can be used as input for tools like the
+# Microsoft HTML help workshop to generate a compiled HTML help file (.chm)
+# of the generated HTML documentation.
+
+GENERATE_HTMLHELP = NO
+
+# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can
+# be used to specify the file name of the resulting .chm file. You
+# can add a path in front of the file if the result should not be
+# written to the html output directory.
+
+CHM_FILE =
+
+# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can
+# be used to specify the location (absolute path including file name) of
+# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run
+# the HTML help compiler on the generated index.hhp.
+
+HHC_LOCATION =
+
+# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag
+# controls if a separate .chi index file is generated (YES) or that
+# it should be included in the master .chm file (NO).
+
+GENERATE_CHI = NO
+
+# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING
+# is used to encode HtmlHelp index (hhk), content (hhc) and project file
+# content.
+
+CHM_INDEX_ENCODING =
+
+# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag
+# controls whether a binary table of contents is generated (YES) or a
+# normal table of contents (NO) in the .chm file.
+
+BINARY_TOC = NO
+
+# The TOC_EXPAND flag can be set to YES to add extra items for group members
+# to the contents of the HTML help documentation and to the tree view.
+
+TOC_EXPAND = NO
+
+# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and
+# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated
+# that can be used as input for Qt's qhelpgenerator to generate a
+# Qt Compressed Help (.qch) of the generated HTML documentation.
+
+GENERATE_QHP = NO
+
+# If the QHG_LOCATION tag is specified, the QCH_FILE tag can
+# be used to specify the file name of the resulting .qch file.
+# The path specified is relative to the HTML output folder.
+
+QCH_FILE =
+
+# The QHP_NAMESPACE tag specifies the namespace to use when generating
+# Qt Help Project output. For more information please see
+# http://doc.trolltech.com/qthelpproject.html#namespace
+
+QHP_NAMESPACE = org.doxygen.Project
+
+# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating
+# Qt Help Project output. For more information please see
+# http://doc.trolltech.com/qthelpproject.html#virtual-folders
+
+QHP_VIRTUAL_FOLDER = doc
+
+# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to
+# add. For more information please see
+# http://doc.trolltech.com/qthelpproject.html#custom-filters
+
+QHP_CUST_FILTER_NAME =
+
+# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the
+# custom filter to add. For more information please see
+#
+# Qt Help Project / Custom Filters.
+
+QHP_CUST_FILTER_ATTRS =
+
+# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this
+# project's
+# filter section matches.
+#
+# Qt Help Project / Filter Attributes.
+
+QHP_SECT_FILTER_ATTRS =
+
+# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can
+# be used to specify the location of Qt's qhelpgenerator.
+# If non-empty doxygen will try to run qhelpgenerator on the generated
+# .qhp file.
+
+QHG_LOCATION =
+
+# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files
+# will be generated, which together with the HTML files, form an Eclipse help
+# plugin. To install this plugin and make it available under the help contents
+# menu in Eclipse, the contents of the directory containing the HTML and XML
+# files needs to be copied into the plugins directory of eclipse. The name of
+# the directory within the plugins directory should be the same as
+# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before
+# the help appears.
+
+GENERATE_ECLIPSEHELP = NO
+
+# A unique identifier for the eclipse help plugin. When installing the plugin
+# the directory name containing the HTML and XML files should also have
+# this name.
+
+ECLIPSE_DOC_ID = org.doxygen.Project
+
+# The DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs)
+# at top of each HTML page. The value NO (the default) enables the index and
+# the value YES disables it. Since the tabs have the same information as the
+# navigation tree you can set this option to NO if you already set
+# GENERATE_TREEVIEW to YES.
+
+DISABLE_INDEX = NO
+
+# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index
+# structure should be generated to display hierarchical information.
+# If the tag value is set to YES, a side panel will be generated
+# containing a tree-like index structure (just like the one that
+# is generated for HTML Help). For this to work a browser that supports
+# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser).
+# Windows users are probably better off using the HTML help feature.
+# Since the tree basically has the same information as the tab index you
+# could consider to set DISABLE_INDEX to NO when enabling this option.
+
+GENERATE_TREEVIEW = YES
+
+# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values
+# (range [0,1..20]) that doxygen will group on one line in the generated HTML
+# documentation. Note that a value of 0 will completely suppress the enum
+# values from appearing in the overview section.
+
+ENUM_VALUES_PER_LINE = 4
+
+# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be
+# used to set the initial width (in pixels) of the frame in which the tree
+# is shown.
+
+TREEVIEW_WIDTH = 250
+
+# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open
+# links to external symbols imported via tag files in a separate window.
+
+EXT_LINKS_IN_WINDOW = NO
+
+# Use this tag to change the font size of Latex formulas included
+# as images in the HTML documentation. The default is 10. Note that
+# when you change the font size after a successful doxygen run you need
+# to manually remove any form_*.png images from the HTML output directory
+# to force them to be regenerated.
+
+FORMULA_FONTSIZE = 10
+
+# Use the FORMULA_TRANPARENT tag to determine whether or not the images
+# generated for formulas are transparent PNGs. Transparent PNGs are
+# not supported properly for IE 6.0, but are supported on all modern browsers.
+# Note that when changing this option you need to delete any form_*.png files
+# in the HTML output before the changes have effect.
+
+FORMULA_TRANSPARENT = YES
+
+# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax
+# (see http://www.mathjax.org) which uses client side Javascript for the
+# rendering instead of using prerendered bitmaps. Use this if you do not
+# have LaTeX installed or if you want to formulas look prettier in the HTML
+# output. When enabled you may also need to install MathJax separately and
+# configure the path to it using the MATHJAX_RELPATH option.
+
+USE_MATHJAX = NO
+
+# When MathJax is enabled you need to specify the location relative to the
+# HTML output directory using the MATHJAX_RELPATH option. The destination
+# directory should contain the MathJax.js script. For instance, if the mathjax
+# directory is located at the same level as the HTML output directory, then
+# MATHJAX_RELPATH should be ../mathjax. The default value points to
+# the MathJax Content Delivery Network so you can quickly see the result without
+# installing MathJax.
+# However, it is strongly recommended to install a local
+# copy of MathJax from http://www.mathjax.org before deployment.
+
+MATHJAX_RELPATH = http://www.mathjax.org/mathjax
+
+# The MATHJAX_EXTENSIONS tag can be used to specify one or MathJax extension
+# names that should be enabled during MathJax rendering.
+
+MATHJAX_EXTENSIONS =
+
+# When the SEARCHENGINE tag is enabled doxygen will generate a search box
+# for the HTML output. The underlying search engine uses javascript
+# and DHTML and should work on any modern browser. Note that when using
+# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets
+# (GENERATE_DOCSET) there is already a search function so this one should
+# typically be disabled. For large projects the javascript based search engine
+# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution.
+
+SEARCHENGINE = YES
+
+# When the SERVER_BASED_SEARCH tag is enabled the search engine will be
+# implemented using a PHP enabled web server instead of at the web client
+# using Javascript. Doxygen will generate the search PHP script and index
+# file to put on the web server. The advantage of the server
+# based approach is that it scales better to large projects and allows
+# full text search. The disadvantages are that it is more difficult to setup
+# and does not have live searching capabilities.
+
+SERVER_BASED_SEARCH = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the LaTeX output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will
+# generate Latex output.
+
+GENERATE_LATEX = NO
+
+# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `latex' will be used as the default path.
+
+LATEX_OUTPUT = latex
+
+# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be
+# invoked. If left blank `latex' will be used as the default command name.
+# Note that when enabling USE_PDFLATEX this option is only used for
+# generating bitmaps for formulas in the HTML output, but not in the
+# Makefile that is written to the output directory.
+
+LATEX_CMD_NAME = latex
+
+# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to
+# generate index for LaTeX. If left blank `makeindex' will be used as the
+# default command name.
+
+MAKEINDEX_CMD_NAME = makeindex
+
+# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact
+# LaTeX documents. This may be useful for small projects and may help to
+# save some trees in general.
+
+COMPACT_LATEX = NO
+
+# The PAPER_TYPE tag can be used to set the paper type that is used
+# by the printer. Possible values are: a4, letter, legal and
+# executive. If left blank a4wide will be used.
+
+PAPER_TYPE = a4
+
+# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX
+# packages that should be included in the LaTeX output.
+
+EXTRA_PACKAGES =
+
+# The LATEX_HEADER tag can be used to specify a personal LaTeX header for
+# the generated latex document. The header should contain everything until
+# the first chapter. If it is left blank doxygen will generate a
+# standard header. Notice: only use this tag if you know what you are doing!
+
+LATEX_HEADER =
+
+# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for
+# the generated latex document. The footer should contain everything after
+# the last chapter. If it is left blank doxygen will generate a
+# standard footer. Notice: only use this tag if you know what you are doing!
+
+LATEX_FOOTER =
+
+# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated
+# is prepared for conversion to pdf (using ps2pdf). The pdf file will
+# contain links (just like the HTML output) instead of page references
+# This makes the output suitable for online browsing using a pdf viewer.
+
+PDF_HYPERLINKS = YES
+
+# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of
+# plain latex in the generated Makefile. Set this option to YES to get a
+# higher quality PDF documentation.
+
+USE_PDFLATEX = YES
+
+# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode.
+# command to the generated LaTeX files. This will instruct LaTeX to keep
+# running if errors occur, instead of asking the user for help.
+# This option is also used when generating formulas in HTML.
+
+LATEX_BATCHMODE = NO
+
+# If LATEX_HIDE_INDICES is set to YES then doxygen will not
+# include the index chapters (such as File Index, Compound Index, etc.)
+# in the output.
+
+LATEX_HIDE_INDICES = NO
+
+# If LATEX_SOURCE_CODE is set to YES then doxygen will include
+# source code with syntax highlighting in the LaTeX output.
+# Note that which sources are shown also depends on other settings
+# such as SOURCE_BROWSER.
+
+LATEX_SOURCE_CODE = NO
+
+# The LATEX_BIB_STYLE tag can be used to specify the style to use for the
+# bibliography, e.g. plainnat, or ieeetr. The default style is "plain". See
+# http://en.wikipedia.org/wiki/BibTeX for more info.
+
+LATEX_BIB_STYLE = plain
+
+#---------------------------------------------------------------------------
+# configuration options related to the RTF output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output
+# The RTF output is optimized for Word 97 and may not look very pretty with
+# other RTF readers or editors.
+
+GENERATE_RTF = NO
+
+# The RTF_OUTPUT tag is used to specify where the RTF docs will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `rtf' will be used as the default path.
+
+RTF_OUTPUT = rtf
+
+# If the COMPACT_RTF tag is set to YES Doxygen generates more compact
+# RTF documents. This may be useful for small projects and may help to
+# save some trees in general.
+
+COMPACT_RTF = NO
+
+# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated
+# will contain hyperlink fields. The RTF file will
+# contain links (just like the HTML output) instead of page references.
+# This makes the output suitable for online browsing using WORD or other
+# programs which support those fields.
+# Note: wordpad (write) and others do not support links.
+
+RTF_HYPERLINKS = NO
+
+# Load style sheet definitions from file. Syntax is similar to doxygen's
+# config file, i.e. a series of assignments. You only have to provide
+# replacements, missing definitions are set to their default value.
+
+RTF_STYLESHEET_FILE =
+
+# Set optional variables used in the generation of an rtf document.
+# Syntax is similar to doxygen's config file.
+
+RTF_EXTENSIONS_FILE =
+
+#---------------------------------------------------------------------------
+# configuration options related to the man page output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_MAN tag is set to YES (the default) Doxygen will
+# generate man pages
+
+GENERATE_MAN = NO
+
+# The MAN_OUTPUT tag is used to specify where the man pages will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `man' will be used as the default path.
+
+MAN_OUTPUT = man
+
+# The MAN_EXTENSION tag determines the extension that is added to
+# the generated man pages (default is the subroutine's section .3)
+
+MAN_EXTENSION = .3
+
+# If the MAN_LINKS tag is set to YES and Doxygen generates man output,
+# then it will generate one additional man file for each entity
+# documented in the real man page(s). These additional files
+# only source the real man page, but without them the man command
+# would be unable to find the correct page. The default is NO.
+
+MAN_LINKS = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the XML output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_XML tag is set to YES Doxygen will
+# generate an XML file that captures the structure of
+# the code including all documentation.
+
+GENERATE_XML = NO
+
+# The XML_OUTPUT tag is used to specify where the XML pages will be put.
+# If a relative path is entered the value of OUTPUT_DIRECTORY will be
+# put in front of it. If left blank `xml' will be used as the default path.
+
+XML_OUTPUT = xml
+
+# The XML_SCHEMA tag can be used to specify an XML schema,
+# which can be used by a validating XML parser to check the
+# syntax of the XML files.
+
+XML_SCHEMA =
+
+# The XML_DTD tag can be used to specify an XML DTD,
+# which can be used by a validating XML parser to check the
+# syntax of the XML files.
+
+XML_DTD =
+
+# If the XML_PROGRAMLISTING tag is set to YES Doxygen will
+# dump the program listings (including syntax highlighting
+# and cross-referencing information) to the XML output. Note that
+# enabling this will significantly increase the size of the XML output.
+
+XML_PROGRAMLISTING = YES
+
+#---------------------------------------------------------------------------
+# configuration options for the AutoGen Definitions output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will
+# generate an AutoGen Definitions (see autogen.sf.net) file
+# that captures the structure of the code including all
+# documentation. Note that this feature is still experimental
+# and incomplete at the moment.
+
+GENERATE_AUTOGEN_DEF = NO
+
+#---------------------------------------------------------------------------
+# configuration options related to the Perl module output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_PERLMOD tag is set to YES Doxygen will
+# generate a Perl module file that captures the structure of
+# the code including all documentation. Note that this
+# feature is still experimental and incomplete at the
+# moment.
+
+GENERATE_PERLMOD = NO
+
+# If the PERLMOD_LATEX tag is set to YES Doxygen will generate
+# the necessary Makefile rules, Perl scripts and LaTeX code to be able
+# to generate PDF and DVI output from the Perl module output.
+
+PERLMOD_LATEX = NO
+
+# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be
+# nicely formatted so it can be parsed by a human reader.
+# This is useful
+# if you want to understand what is going on.
+# On the other hand, if this
+# tag is set to NO the size of the Perl module output will be much smaller
+# and Perl will parse it just the same.
+
+PERLMOD_PRETTY = YES
+
+# The names of the make variables in the generated doxyrules.make file
+# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX.
+# This is useful so different doxyrules.make files included by the same
+# Makefile don't overwrite each other's variables.
+
+PERLMOD_MAKEVAR_PREFIX =
+
+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor
+#---------------------------------------------------------------------------
+
+# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will
+# evaluate all C-preprocessor directives found in the sources and include
+# files.
+
+ENABLE_PREPROCESSING = YES
+
+# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro
+# names in the source code. If set to NO (the default) only conditional
+# compilation will be performed. Macro expansion can be done in a controlled
+# way by setting EXPAND_ONLY_PREDEF to YES.
+
+MACRO_EXPANSION = YES
+
+# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES
+# then the macro expansion is limited to the macros specified with the
+# PREDEFINED and EXPAND_AS_DEFINED tags.
+
+EXPAND_ONLY_PREDEF = YES
+
+# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files
+# pointed to by INCLUDE_PATH will be searched when a #include is found.
+
+SEARCH_INCLUDES = YES
+
+# The INCLUDE_PATH tag can be used to specify one or more directories that
+# contain include files that are not input files but should be processed by
+# the preprocessor.
+
+INCLUDE_PATH =
+
+# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard
+# patterns (like *.h and *.hpp) to filter out the header-files in the
+# directories. If left blank, the patterns specified with FILE_PATTERNS will
+# be used.
+
+INCLUDE_FILE_PATTERNS =
+
+# The PREDEFINED tag can be used to specify one or more macro names that
+# are defined before the preprocessor is started (similar to the -D option of
+# gcc). The argument of the tag is a list of macros of the form: name
+# or name=definition (no spaces). If the definition and the = are
+# omitted =1 is assumed. To prevent a macro definition from being
+# undefined via #undef or recursively expanded use the := operator
+# instead of the = operator.
+
+PREDEFINED = __attribute__(x)= BEGIN_DECLS END_DECLS
+
+# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then
+# this tag can be used to specify a list of macro names that should be expanded.
+# The macro definition that is found in the sources will be used.
+# Use the PREDEFINED tag if you want to use a different macro definition that
+# overrules the definition found in the source code.
+
+EXPAND_AS_DEFINED =
+
+# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then
+# doxygen's preprocessor will remove all references to function-like macros
+# that are alone on a line, have an all uppercase name, and do not end with a
+# semicolon, because these will confuse the parser if not removed.
+
+SKIP_FUNCTION_MACROS = YES
+
+#---------------------------------------------------------------------------
+# Configuration::additions related to external references
+#---------------------------------------------------------------------------
+
+# The TAGFILES option can be used to specify one or more tagfiles. For each
+# tag file the location of the external documentation should be added. The
+# format of a tag file without this location is as follows:
+#
+# TAGFILES = file1 file2 ...
+# Adding location for the tag files is done as follows:
+#
+# TAGFILES = file1=loc1 "file2 = loc2" ...
+# where "loc1" and "loc2" can be relative or absolute paths
+# or URLs. Note that each tag file must have a unique name (where the name does
+# NOT include the path). If a tag file is not located in the directory in which
+# doxygen is run, you must also specify the path to the tagfile here.
+
+TAGFILES =
+
+# When a file name is specified after GENERATE_TAGFILE, doxygen will create
+# a tag file that is based on the input files it reads.
+
+GENERATE_TAGFILE =
+
+# If the ALLEXTERNALS tag is set to YES all external classes will be listed
+# in the class index. If set to NO only the inherited external classes
+# will be listed.
+
+ALLEXTERNALS = NO
+
+# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed
+# in the modules index. If set to NO, only the current project's groups will
+# be listed.
+
+EXTERNAL_GROUPS = NO
+
+# The PERL_PATH should be the absolute path and name of the perl script
+# interpreter (i.e. the result of `which perl').
+
+PERL_PATH = /usr/bin/perl
+
+#---------------------------------------------------------------------------
+# Configuration options related to the dot tool
+#---------------------------------------------------------------------------
+
+# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will
+# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base
+# or super classes. Setting the tag to NO turns the diagrams off. Note that
+# this option also works with HAVE_DOT disabled, but it is recommended to
+# install and use dot, since it yields more powerful graphs.
+
+CLASS_DIAGRAMS = YES
+
+# You can define message sequence charts within doxygen comments using the \msc
+# command. Doxygen will then run the mscgen tool (see
+# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the
+# documentation. The MSCGEN_PATH tag allows you to specify the directory where
+# the mscgen tool resides. If left empty the tool is assumed to be found in the
+# default search path.
+
+MSCGEN_PATH =
+
+# If set to YES, the inheritance and collaboration graphs will hide
+# inheritance and usage relations if the target is undocumented
+# or is not a class.
+
+HIDE_UNDOC_RELATIONS = YES
+
+# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is
+# available from the path. This tool is part of Graphviz, a graph visualization
+# toolkit from AT&T and Lucent Bell Labs. The other options in this section
+# have no effect if this option is set to NO (the default)
+
+HAVE_DOT = YES
+
+# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is
+# allowed to run in parallel. When set to 0 (the default) doxygen will
+# base this on the number of processors available in the system. You can set it
+# explicitly to a value larger than 0 to get control over the balance
+# between CPU load and processing speed.
+
+DOT_NUM_THREADS = 0
+
+# By default doxygen will use the Helvetica font for all dot files that
+# doxygen generates. When you want a differently looking font you can specify
+# the font name using DOT_FONTNAME. You need to make sure dot is able to find
+# the font, which can be done by putting it in a standard location or by setting
+# the DOTFONTPATH environment variable or by setting DOT_FONTPATH to the
+# directory containing the font.
+
+DOT_FONTNAME = Helvetica
+
+# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs.
+# The default size is 10pt.
+
+DOT_FONTSIZE = 10
+
+# By default doxygen will tell dot to use the Helvetica font.
+# If you specify a different font using DOT_FONTNAME you can use DOT_FONTPATH to
+# set the path where dot can find it.
+
+DOT_FONTPATH =
+
+# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen
+# will generate a graph for each documented class showing the direct and
+# indirect inheritance relations. Setting this tag to YES will force the
+# CLASS_DIAGRAMS tag to NO.
+
+CLASS_GRAPH = YES
+
+# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen
+# will generate a graph for each documented class showing the direct and
+# indirect implementation dependencies (inheritance, containment, and
+# class references variables) of the class with other documented classes.
+
+COLLABORATION_GRAPH = YES
+
+# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen
+# will generate a graph for groups, showing the direct groups dependencies
+
+GROUP_GRAPHS = YES
+
+# If the UML_LOOK tag is set to YES doxygen will generate inheritance and
+# collaboration diagrams in a style similar to the OMG's Unified Modeling
+# Language.
+
+UML_LOOK = NO
+
+# If the UML_LOOK tag is enabled, the fields and methods are shown inside
+# the class node. If there are many fields or methods and many nodes the
+# graph may become too big to be useful. The UML_LIMIT_NUM_FIELDS
+# threshold limits the number of items for each type to make the size more
+# managable. Set this to 0 for no limit. Note that the threshold may be
+# exceeded by 50% before the limit is enforced.
+
+UML_LIMIT_NUM_FIELDS = 10
+
+# If set to YES, the inheritance and collaboration graphs will show the
+# relations between templates and their instances.
+
+TEMPLATE_RELATIONS = NO
+
+# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT
+# tags are set to YES then doxygen will generate a graph for each documented
+# file showing the direct and indirect include dependencies of the file with
+# other documented files.
+
+INCLUDE_GRAPH = YES
+
+# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and
+# HAVE_DOT tags are set to YES then doxygen will generate a graph for each
+# documented header file showing the documented files that directly or
+# indirectly include this file.
+
+INCLUDED_BY_GRAPH = YES
+
+# If the CALL_GRAPH and HAVE_DOT options are set to YES then
+# doxygen will generate a call dependency graph for every global function
+# or class method. Note that enabling this option will significantly increase
+# the time of a run. So in most cases it will be better to enable call graphs
+# for selected functions only using the \callgraph command.
+
+CALL_GRAPH = YES
+
+# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then
+# doxygen will generate a caller dependency graph for every global function
+# or class method. Note that enabling this option will significantly increase
+# the time of a run. So in most cases it will be better to enable caller
+# graphs for selected functions only using the \callergraph command.
+
+CALLER_GRAPH = YES
+
+# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen
+# will generate a graphical hierarchy of all classes instead of a textual one.
+
+GRAPHICAL_HIERARCHY = YES
+
+# If the DIRECTORY_GRAPH and HAVE_DOT tags are set to YES
+# then doxygen will show the dependencies a directory has on other directories
+# in a graphical way. The dependency relations are determined by the #include
+# relations between the files in the directories.
+
+DIRECTORY_GRAPH = YES
+
+# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images
+# generated by dot. Possible values are svg, png, jpg, or gif.
+# If left blank png will be used. If you choose svg you need to set
+# HTML_FILE_EXTENSION to xhtml in order to make the SVG files
+# visible in IE 9+ (other browsers do not have this requirement).
+
+DOT_IMAGE_FORMAT = png
+
+# If DOT_IMAGE_FORMAT is set to svg, then this option can be set to YES to
+# enable generation of interactive SVG images that allow zooming and panning.
+# Note that this requires a modern browser other than Internet Explorer.
+# Tested and working are Firefox, Chrome, Safari, and Opera. For IE 9+ you
+# need to set HTML_FILE_EXTENSION to xhtml in order to make the SVG files
+# visible. Older versions of IE do not have SVG support.
+
+INTERACTIVE_SVG = NO
+
+# The tag DOT_PATH can be used to specify the path where the dot tool can be
+# found. If left blank, it is assumed the dot tool can be found in the path.
+
+DOT_PATH =
+
+# The DOTFILE_DIRS tag can be used to specify one or more directories that
+# contain dot files that are included in the documentation (see the
+# \dotfile command).
+
+DOTFILE_DIRS =
+
+# The MSCFILE_DIRS tag can be used to specify one or more directories that
+# contain msc files that are included in the documentation (see the
+# \mscfile command).
+
+MSCFILE_DIRS =
+
+# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of
+# nodes that will be shown in the graph. If the number of nodes in a graph
+# becomes larger than this value, doxygen will truncate the graph, which is
+# visualized by representing a node as a red box. Note that doxygen if the
+# number of direct children of the root node in a graph is already larger than
+# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note
+# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH.
+
+DOT_GRAPH_MAX_NODES = 50
+
+# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the
+# graphs generated by dot. A depth value of 3 means that only nodes reachable
+# from the root by following a path via at most 3 edges will be shown. Nodes
+# that lay further from the root node will be omitted. Note that setting this
+# option to 1 or 2 may greatly reduce the computation time needed for large
+# code bases. Also note that the size of a graph can be further restricted by
+# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction.
+
+MAX_DOT_GRAPH_DEPTH = 0
+
+# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent
+# background. This is disabled by default, because dot on Windows does not
+# seem to support this out of the box. Warning: Depending on the platform used,
+# enabling this option may lead to badly anti-aliased labels on the edges of
+# a graph (i.e. they become hard to read).
+
+DOT_TRANSPARENT = NO
+
+# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output
+# files in one run (i.e. multiple -o and -T options on the command line). This
+# makes dot run faster, but since only newer versions of dot (>1.8.10)
+# support this, this feature is disabled by default.
+
+DOT_MULTI_TARGETS = YES
+
+# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will
+# generate a legend page explaining the meaning of the various boxes and
+# arrows in the dot generated graphs.
+
+GENERATE_LEGEND = YES
+
+# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will
+# remove the intermediate dot files that are used to generate
+# the various graphs.
+
+DOT_CLEANUP = YES
+
diff --git a/libopencm3/doc/DoxygenLayout.xml b/libopencm3/doc/DoxygenLayout.xml
new file mode 100644
index 0000000..a01b621
--- /dev/null
+++ b/libopencm3/doc/DoxygenLayout.xml
@@ -0,0 +1,195 @@
+
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diff --git a/libopencm3/doc/HACKING b/libopencm3/doc/HACKING
new file mode 100644
index 0000000..d67684b
--- /dev/null
+++ b/libopencm3/doc/HACKING
@@ -0,0 +1,114 @@
+libopencm3 Documentation
+12 October 2012 (C) K Sarkies
+-----------------------------
+
+Each family and subfamily of devices has a separate directory and configuration
+files. Doxygen is run independently on each of these and the result is
+integrated under a single HTML page. LaTeX and pdf files are produced
+separately. Due to relative referencing used in the files, the directory
+structure is important and should be maintained.
+
+Each of the subdirectories has a configuration file, a layout file and
+subdirectories for the documentation. Doxygen is intended to be run inside
+these subdirectories. The Makefile will handle this in the appropriate
+order.
+
+Markup
+------
+
+Each family has been given a group name that will allow subgrouping of API
+functions and defines in the documentation.
+
+The header and source files for each peripheral in each family must have a
+heading section in which an @defgroup defines the group name for the particular
+peripheral. This group name will be the same across all families as each one
+is documented separately. Thus for a peripheral xxx the header will have a
+group name xxx_defines and the source file will have xxx_file. This will allow
+the group to appear separately. An @ingroup must be provided to place the group
+as a subgroup of the appropriate family grouping. Note that @file is not used.
+
+The heading section must include the version number and date and authors names
+plus a license reference. Any documentation specific to the family can be
+included here. If there are common files included then their documentation will
+appear in a separate section.
+
+Common header and source files that are included into a number of families must
+have an @addgroup to include its documentation into the appropriate peripheral
+group. These headings may include authors and any specific descriptions but the
+date and version number must be omitted as it will be included from the family
+files. There must not be any reference to family groupings as these common files
+will be incorporated into multiple family groups.
+
+The common files should not be included in an application explicitly. Also the
+doxygen preprocessor must be enabled to ensure that all macros and defines are
+included. This means that common header files need to have a section at the top
+of the file of the type (eg for gpio_common_f24.h):
+
+/** @cond */
+#ifdef LIBOPENCM3_GPIO_H
+/** @endcond */
+
+and at the end of the file:
+
+/** @cond */
+#else
+#warning "gpio_common_f24.h should not be included explicitly, only via gpio.h"
+#endif
+/** @endcond */
+
+This will stop the compiler preprocessor from including the common header file
+unless the device family header file has also been included. The doxygen
+conditional clauses are needed to stop the doxygen preprocessor seeing this
+statement and so excluding processing of the common file contents.
+
+/** @cond */
+#if defined(LIBOPENCM3_GPIO_H) || defined(LIBOPENCM3_GPIO_COMMON_F24_H)
+/** @endcond */
+
+Each helper function must have a header with an @brief, and where appropriate
+additional description, @parameter and @return elements. These latter must
+describe the allowable parameter ranges preferably with reference to a suitable
+define in the corresponding header file.
+
+The Doxyfile for a family must include input files from the header and source
+subdirectories, as well as all needed common files. The common files can be
+added separately or as an entire directory with exclusions of inappropriate
+files.
+
+Doxyfiles
+---------
+
+Doxyfile_common holds global settings.
+
+OUTPUT_DIRECTORY blank so that the output is placed in the current directory.
+RECURSIVE = NO
+EXTERNAL_GROUPS = NO
+
+Each Doxyfile_include for a processor family has:
+
+@INCLUDE = ../Doxyfile_common
+INPUT = specific directories needed, including /include/libopencm3/cm3
+ in top directory to set the top level page and GNU license.
+LAYOUT_FILE = DoxygenLayout_$processor.xml
+WARN_LOGFILE = doxygen_$processor.log
+TAGFILES = ../cm3/cm3.tag=../../cm3/html
+GENERATE_TAGFILE = $processor.tag
+PREDEFINED = list of macro definitions
+
+For the top level Doxyfile
+
+INPUT = ../include/libopencm3/docmain.dox to add in the main page text
+LAYOUT_FILE = DoxygenLayout.xml
+WARN_LOGFILE = doxygen.log
+TAGFILES = cm3/cm3.tag=../cm3/html plus all families to be included.
+
+Generation of PDF
+-----------------
+
+The needs for pdf documents differ from HTML so separate Doxyfile_latex
+files are provided.
+
+@INCLUDE = ../Doxyfile_common
+GENERATE_LATEX = YES
+GENERATE_HTML = NO
+
diff --git a/libopencm3/doc/Makefile b/libopencm3/doc/Makefile
new file mode 100644
index 0000000..95e394c
--- /dev/null
+++ b/libopencm3/doc/Makefile
@@ -0,0 +1,145 @@
+# Makefile to build libopencm3 documentation
+
+# 14 September 2012
+# (C) Ken Sarkies
+
+doc: html latex
+
+html: cm3 usb stm32l1 stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 efm32g efm32gg efm32lg efm32tg lm3s lm4f lpc13 lpc17 lpc43 sam3a sam3n sam3s sam3u sam3x top
+
+cm3:
+ cd cm3/; doxygen
+
+usb:
+ cd usb/; doxygen
+
+lm3s:
+ cd lm3s/; doxygen
+
+lm4f:
+ cd lm4f/; doxygen
+
+efm32g:
+ cd efm32g/; doxygen
+
+efm32gg:
+ cd efm32gg/; doxygen
+
+efm32lg:
+ cd efm32lg/; doxygen
+
+efm32tg:
+ cd efm32tg/; doxygen
+
+lpc13:
+ cd lpc13xx/; doxygen
+
+lpc17:
+ cd lpc17xx/; doxygen
+
+lpc43:
+ cd lpc43xx/; doxygen
+
+stm32f0:
+ cd stm32f0/; doxygen
+
+stm32f1:
+ cd stm32f1/; doxygen
+
+stm32f2:
+ cd stm32f2/; doxygen
+
+stm32f3:
+ cd stm32f3/; doxygen
+
+stm32f4:
+ cd stm32f4/; doxygen
+
+stm32l1:
+ cd stm32l1/; doxygen
+
+sam3a:
+ cd sam3a/; doxygen
+
+sam3n:
+ cd sam3n/; doxygen
+
+sam3s:
+ cd sam3s/; doxygen
+
+sam3u:
+ cd sam3u/; doxygen
+
+sam3x:
+ cd sam3x/; doxygen
+
+top:
+ doxygen
+
+latex: stm32l1.pdf stm32f0.pdf stm32f1.pdf stm32f2.pdf stm32f3.pdf stm32f4.pdf lm3s.pdf lm4f.pdf lpc13.pdf lpc17.pdf lpc43.pdf efm32g.pdf efm32gg.pdf efm32lg.pdf efm32tg.pdf sam3a.pdf sam3n.pdf sam3s.pdf sam3u.pdf sam3x.pdf
+
+stm32l1.pdf:
+ cd stm32l1/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../stm32l1.pdf
+
+stm32f0.pdf:
+ cd stm32f0/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../stm32f0.pdf
+
+stm32f1.pdf:
+ cd stm32f1/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../stm32f1.pdf
+
+stm32f2.pdf:
+ cd stm32f2/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../stm32f2.pdf
+
+stm32f3.pdf:
+ cd stm32f3/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../stm32f3.pdf
+
+stm32f4.pdf:
+ cd stm32f4/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../stm32f4.pdf
+
+lm3s.pdf:
+ cd lm3s/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../lm3s.pdf
+
+lm4f.pdf:
+ cd lm4f/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../lm4f.pdf
+
+lpc13.pdf:
+ cd lpc13xx/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../lpc13.pdf
+
+lpc17.pdf:
+ cd lpc17xx/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../lpc17.pdf
+
+lpc43.pdf:
+ cd lpc43xx/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../lpc43.pdf
+
+efm32g.pdf:
+ cd efm32g/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../efm32g.pdf
+
+efm32gg.pdf:
+ cd efm32gg/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../efm32gg.pdf
+
+efm32lg.pdf:
+ cd efm32lg/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../efm32lg.pdf
+
+efm32tg.pdf:
+ cd efm32tg/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../efm32tg.pdf
+
+sam3a.pdf:
+ cd sam3a/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../sam3a.pdf
+
+sam3n.pdf:
+ cd sam3n/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../sam3n.pdf
+
+sam3s.pdf:
+ cd sam3s/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../sam3s.pdf
+
+sam3u.pdf:
+ cd sam3u/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../sam3u.pdf
+
+sam3x.pdf:
+ cd sam3x/; doxygen Doxyfile_latex; cd latex/; $(MAKE); cp refman.pdf ../../sam3x.pdf
+
+clean:
+ @rm -rf html/ */html/ */latex/ *.pdf */*.tag
+
+.PHONY: doc html cm3 usb lm3s lm4f lpc13 lpc17 lpc43 stm32l1 stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 efm32g efm32gg efm32lg efm32tg sam3a sam3n sam3s sam3u sam3x top latex
+
diff --git a/libopencm3/doc/README b/libopencm3/doc/README
new file mode 100644
index 0000000..a7ac627
--- /dev/null
+++ b/libopencm3/doc/README
@@ -0,0 +1,34 @@
+libopencm3 Documentation
+14 September 2012 (C) K Sarkies
+-------------------------------
+
+To generate all documentation run 'make doc' in the doc directory, or
+for html documentation only run 'make html' (much faster). This runs doxygen
+for each of the processor families then integrates the whole.
+
+Alternatively run 'make doc' in the top directory to make html documentation.
+LaTeX and pdf documentation is currently very large in size.
+
+This requires doxygen v 1.8.2 or later.
+
+HTML, LaTeX, and pdf output can be produced.
+
+Generation of HTML
+------------------
+
+To view HTML, point a browser to libopencm3/doc/html/index.html.
+
+Generation of PDF
+-----------------
+
+The pdf is generated via LaTeX. The pdf files are placed in the
+doc directory. Each file contains all documentation for the core and common
+features. The resulting files are huge.
+
+
+Requirements
+------------
+On Fedora 19, the following packages (at least!) are needed to build the pdf
+output
+
+ texlive texlive-sectsty texlive-tocloft texlive-xtab texlive-multirow
diff --git a/libopencm3/doc/cm3/Doxyfile b/libopencm3/doc/cm3/Doxyfile
new file mode 100644
index 0000000..7cf6496
--- /dev/null
+++ b/libopencm3/doc/cm3/Doxyfile
@@ -0,0 +1,24 @@
+# HTML Documentation for CM3 Core features.
+
+# 14 September 2012
+# (C) Ken Sarkies
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_cm3.log
+
+INPUT = ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/cm3/
+
+LAYOUT_FILE = DoxygenLayout_cm3.xml
+
+GENERATE_TAGFILE = cm3.tag
+
diff --git a/libopencm3/doc/cm3/DoxygenLayout_cm3.xml b/libopencm3/doc/cm3/DoxygenLayout_cm3.xml
new file mode 100644
index 0000000..c4219af
--- /dev/null
+++ b/libopencm3/doc/cm3/DoxygenLayout_cm3.xml
@@ -0,0 +1,205 @@
+
+
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diff --git a/libopencm3/doc/efm32g/Doxyfile b/libopencm3/doc/efm32g/Doxyfile
new file mode 100644
index 0000000..a3a65c7
--- /dev/null
+++ b/libopencm3/doc/efm32g/Doxyfile
@@ -0,0 +1,30 @@
+# HTML Documentation for efm32 code level
+
+# 11 November 2012
+# (C) Ken Sarkies
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_efm32g.log
+
+INPUT = ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/efm32/efm32g \
+ ../../lib/efm32/efm32g
+
+EXCLUDE =
+
+LAYOUT_FILE = DoxygenLayout_efm32g.xml
+
+GENERATE_TAGFILE = efm32g.tag
+
+ENABLE_PREPROCESSING = YES
+
+
diff --git a/libopencm3/doc/efm32g/Doxyfile_latex b/libopencm3/doc/efm32g/Doxyfile_latex
new file mode 100644
index 0000000..47373f0
--- /dev/null
+++ b/libopencm3/doc/efm32g/Doxyfile_latex
@@ -0,0 +1,32 @@
+# LaTeX Documentation for efm32 code level
+
+# 12 November 2012
+# (C) Ken Sarkies
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_efm32g_latex.log
+
+INPUT = ../../include/libopencm3/docmain.dox \
+ ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/efm32/efm32g \
+ ../../lib/efm32/efm32g
+
+EXCLUDE = ../../include/libopencm3/efm32/doc-efm32g.h
+
+LAYOUT_FILE = DoxygenLayout_efm32g.xml
+
+GENERATE_HTML = NO
+
+GENERATE_LATEX = YES
+
+LATEX_HEADER = header_efm32g.tex
+
diff --git a/libopencm3/doc/efm32g/DoxygenLayout_efm32g.xml b/libopencm3/doc/efm32g/DoxygenLayout_efm32g.xml
new file mode 100644
index 0000000..9ace984
--- /dev/null
+++ b/libopencm3/doc/efm32g/DoxygenLayout_efm32g.xml
@@ -0,0 +1,206 @@
+
+
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diff --git a/libopencm3/doc/efm32g/header_efm32g.tex b/libopencm3/doc/efm32g/header_efm32g.tex
new file mode 100644
index 0000000..43a3ea6
--- /dev/null
+++ b/libopencm3/doc/efm32g/header_efm32g.tex
@@ -0,0 +1,61 @@
+\documentclass{book}
+\usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry}
+\usepackage{makeidx}
+\usepackage{natbib}
+\usepackage{graphicx}
+\usepackage{multicol}
+\usepackage{float}
+\usepackage{listings}
+\usepackage{color}
+\usepackage{ifthen}
+\usepackage[table]{xcolor}
+\usepackage{textcomp}
+\usepackage{alltt}
+\usepackage{ifpdf}
+\ifpdf
+\usepackage[pdftex,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\else
+\usepackage[ps2pdf,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\usepackage{pspicture}
+\fi
+\usepackage[utf8]{inputenc}
+\usepackage{mathptmx}
+\usepackage[scaled=.90]{helvet}
+\usepackage{courier}
+\usepackage{sectsty}
+\usepackage{amssymb}
+\usepackage[titles]{tocloft}
+\usepackage{doxygen}
+\lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left }
+\makeindex
+\setcounter{tocdepth}{3}
+\renewcommand{\footrulewidth}{0.4pt}
+\renewcommand{\familydefault}{\sfdefault}
+\hfuzz=15pt
+\setlength{\emergencystretch}{15pt}
+\hbadness=750
+\tolerance=750
+\begin{document}
+\hypersetup{pageanchor=false,citecolor=blue}
+\begin{titlepage}
+\vspace*{7cm}
+\begin{center}
+{\Huge libopencm3: API Reference\\ EFM32 Gecko ARM Cortex M3 Series}\\
+\vspace*{1cm}
+{\large Generated by Doxygen 1.8.2}\\
+\vspace*{0.5cm}
+{\small Thu Sep 13 2012 23:26:45}\\
+\end{center}
+\end{titlepage}
+\pagenumbering{arabic}
+\hypersetup{pageanchor=true,citecolor=blue}
diff --git a/libopencm3/doc/efm32gg/Doxyfile b/libopencm3/doc/efm32gg/Doxyfile
new file mode 100644
index 0000000..1b93900
--- /dev/null
+++ b/libopencm3/doc/efm32gg/Doxyfile
@@ -0,0 +1,30 @@
+# HTML Documentation for efm32 code level
+
+# 11 November 2012
+# (C) Ken Sarkies
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_efm32gg.log
+
+INPUT = ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/efm32/efm32gg \
+ ../../lib/efm32/efm32gg
+
+EXCLUDE =
+
+LAYOUT_FILE = DoxygenLayout_efm32gg.xml
+
+GENERATE_TAGFILE = efm32gg.tag
+
+ENABLE_PREPROCESSING = YES
+
+
diff --git a/libopencm3/doc/efm32gg/Doxyfile_latex b/libopencm3/doc/efm32gg/Doxyfile_latex
new file mode 100644
index 0000000..2f1f8fd
--- /dev/null
+++ b/libopencm3/doc/efm32gg/Doxyfile_latex
@@ -0,0 +1,32 @@
+# LaTeX Documentation for efm32 code level
+
+# 12 November 2012
+# (C) Ken Sarkies
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_efm32gg_latex.log
+
+INPUT = ../../include/libopencm3/docmain.dox \
+ ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/efm32/efm32gg \
+ ../../lib/efm32/efm32gg
+
+EXCLUDE = ../../include/libopencm3/efm32/doc-efm32gg.h
+
+LAYOUT_FILE = DoxygenLayout_efm32gg.xml
+
+GENERATE_HTML = NO
+
+GENERATE_LATEX = YES
+
+LATEX_HEADER = header_efm32gg.tex
+
diff --git a/libopencm3/doc/efm32gg/DoxygenLayout_efm32gg.xml b/libopencm3/doc/efm32gg/DoxygenLayout_efm32gg.xml
new file mode 100644
index 0000000..ab7fb34
--- /dev/null
+++ b/libopencm3/doc/efm32gg/DoxygenLayout_efm32gg.xml
@@ -0,0 +1,206 @@
+
+
+
+
+
+
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diff --git a/libopencm3/doc/efm32gg/header_efm32gg.tex b/libopencm3/doc/efm32gg/header_efm32gg.tex
new file mode 100644
index 0000000..55288fb
--- /dev/null
+++ b/libopencm3/doc/efm32gg/header_efm32gg.tex
@@ -0,0 +1,61 @@
+\documentclass{book}
+\usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry}
+\usepackage{makeidx}
+\usepackage{natbib}
+\usepackage{graphicx}
+\usepackage{multicol}
+\usepackage{float}
+\usepackage{listings}
+\usepackage{color}
+\usepackage{ifthen}
+\usepackage[table]{xcolor}
+\usepackage{textcomp}
+\usepackage{alltt}
+\usepackage{ifpdf}
+\ifpdf
+\usepackage[pdftex,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\else
+\usepackage[ps2pdf,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\usepackage{pspicture}
+\fi
+\usepackage[utf8]{inputenc}
+\usepackage{mathptmx}
+\usepackage[scaled=.90]{helvet}
+\usepackage{courier}
+\usepackage{sectsty}
+\usepackage{amssymb}
+\usepackage[titles]{tocloft}
+\usepackage{doxygen}
+\lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left }
+\makeindex
+\setcounter{tocdepth}{3}
+\renewcommand{\footrulewidth}{0.4pt}
+\renewcommand{\familydefault}{\sfdefault}
+\hfuzz=15pt
+\setlength{\emergencystretch}{15pt}
+\hbadness=750
+\tolerance=750
+\begin{document}
+\hypersetup{pageanchor=false,citecolor=blue}
+\begin{titlepage}
+\vspace*{7cm}
+\begin{center}
+{\Huge libopencm3: API Reference\\ EFM32 Giant Gecko ARM Cortex M3 Series}\\
+\vspace*{1cm}
+{\large Generated by Doxygen 1.8.2}\\
+\vspace*{0.5cm}
+{\small Thu Sep 13 2012 23:26:45}\\
+\end{center}
+\end{titlepage}
+\pagenumbering{arabic}
+\hypersetup{pageanchor=true,citecolor=blue}
diff --git a/libopencm3/doc/efm32lg/Doxyfile b/libopencm3/doc/efm32lg/Doxyfile
new file mode 100644
index 0000000..2139da5
--- /dev/null
+++ b/libopencm3/doc/efm32lg/Doxyfile
@@ -0,0 +1,30 @@
+# HTML Documentation for efm32 code level
+
+# 11 November 2012
+# (C) Ken Sarkies
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_efm32lg.log
+
+INPUT = ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/efm32/efm32lg \
+ ../../lib/efm32/efm32lg
+
+EXCLUDE =
+
+LAYOUT_FILE = DoxygenLayout_efm32lg.xml
+
+GENERATE_TAGFILE = efm32lg.tag
+
+ENABLE_PREPROCESSING = YES
+
+
diff --git a/libopencm3/doc/efm32lg/Doxyfile_latex b/libopencm3/doc/efm32lg/Doxyfile_latex
new file mode 100644
index 0000000..0b8ed0d
--- /dev/null
+++ b/libopencm3/doc/efm32lg/Doxyfile_latex
@@ -0,0 +1,32 @@
+# LaTeX Documentation for efm32 code level
+
+# 12 November 2012
+# (C) Ken Sarkies
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_efm32lg_latex.log
+
+INPUT = ../../include/libopencm3/docmain.dox \
+ ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/efm32/efm32lg \
+ ../../lib/efm32/efm32lg
+
+EXCLUDE = ../../include/libopencm3/efm32/doc-efm32lg.h
+
+LAYOUT_FILE = DoxygenLayout_efm32lg.xml
+
+GENERATE_HTML = NO
+
+GENERATE_LATEX = YES
+
+LATEX_HEADER = header_efm32lg.tex
+
diff --git a/libopencm3/doc/efm32lg/DoxygenLayout_efm32lg.xml b/libopencm3/doc/efm32lg/DoxygenLayout_efm32lg.xml
new file mode 100644
index 0000000..fd07092
--- /dev/null
+++ b/libopencm3/doc/efm32lg/DoxygenLayout_efm32lg.xml
@@ -0,0 +1,206 @@
+
+
+
+
+
+
+
+
+
+
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diff --git a/libopencm3/doc/efm32lg/header_efm32lg.tex b/libopencm3/doc/efm32lg/header_efm32lg.tex
new file mode 100644
index 0000000..900752c
--- /dev/null
+++ b/libopencm3/doc/efm32lg/header_efm32lg.tex
@@ -0,0 +1,61 @@
+\documentclass{book}
+\usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry}
+\usepackage{makeidx}
+\usepackage{natbib}
+\usepackage{graphicx}
+\usepackage{multicol}
+\usepackage{float}
+\usepackage{listings}
+\usepackage{color}
+\usepackage{ifthen}
+\usepackage[table]{xcolor}
+\usepackage{textcomp}
+\usepackage{alltt}
+\usepackage{ifpdf}
+\ifpdf
+\usepackage[pdftex,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\else
+\usepackage[ps2pdf,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\usepackage{pspicture}
+\fi
+\usepackage[utf8]{inputenc}
+\usepackage{mathptmx}
+\usepackage[scaled=.90]{helvet}
+\usepackage{courier}
+\usepackage{sectsty}
+\usepackage{amssymb}
+\usepackage[titles]{tocloft}
+\usepackage{doxygen}
+\lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left }
+\makeindex
+\setcounter{tocdepth}{3}
+\renewcommand{\footrulewidth}{0.4pt}
+\renewcommand{\familydefault}{\sfdefault}
+\hfuzz=15pt
+\setlength{\emergencystretch}{15pt}
+\hbadness=750
+\tolerance=750
+\begin{document}
+\hypersetup{pageanchor=false,citecolor=blue}
+\begin{titlepage}
+\vspace*{7cm}
+\begin{center}
+{\Huge libopencm3: API Reference\\ EFM32 Leopard Gecko ARM Cortex M3 Series}\\
+\vspace*{1cm}
+{\large Generated by Doxygen 1.8.2}\\
+\vspace*{0.5cm}
+{\small Thu Sep 13 2012 23:26:45}\\
+\end{center}
+\end{titlepage}
+\pagenumbering{arabic}
+\hypersetup{pageanchor=true,citecolor=blue}
diff --git a/libopencm3/doc/efm32tg/Doxyfile b/libopencm3/doc/efm32tg/Doxyfile
new file mode 100644
index 0000000..1610f21
--- /dev/null
+++ b/libopencm3/doc/efm32tg/Doxyfile
@@ -0,0 +1,30 @@
+# HTML Documentation for efm32 code level
+
+# 11 November 2012
+# (C) Ken Sarkies
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_efm32tg.log
+
+INPUT = ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/efm32/efm32tg \
+ ../../lib/efm32/efm32tg
+
+EXCLUDE =
+
+LAYOUT_FILE = DoxygenLayout_efm32tg.xml
+
+GENERATE_TAGFILE = efm32tg.tag
+
+ENABLE_PREPROCESSING = YES
+
+
diff --git a/libopencm3/doc/efm32tg/Doxyfile_latex b/libopencm3/doc/efm32tg/Doxyfile_latex
new file mode 100644
index 0000000..adca3de
--- /dev/null
+++ b/libopencm3/doc/efm32tg/Doxyfile_latex
@@ -0,0 +1,32 @@
+# LaTeX Documentation for efm32 code level
+
+# 12 November 2012
+# (C) Ken Sarkies
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_efm32tg_latex.log
+
+INPUT = ../../include/libopencm3/docmain.dox \
+ ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/efm32/efm32tg \
+ ../../lib/efm32/efm32tg
+
+EXCLUDE = ../../include/libopencm3/efm32/doc-efm32tg.h
+
+LAYOUT_FILE = DoxygenLayout_efm32tg.xml
+
+GENERATE_HTML = NO
+
+GENERATE_LATEX = YES
+
+LATEX_HEADER = header_efm32tg.tex
+
diff --git a/libopencm3/doc/efm32tg/DoxygenLayout_efm32tg.xml b/libopencm3/doc/efm32tg/DoxygenLayout_efm32tg.xml
new file mode 100644
index 0000000..f27b114
--- /dev/null
+++ b/libopencm3/doc/efm32tg/DoxygenLayout_efm32tg.xml
@@ -0,0 +1,206 @@
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diff --git a/libopencm3/doc/efm32tg/header_efm32tg.tex b/libopencm3/doc/efm32tg/header_efm32tg.tex
new file mode 100644
index 0000000..625e7fa
--- /dev/null
+++ b/libopencm3/doc/efm32tg/header_efm32tg.tex
@@ -0,0 +1,61 @@
+\documentclass{book}
+\usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry}
+\usepackage{makeidx}
+\usepackage{natbib}
+\usepackage{graphicx}
+\usepackage{multicol}
+\usepackage{float}
+\usepackage{listings}
+\usepackage{color}
+\usepackage{ifthen}
+\usepackage[table]{xcolor}
+\usepackage{textcomp}
+\usepackage{alltt}
+\usepackage{ifpdf}
+\ifpdf
+\usepackage[pdftex,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\else
+\usepackage[ps2pdf,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\usepackage{pspicture}
+\fi
+\usepackage[utf8]{inputenc}
+\usepackage{mathptmx}
+\usepackage[scaled=.90]{helvet}
+\usepackage{courier}
+\usepackage{sectsty}
+\usepackage{amssymb}
+\usepackage[titles]{tocloft}
+\usepackage{doxygen}
+\lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left }
+\makeindex
+\setcounter{tocdepth}{3}
+\renewcommand{\footrulewidth}{0.4pt}
+\renewcommand{\familydefault}{\sfdefault}
+\hfuzz=15pt
+\setlength{\emergencystretch}{15pt}
+\hbadness=750
+\tolerance=750
+\begin{document}
+\hypersetup{pageanchor=false,citecolor=blue}
+\begin{titlepage}
+\vspace*{7cm}
+\begin{center}
+{\Huge libopencm3: API Reference\\ EFM32 Tiny Gecko ARM Cortex M3 Series}\\
+\vspace*{1cm}
+{\large Generated by Doxygen 1.8.2}\\
+\vspace*{0.5cm}
+{\small Thu Sep 13 2012 23:26:45}\\
+\end{center}
+\end{titlepage}
+\pagenumbering{arabic}
+\hypersetup{pageanchor=true,citecolor=blue}
diff --git a/libopencm3/doc/index.html b/libopencm3/doc/index.html
new file mode 100644
index 0000000..7715877
--- /dev/null
+++ b/libopencm3/doc/index.html
@@ -0,0 +1,8 @@
+
+
+
+
+
+ Documentation index
+
+
diff --git a/libopencm3/doc/lm3s/Doxyfile b/libopencm3/doc/lm3s/Doxyfile
new file mode 100644
index 0000000..d7feff2
--- /dev/null
+++ b/libopencm3/doc/lm3s/Doxyfile
@@ -0,0 +1,28 @@
+# HTML Documentation for LM3S code level
+
+# 14 September 2012
+# (C) Ken Sarkies
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_lm3s.log
+
+INPUT = ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/lm3s \
+ ../../lib/lm3s
+
+LAYOUT_FILE = DoxygenLayout_lm3s.xml
+
+GENERATE_TAGFILE = lm3s.tag
+
+ENABLE_PREPROCESSING = YES
+
+
diff --git a/libopencm3/doc/lm3s/Doxyfile_latex b/libopencm3/doc/lm3s/Doxyfile_latex
new file mode 100644
index 0000000..1cff565
--- /dev/null
+++ b/libopencm3/doc/lm3s/Doxyfile_latex
@@ -0,0 +1,32 @@
+# LaTeX Documentation for LM3S code level
+
+# 14 September 2012
+# (C) Ken Sarkies
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_lm3s_latex.log
+
+INPUT = ../../include/libopencm3/docmain.dox \
+ ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/lm3s \
+ ../../lib/lm3s
+
+EXCLUDE = ../../include/libopencm3/lm3s/doc-lm3s.h
+
+LAYOUT_FILE = DoxygenLayout_lm3s.xml
+
+GENERATE_HTML = NO
+
+GENERATE_LATEX = YES
+
+LATEX_HEADER = header_lm3s.tex
+
diff --git a/libopencm3/doc/lm3s/DoxygenLayout_lm3s.xml b/libopencm3/doc/lm3s/DoxygenLayout_lm3s.xml
new file mode 100644
index 0000000..73bb673
--- /dev/null
+++ b/libopencm3/doc/lm3s/DoxygenLayout_lm3s.xml
@@ -0,0 +1,206 @@
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diff --git a/libopencm3/doc/lm3s/header_lm3s.tex b/libopencm3/doc/lm3s/header_lm3s.tex
new file mode 100644
index 0000000..089dce3
--- /dev/null
+++ b/libopencm3/doc/lm3s/header_lm3s.tex
@@ -0,0 +1,61 @@
+\documentclass{book}
+\usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry}
+\usepackage{makeidx}
+\usepackage{natbib}
+\usepackage{graphicx}
+\usepackage{multicol}
+\usepackage{float}
+\usepackage{listings}
+\usepackage{color}
+\usepackage{ifthen}
+\usepackage[table]{xcolor}
+\usepackage{textcomp}
+\usepackage{alltt}
+\usepackage{ifpdf}
+\ifpdf
+\usepackage[pdftex,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\else
+\usepackage[ps2pdf,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\usepackage{pspicture}
+\fi
+\usepackage[utf8]{inputenc}
+\usepackage{mathptmx}
+\usepackage[scaled=.90]{helvet}
+\usepackage{courier}
+\usepackage{sectsty}
+\usepackage{amssymb}
+\usepackage[titles]{tocloft}
+\usepackage{doxygen}
+\lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left }
+\makeindex
+\setcounter{tocdepth}{3}
+\renewcommand{\footrulewidth}{0.4pt}
+\renewcommand{\familydefault}{\sfdefault}
+\hfuzz=15pt
+\setlength{\emergencystretch}{15pt}
+\hbadness=750
+\tolerance=750
+\begin{document}
+\hypersetup{pageanchor=false,citecolor=blue}
+\begin{titlepage}
+\vspace*{7cm}
+\begin{center}
+{\Huge libopencm3: API Reference\\ TI LM3S ARM Cortex M3 Series}\\
+\vspace*{1cm}
+{\large Generated by Doxygen 1.8.2}\\
+\vspace*{0.5cm}
+{\small Thu Sep 13 2012 23:26:45}\\
+\end{center}
+\end{titlepage}
+\pagenumbering{arabic}
+\hypersetup{pageanchor=true,citecolor=blue}
diff --git a/libopencm3/doc/lm4f/Doxyfile b/libopencm3/doc/lm4f/Doxyfile
new file mode 100644
index 0000000..284ac7a
--- /dev/null
+++ b/libopencm3/doc/lm4f/Doxyfile
@@ -0,0 +1,28 @@
+# HTML Documentation for LM3S code level
+
+# 14 September 2012
+# (C) Ken Sarkies
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_lm4f.log
+
+INPUT = ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/lm4f \
+ ../../lib/lm4f
+
+LAYOUT_FILE = DoxygenLayout_lm4f.xml
+
+GENERATE_TAGFILE = lm4f.tag
+
+ENABLE_PREPROCESSING = YES
+
+
diff --git a/libopencm3/doc/lm4f/Doxyfile_latex b/libopencm3/doc/lm4f/Doxyfile_latex
new file mode 100644
index 0000000..da3c0dd
--- /dev/null
+++ b/libopencm3/doc/lm4f/Doxyfile_latex
@@ -0,0 +1,33 @@
+# LaTeX Documentation for LM3S code level
+
+# 14 September 2012
+# Copyright (C) Ken Sarkies
+# Copyright (C) 2012 Alexandru Gagniuc
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_lm4f_latex.log
+
+INPUT = ../../include/libopencm3/docmain.dox \
+ ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/lm4f \
+ ../../lib/lm4f
+
+EXCLUDE = ../../include/libopencm3/lm4f/doc-lm4f.h
+
+LAYOUT_FILE = DoxygenLayout_lm4f.xml
+
+GENERATE_HTML = NO
+
+GENERATE_LATEX = YES
+
+LATEX_HEADER = header_lm4f.tex
+
diff --git a/libopencm3/doc/lm4f/DoxygenLayout_lm4f.xml b/libopencm3/doc/lm4f/DoxygenLayout_lm4f.xml
new file mode 100644
index 0000000..710c4fc
--- /dev/null
+++ b/libopencm3/doc/lm4f/DoxygenLayout_lm4f.xml
@@ -0,0 +1,206 @@
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diff --git a/libopencm3/doc/lm4f/header_lm4f.tex b/libopencm3/doc/lm4f/header_lm4f.tex
new file mode 100644
index 0000000..68f02ba
--- /dev/null
+++ b/libopencm3/doc/lm4f/header_lm4f.tex
@@ -0,0 +1,61 @@
+\documentclass{book}
+\usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry}
+\usepackage{makeidx}
+\usepackage{natbib}
+\usepackage{graphicx}
+\usepackage{multicol}
+\usepackage{float}
+\usepackage{listings}
+\usepackage{color}
+\usepackage{ifthen}
+\usepackage[table]{xcolor}
+\usepackage{textcomp}
+\usepackage{alltt}
+\usepackage{ifpdf}
+\ifpdf
+\usepackage[pdftex,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\else
+\usepackage[ps2pdf,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\usepackage{pspicture}
+\fi
+\usepackage[utf8]{inputenc}
+\usepackage{mathptmx}
+\usepackage[scaled=.90]{helvet}
+\usepackage{courier}
+\usepackage{sectsty}
+\usepackage{amssymb}
+\usepackage[titles]{tocloft}
+\usepackage{doxygen}
+\lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left }
+\makeindex
+\setcounter{tocdepth}{3}
+\renewcommand{\footrulewidth}{0.4pt}
+\renewcommand{\familydefault}{\sfdefault}
+\hfuzz=15pt
+\setlength{\emergencystretch}{15pt}
+\hbadness=750
+\tolerance=750
+\begin{document}
+\hypersetup{pageanchor=false,citecolor=blue}
+\begin{titlepage}
+\vspace*{7cm}
+\begin{center}
+{\Huge libopencm3: API Reference\\ TI LM4f ARM Cortex M3 Series}\\
+\vspace*{1cm}
+{\large Generated by Doxygen 1.8.2}\\
+\vspace*{0.5cm}
+{\small Thu Sep 13 2012 23:26:45}\\
+\end{center}
+\end{titlepage}
+\pagenumbering{arabic}
+\hypersetup{pageanchor=true,citecolor=blue}
diff --git a/libopencm3/doc/lpc13xx/Doxyfile b/libopencm3/doc/lpc13xx/Doxyfile
new file mode 100644
index 0000000..d8284fc
--- /dev/null
+++ b/libopencm3/doc/lpc13xx/Doxyfile
@@ -0,0 +1,28 @@
+# HTML Documentation for LPC13xx code level
+
+# 14 September 2012
+# (C) Ken Sarkies
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_lpc13xx.log
+
+INPUT = ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/lpc13xx \
+ ../../lib/lpc13xx
+
+LAYOUT_FILE = DoxygenLayout_lpc13xx.xml
+
+GENERATE_TAGFILE = lpc13xx.tag
+
+ENABLE_PREPROCESSING = YES
+
+
diff --git a/libopencm3/doc/lpc13xx/Doxyfile_latex b/libopencm3/doc/lpc13xx/Doxyfile_latex
new file mode 100644
index 0000000..140e908
--- /dev/null
+++ b/libopencm3/doc/lpc13xx/Doxyfile_latex
@@ -0,0 +1,32 @@
+# LaTeX Documentation for LPC13xx code level
+
+# 14 September 2012
+# (C) Ken Sarkies
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_lpc13xx_latex.log
+
+INPUT = ../../include/libopencm3/docmain.dox \
+ ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/lpc13xx/ \
+ ../../lib/lpc13xx
+
+EXCLUDE = ../../include/libopencm3/lpc13xx/doc-lpc13xx.h
+
+LAYOUT_FILE = DoxygenLayout_lpc13xx.xml
+
+GENERATE_HTML = NO
+
+GENERATE_LATEX = YES
+
+LATEX_HEADER = header_lpc13xx.tex
+
diff --git a/libopencm3/doc/lpc13xx/DoxygenLayout_lpc13xx.xml b/libopencm3/doc/lpc13xx/DoxygenLayout_lpc13xx.xml
new file mode 100644
index 0000000..3ca7013
--- /dev/null
+++ b/libopencm3/doc/lpc13xx/DoxygenLayout_lpc13xx.xml
@@ -0,0 +1,205 @@
+
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diff --git a/libopencm3/doc/lpc13xx/header_lpc13xx.tex b/libopencm3/doc/lpc13xx/header_lpc13xx.tex
new file mode 100644
index 0000000..2f50154
--- /dev/null
+++ b/libopencm3/doc/lpc13xx/header_lpc13xx.tex
@@ -0,0 +1,61 @@
+\documentclass{book}
+\usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry}
+\usepackage{makeidx}
+\usepackage{natbib}
+\usepackage{graphicx}
+\usepackage{multicol}
+\usepackage{float}
+\usepackage{listings}
+\usepackage{color}
+\usepackage{ifthen}
+\usepackage[table]{xcolor}
+\usepackage{textcomp}
+\usepackage{alltt}
+\usepackage{ifpdf}
+\ifpdf
+\usepackage[pdftex,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\else
+\usepackage[ps2pdf,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\usepackage{pspicture}
+\fi
+\usepackage[utf8]{inputenc}
+\usepackage{mathptmx}
+\usepackage[scaled=.90]{helvet}
+\usepackage{courier}
+\usepackage{sectsty}
+\usepackage{amssymb}
+\usepackage[titles]{tocloft}
+\usepackage{doxygen}
+\lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left }
+\makeindex
+\setcounter{tocdepth}{3}
+\renewcommand{\footrulewidth}{0.4pt}
+\renewcommand{\familydefault}{\sfdefault}
+\hfuzz=15pt
+\setlength{\emergencystretch}{15pt}
+\hbadness=750
+\tolerance=750
+\begin{document}
+\hypersetup{pageanchor=false,citecolor=blue}
+\begin{titlepage}
+\vspace*{7cm}
+\begin{center}
+{\Huge libopencm3: API Reference\\ NXP LPC13xx ARM Cortex M3 Series}\\
+\vspace*{1cm}
+{\large Generated by Doxygen 1.8.2}\\
+\vspace*{0.5cm}
+{\small Thu Sep 13 2012 23:26:45}\\
+\end{center}
+\end{titlepage}
+\pagenumbering{arabic}
+\hypersetup{pageanchor=true,citecolor=blue}
diff --git a/libopencm3/doc/lpc17xx/Doxyfile b/libopencm3/doc/lpc17xx/Doxyfile
new file mode 100644
index 0000000..0dba663
--- /dev/null
+++ b/libopencm3/doc/lpc17xx/Doxyfile
@@ -0,0 +1,28 @@
+# HTML Documentation for LPC17xx code level
+
+# 14 September 2012
+# (C) Ken Sarkies
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_lpc17xx.log
+
+INPUT = ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/lpc17xx \
+ ../../lib/lpc17xx
+
+LAYOUT_FILE = DoxygenLayout_lpc17xx.xml
+
+GENERATE_TAGFILE = lpc17xx.tag
+
+ENABLE_PREPROCESSING = YES
+
+
diff --git a/libopencm3/doc/lpc17xx/Doxyfile_latex b/libopencm3/doc/lpc17xx/Doxyfile_latex
new file mode 100644
index 0000000..8d3202c
--- /dev/null
+++ b/libopencm3/doc/lpc17xx/Doxyfile_latex
@@ -0,0 +1,32 @@
+# LaTeX Documentation for LPC17xx code level
+
+# 14 September 2012
+# (C) Ken Sarkies
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_lpc17xx_latex.log
+
+INPUT = ../../include/libopencm3/docmain.dox \
+ ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/lpc17xx/ \
+ ../../lib/lpc17xx
+
+EXCLUDE = ../../include/libopencm3/lpc17xx/doc-lpc17xx.h
+
+LAYOUT_FILE = DoxygenLayout_lpc17xx.xml
+
+GENERATE_HTML = NO
+
+GENERATE_LATEX = YES
+
+LATEX_HEADER = header_lpc17xx.tex
+
diff --git a/libopencm3/doc/lpc17xx/DoxygenLayout_lpc17xx.xml b/libopencm3/doc/lpc17xx/DoxygenLayout_lpc17xx.xml
new file mode 100644
index 0000000..278d44f
--- /dev/null
+++ b/libopencm3/doc/lpc17xx/DoxygenLayout_lpc17xx.xml
@@ -0,0 +1,205 @@
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diff --git a/libopencm3/doc/lpc17xx/header_lpc17xx.tex b/libopencm3/doc/lpc17xx/header_lpc17xx.tex
new file mode 100644
index 0000000..3f8539d
--- /dev/null
+++ b/libopencm3/doc/lpc17xx/header_lpc17xx.tex
@@ -0,0 +1,61 @@
+\documentclass{book}
+\usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry}
+\usepackage{makeidx}
+\usepackage{natbib}
+\usepackage{graphicx}
+\usepackage{multicol}
+\usepackage{float}
+\usepackage{listings}
+\usepackage{color}
+\usepackage{ifthen}
+\usepackage[table]{xcolor}
+\usepackage{textcomp}
+\usepackage{alltt}
+\usepackage{ifpdf}
+\ifpdf
+\usepackage[pdftex,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\else
+\usepackage[ps2pdf,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\usepackage{pspicture}
+\fi
+\usepackage[utf8]{inputenc}
+\usepackage{mathptmx}
+\usepackage[scaled=.90]{helvet}
+\usepackage{courier}
+\usepackage{sectsty}
+\usepackage{amssymb}
+\usepackage[titles]{tocloft}
+\usepackage{doxygen}
+\lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left }
+\makeindex
+\setcounter{tocdepth}{3}
+\renewcommand{\footrulewidth}{0.4pt}
+\renewcommand{\familydefault}{\sfdefault}
+\hfuzz=15pt
+\setlength{\emergencystretch}{15pt}
+\hbadness=750
+\tolerance=750
+\begin{document}
+\hypersetup{pageanchor=false,citecolor=blue}
+\begin{titlepage}
+\vspace*{7cm}
+\begin{center}
+{\Huge libopencm3: API Reference\\ NXP LPC17xx ARM Cortex M3 Series}\\
+\vspace*{1cm}
+{\large Generated by Doxygen 1.8.2}\\
+\vspace*{0.5cm}
+{\small Thu Sep 13 2012 23:26:45}\\
+\end{center}
+\end{titlepage}
+\pagenumbering{arabic}
+\hypersetup{pageanchor=true,citecolor=blue}
diff --git a/libopencm3/doc/lpc43xx/Doxyfile b/libopencm3/doc/lpc43xx/Doxyfile
new file mode 100644
index 0000000..fc6a311
--- /dev/null
+++ b/libopencm3/doc/lpc43xx/Doxyfile
@@ -0,0 +1,28 @@
+# HTML Documentation for LPC43xx code level
+
+# 14 September 2012
+# (C) Ken Sarkies
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_lpc43xx.log
+
+INPUT = ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/lpc43xx \
+ ../../lib/lpc43xx
+
+LAYOUT_FILE = DoxygenLayout_lpc43xx.xml
+
+GENERATE_TAGFILE = lpc43xx.tag
+
+ENABLE_PREPROCESSING = YES
+
+
diff --git a/libopencm3/doc/lpc43xx/Doxyfile_latex b/libopencm3/doc/lpc43xx/Doxyfile_latex
new file mode 100644
index 0000000..567ddc2
--- /dev/null
+++ b/libopencm3/doc/lpc43xx/Doxyfile_latex
@@ -0,0 +1,32 @@
+# LaTeX Documentation for LPC43xx code level
+
+# 14 September 2012
+# (C) Ken Sarkies
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_lpc43xx_latex.log
+
+INPUT = ../../include/libopencm3/docmain.dox \
+ ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/lpc43xx/ \
+ ../../lib/lpc43xx
+
+EXCLUDE = ../../include/libopencm3/lpc43xx/doc-lpc43xx.h
+
+LAYOUT_FILE = DoxygenLayout_lpc43xx.xml
+
+GENERATE_HTML = NO
+
+GENERATE_LATEX = YES
+
+LATEX_HEADER = header_lpc43xx.tex
+
diff --git a/libopencm3/doc/lpc43xx/DoxygenLayout_lpc43xx.xml b/libopencm3/doc/lpc43xx/DoxygenLayout_lpc43xx.xml
new file mode 100644
index 0000000..6f6ad5b
--- /dev/null
+++ b/libopencm3/doc/lpc43xx/DoxygenLayout_lpc43xx.xml
@@ -0,0 +1,205 @@
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diff --git a/libopencm3/doc/lpc43xx/header_lpc43xx.tex b/libopencm3/doc/lpc43xx/header_lpc43xx.tex
new file mode 100644
index 0000000..829e2e7
--- /dev/null
+++ b/libopencm3/doc/lpc43xx/header_lpc43xx.tex
@@ -0,0 +1,61 @@
+\documentclass{book}
+\usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry}
+\usepackage{makeidx}
+\usepackage{natbib}
+\usepackage{graphicx}
+\usepackage{multicol}
+\usepackage{float}
+\usepackage{listings}
+\usepackage{color}
+\usepackage{ifthen}
+\usepackage[table]{xcolor}
+\usepackage{textcomp}
+\usepackage{alltt}
+\usepackage{ifpdf}
+\ifpdf
+\usepackage[pdftex,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\else
+\usepackage[ps2pdf,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\usepackage{pspicture}
+\fi
+\usepackage[utf8]{inputenc}
+\usepackage{mathptmx}
+\usepackage[scaled=.90]{helvet}
+\usepackage{courier}
+\usepackage{sectsty}
+\usepackage{amssymb}
+\usepackage[titles]{tocloft}
+\usepackage{doxygen}
+\lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left }
+\makeindex
+\setcounter{tocdepth}{3}
+\renewcommand{\footrulewidth}{0.4pt}
+\renewcommand{\familydefault}{\sfdefault}
+\hfuzz=15pt
+\setlength{\emergencystretch}{15pt}
+\hbadness=750
+\tolerance=750
+\begin{document}
+\hypersetup{pageanchor=false,citecolor=blue}
+\begin{titlepage}
+\vspace*{7cm}
+\begin{center}
+{\Huge libopencm3: API Reference\\ NXP LPC43xx ARM Cortex M3 Series}\\
+\vspace*{1cm}
+{\large Generated by Doxygen 1.8.2}\\
+\vspace*{0.5cm}
+{\small Thu Sep 13 2012 23:26:45}\\
+\end{center}
+\end{titlepage}
+\pagenumbering{arabic}
+\hypersetup{pageanchor=true,citecolor=blue}
diff --git a/libopencm3/doc/sam3a/Doxyfile b/libopencm3/doc/sam3a/Doxyfile
new file mode 100644
index 0000000..4ec920c
--- /dev/null
+++ b/libopencm3/doc/sam3a/Doxyfile
@@ -0,0 +1,37 @@
+# HTML Documentation for SAM3A code level
+
+# 14 September 2012
+# (C) Ken Sarkies
+# 09 February 2014
+# (C) Felix Held
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_sam3a.log
+
+INPUT = ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/sam/3a \
+ ../../include/libopencm3/sam/common
+
+INPUT += ../../lib/sam/3a \
+ ../../lib/sam/common
+
+EXCLUDE =
+
+EXCLUDE_PATTERNS = *_common_3n3s.h
+
+LAYOUT_FILE = DoxygenLayout_sam3a.xml
+
+GENERATE_TAGFILE = sam3a.tag
+
+ENABLE_PREPROCESSING = YES
+
+
diff --git a/libopencm3/doc/sam3a/Doxyfile_latex b/libopencm3/doc/sam3a/Doxyfile_latex
new file mode 100644
index 0000000..c20eb73
--- /dev/null
+++ b/libopencm3/doc/sam3a/Doxyfile_latex
@@ -0,0 +1,39 @@
+# LaTeX Documentation for SAM3A code level
+
+# 14 September 2012
+# (C) Ken Sarkies
+# 09 February 2014
+# (C) Felix Held
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_sam3a_latex.log
+
+INPUT = ../../include/libopencm3/docmain.dox \
+ ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/sam/3a \
+ ../../include/libopencm3/sam/common
+
+INPUT += ../../lib/sam/3a \
+ ../../lib/sam/common
+
+EXCLUDE =
+
+EXCLUDE_PATTERNS = *_common_3n3s.h
+
+LAYOUT_FILE = DoxygenLayout_sam3a.xml
+
+GENERATE_HTML = NO
+
+GENERATE_LATEX = YES
+
+LATEX_HEADER = header_sam3a.tex
+
diff --git a/libopencm3/doc/sam3a/DoxygenLayout_sam3a.xml b/libopencm3/doc/sam3a/DoxygenLayout_sam3a.xml
new file mode 100644
index 0000000..d1d425b
--- /dev/null
+++ b/libopencm3/doc/sam3a/DoxygenLayout_sam3a.xml
@@ -0,0 +1,206 @@
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diff --git a/libopencm3/doc/sam3a/header_sam3a.tex b/libopencm3/doc/sam3a/header_sam3a.tex
new file mode 100644
index 0000000..89c4888
--- /dev/null
+++ b/libopencm3/doc/sam3a/header_sam3a.tex
@@ -0,0 +1,61 @@
+\documentclass{book}
+\usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry}
+\usepackage{makeidx}
+\usepackage{natbib}
+\usepackage{graphicx}
+\usepackage{multicol}
+\usepackage{float}
+\usepackage{listings}
+\usepackage{color}
+\usepackage{ifthen}
+\usepackage[table]{xcolor}
+\usepackage{textcomp}
+\usepackage{alltt}
+\usepackage{ifpdf}
+\ifpdf
+\usepackage[pdftex,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\else
+\usepackage[ps2pdf,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\usepackage{pspicture}
+\fi
+\usepackage[utf8]{inputenc}
+\usepackage{mathptmx}
+\usepackage[scaled=.90]{helvet}
+\usepackage{courier}
+\usepackage{sectsty}
+\usepackage{amssymb}
+\usepackage[titles]{tocloft}
+\usepackage{doxygen}
+\lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left }
+\makeindex
+\setcounter{tocdepth}{3}
+\renewcommand{\footrulewidth}{0.4pt}
+\renewcommand{\familydefault}{\sfdefault}
+\hfuzz=15pt
+\setlength{\emergencystretch}{15pt}
+\hbadness=750
+\tolerance=750
+\begin{document}
+\hypersetup{pageanchor=false,citecolor=blue}
+\begin{titlepage}
+\vspace*{7cm}
+\begin{center}
+{\Huge libopencm3: API Reference\\ Atmel SAM3A ARM Cortex M3 Series}\\
+\vspace*{1cm}
+{\large Generated by Doxygen 1.8.2}\\
+\vspace*{0.5cm}
+{\small Thu Sep 13 2012 23:26:45}\\
+\end{center}
+\end{titlepage}
+\pagenumbering{arabic}
+\hypersetup{pageanchor=true,citecolor=blue}
diff --git a/libopencm3/doc/sam3n/Doxyfile b/libopencm3/doc/sam3n/Doxyfile
new file mode 100644
index 0000000..c268821
--- /dev/null
+++ b/libopencm3/doc/sam3n/Doxyfile
@@ -0,0 +1,37 @@
+# HTML Documentation for SAM3N code level
+
+# 14 September 2012
+# (C) Ken Sarkies
+# 09 February 2014
+# (C) Felix Held
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_sam3n.log
+
+INPUT = ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/sam/3n \
+ ../../include/libopencm3/sam/common
+
+INPUT += ../../lib/sam/3n \
+ ../../lib/sam/common
+
+EXCLUDE =
+
+EXCLUDE_PATTERNS = *_common_3a3u3x.h
+
+LAYOUT_FILE = DoxygenLayout_sam3n.xml
+
+GENERATE_TAGFILE = sam3n.tag
+
+ENABLE_PREPROCESSING = YES
+
+
diff --git a/libopencm3/doc/sam3n/Doxyfile_latex b/libopencm3/doc/sam3n/Doxyfile_latex
new file mode 100644
index 0000000..9583bc5
--- /dev/null
+++ b/libopencm3/doc/sam3n/Doxyfile_latex
@@ -0,0 +1,39 @@
+# LaTeX Documentation for SAM3N code level
+
+# 14 September 2012
+# (C) Ken Sarkies
+# 09 February 2014
+# (C) Felix Held
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_sam3n_latex.log
+
+INPUT = ../../include/libopencm3/docmain.dox \
+ ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/sam/3n \
+ ../../include/libopencm3/sam/common
+
+INPUT += ../../lib/sam/3n \
+ ../../lib/sam/common
+
+EXCLUDE =
+
+EXCLUDE_PATTERNS = *_common_3a3u3x.h
+
+LAYOUT_FILE = DoxygenLayout_sam3n.xml
+
+GENERATE_HTML = NO
+
+GENERATE_LATEX = YES
+
+LATEX_HEADER = header_sam3n.tex
+
diff --git a/libopencm3/doc/sam3n/DoxygenLayout_sam3n.xml b/libopencm3/doc/sam3n/DoxygenLayout_sam3n.xml
new file mode 100644
index 0000000..d7a17b8
--- /dev/null
+++ b/libopencm3/doc/sam3n/DoxygenLayout_sam3n.xml
@@ -0,0 +1,206 @@
+
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diff --git a/libopencm3/doc/sam3n/header_sam3a.tex b/libopencm3/doc/sam3n/header_sam3a.tex
new file mode 100644
index 0000000..987ced7
--- /dev/null
+++ b/libopencm3/doc/sam3n/header_sam3a.tex
@@ -0,0 +1,61 @@
+\documentclass{book}
+\usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry}
+\usepackage{makeidx}
+\usepackage{natbib}
+\usepackage{graphicx}
+\usepackage{multicol}
+\usepackage{float}
+\usepackage{listings}
+\usepackage{color}
+\usepackage{ifthen}
+\usepackage[table]{xcolor}
+\usepackage{textcomp}
+\usepackage{alltt}
+\usepackage{ifpdf}
+\ifpdf
+\usepackage[pdftex,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\else
+\usepackage[ps2pdf,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\usepackage{pspicture}
+\fi
+\usepackage[utf8]{inputenc}
+\usepackage{mathptmx}
+\usepackage[scaled=.90]{helvet}
+\usepackage{courier}
+\usepackage{sectsty}
+\usepackage{amssymb}
+\usepackage[titles]{tocloft}
+\usepackage{doxygen}
+\lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left }
+\makeindex
+\setcounter{tocdepth}{3}
+\renewcommand{\footrulewidth}{0.4pt}
+\renewcommand{\familydefault}{\sfdefault}
+\hfuzz=15pt
+\setlength{\emergencystretch}{15pt}
+\hbadness=750
+\tolerance=750
+\begin{document}
+\hypersetup{pageanchor=false,citecolor=blue}
+\begin{titlepage}
+\vspace*{7cm}
+\begin{center}
+{\Huge libopencm3: API Reference\\ Atmel SAM3N ARM Cortex M3 Series}\\
+\vspace*{1cm}
+{\large Generated by Doxygen 1.8.2}\\
+\vspace*{0.5cm}
+{\small Thu Sep 13 2012 23:26:45}\\
+\end{center}
+\end{titlepage}
+\pagenumbering{arabic}
+\hypersetup{pageanchor=true,citecolor=blue}
diff --git a/libopencm3/doc/sam3s/Doxyfile b/libopencm3/doc/sam3s/Doxyfile
new file mode 100644
index 0000000..2c6a2eb
--- /dev/null
+++ b/libopencm3/doc/sam3s/Doxyfile
@@ -0,0 +1,37 @@
+# HTML Documentation for SAM3S code level
+
+# 14 September 2012
+# (C) Ken Sarkies
+# 09 February 2014
+# (C) Felix Held
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_sam3s.log
+
+INPUT = ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/sam/3s \
+ ../../include/libopencm3/sam/common
+
+INPUT += ../../lib/sam/3a \
+ ../../lib/sam/common
+
+EXCLUDE =
+
+EXCLUDE_PATTERNS = *_common_3a3u3x.h
+
+LAYOUT_FILE = DoxygenLayout_sam3s.xml
+
+GENERATE_TAGFILE = sam3s.tag
+
+ENABLE_PREPROCESSING = YES
+
+
diff --git a/libopencm3/doc/sam3s/Doxyfile_latex b/libopencm3/doc/sam3s/Doxyfile_latex
new file mode 100644
index 0000000..648f7a8
--- /dev/null
+++ b/libopencm3/doc/sam3s/Doxyfile_latex
@@ -0,0 +1,39 @@
+# LaTeX Documentation for SAM3S code level
+
+# 14 September 2012
+# (C) Ken Sarkies
+# 09 February 2014
+# (C) Felix Held
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_sam3s_latex.log
+
+INPUT = ../../include/libopencm3/docmain.dox \
+ ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/sam/3s \
+ ../../include/libopencm3/sam/common
+
+INPUT += ../../lib/sam/3s \
+ ../../lib/sam/common
+
+EXCLUDE =
+
+EXCLUDE_PATTERNS = *_common_3a3u3x.h
+
+LAYOUT_FILE = DoxygenLayout_sam3s.xml
+
+GENERATE_HTML = NO
+
+GENERATE_LATEX = YES
+
+LATEX_HEADER = header_sam3s.tex
+
diff --git a/libopencm3/doc/sam3s/DoxygenLayout_sam3s.xml b/libopencm3/doc/sam3s/DoxygenLayout_sam3s.xml
new file mode 100644
index 0000000..83e4a36
--- /dev/null
+++ b/libopencm3/doc/sam3s/DoxygenLayout_sam3s.xml
@@ -0,0 +1,206 @@
+
+
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diff --git a/libopencm3/doc/sam3s/header_sam3a.tex b/libopencm3/doc/sam3s/header_sam3a.tex
new file mode 100644
index 0000000..61e24c1
--- /dev/null
+++ b/libopencm3/doc/sam3s/header_sam3a.tex
@@ -0,0 +1,61 @@
+\documentclass{book}
+\usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry}
+\usepackage{makeidx}
+\usepackage{natbib}
+\usepackage{graphicx}
+\usepackage{multicol}
+\usepackage{float}
+\usepackage{listings}
+\usepackage{color}
+\usepackage{ifthen}
+\usepackage[table]{xcolor}
+\usepackage{textcomp}
+\usepackage{alltt}
+\usepackage{ifpdf}
+\ifpdf
+\usepackage[pdftex,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\else
+\usepackage[ps2pdf,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\usepackage{pspicture}
+\fi
+\usepackage[utf8]{inputenc}
+\usepackage{mathptmx}
+\usepackage[scaled=.90]{helvet}
+\usepackage{courier}
+\usepackage{sectsty}
+\usepackage{amssymb}
+\usepackage[titles]{tocloft}
+\usepackage{doxygen}
+\lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left }
+\makeindex
+\setcounter{tocdepth}{3}
+\renewcommand{\footrulewidth}{0.4pt}
+\renewcommand{\familydefault}{\sfdefault}
+\hfuzz=15pt
+\setlength{\emergencystretch}{15pt}
+\hbadness=750
+\tolerance=750
+\begin{document}
+\hypersetup{pageanchor=false,citecolor=blue}
+\begin{titlepage}
+\vspace*{7cm}
+\begin{center}
+{\Huge libopencm3: API Reference\\ Atmel SAM3S ARM Cortex M3 Series}\\
+\vspace*{1cm}
+{\large Generated by Doxygen 1.8.2}\\
+\vspace*{0.5cm}
+{\small Thu Sep 13 2012 23:26:45}\\
+\end{center}
+\end{titlepage}
+\pagenumbering{arabic}
+\hypersetup{pageanchor=true,citecolor=blue}
diff --git a/libopencm3/doc/sam3u/Doxyfile b/libopencm3/doc/sam3u/Doxyfile
new file mode 100644
index 0000000..72fddf4
--- /dev/null
+++ b/libopencm3/doc/sam3u/Doxyfile
@@ -0,0 +1,37 @@
+# HTML Documentation for SAM3U code level
+
+# 14 September 2012
+# (C) Ken Sarkies
+# 09 February 2014
+# (C) Felix Held
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_sam3u.log
+
+INPUT = ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/sam/3u \
+ ../../include/libopencm3/sam/common
+
+INPUT += ../../lib/sam/3u \
+ ../../lib/sam/common
+
+EXCLUDE =
+
+EXCLUDE_PATTERNS = *_common_3n3s.h
+
+LAYOUT_FILE = DoxygenLayout_sam3u.xml
+
+GENERATE_TAGFILE = sam3u.tag
+
+ENABLE_PREPROCESSING = YES
+
+
diff --git a/libopencm3/doc/sam3u/Doxyfile_latex b/libopencm3/doc/sam3u/Doxyfile_latex
new file mode 100644
index 0000000..d732d6e
--- /dev/null
+++ b/libopencm3/doc/sam3u/Doxyfile_latex
@@ -0,0 +1,39 @@
+# LaTeX Documentation for SAM3U code level
+
+# 14 September 2012
+# (C) Ken Sarkies
+# 09 February 2014
+# (C) Felix Held
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_sam3u_latex.log
+
+INPUT = ../../include/libopencm3/docmain.dox \
+ ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/sam/3u \
+ ../../include/libopencm3/sam/common
+
+INPUT += ../../lib/sam/3u \
+ ../../lib/sam/common
+
+EXCLUDE =
+
+EXCLUDE_PATTERNS = *_common_3n3s.h
+
+LAYOUT_FILE = DoxygenLayout_sam3u.xml
+
+GENERATE_HTML = NO
+
+GENERATE_LATEX = YES
+
+LATEX_HEADER = header_sam3u.tex
+
diff --git a/libopencm3/doc/sam3u/DoxygenLayout_sam3u.xml b/libopencm3/doc/sam3u/DoxygenLayout_sam3u.xml
new file mode 100644
index 0000000..f39f0de
--- /dev/null
+++ b/libopencm3/doc/sam3u/DoxygenLayout_sam3u.xml
@@ -0,0 +1,206 @@
+
+
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diff --git a/libopencm3/doc/sam3u/header_sam3a.tex b/libopencm3/doc/sam3u/header_sam3a.tex
new file mode 100644
index 0000000..79668b1
--- /dev/null
+++ b/libopencm3/doc/sam3u/header_sam3a.tex
@@ -0,0 +1,61 @@
+\documentclass{book}
+\usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry}
+\usepackage{makeidx}
+\usepackage{natbib}
+\usepackage{graphicx}
+\usepackage{multicol}
+\usepackage{float}
+\usepackage{listings}
+\usepackage{color}
+\usepackage{ifthen}
+\usepackage[table]{xcolor}
+\usepackage{textcomp}
+\usepackage{alltt}
+\usepackage{ifpdf}
+\ifpdf
+\usepackage[pdftex,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\else
+\usepackage[ps2pdf,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\usepackage{pspicture}
+\fi
+\usepackage[utf8]{inputenc}
+\usepackage{mathptmx}
+\usepackage[scaled=.90]{helvet}
+\usepackage{courier}
+\usepackage{sectsty}
+\usepackage{amssymb}
+\usepackage[titles]{tocloft}
+\usepackage{doxygen}
+\lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left }
+\makeindex
+\setcounter{tocdepth}{3}
+\renewcommand{\footrulewidth}{0.4pt}
+\renewcommand{\familydefault}{\sfdefault}
+\hfuzz=15pt
+\setlength{\emergencystretch}{15pt}
+\hbadness=750
+\tolerance=750
+\begin{document}
+\hypersetup{pageanchor=false,citecolor=blue}
+\begin{titlepage}
+\vspace*{7cm}
+\begin{center}
+{\Huge libopencm3: API Reference\\ Atmel SAM3U ARM Cortex M3 Series}\\
+\vspace*{1cm}
+{\large Generated by Doxygen 1.8.2}\\
+\vspace*{0.5cm}
+{\small Thu Sep 13 2012 23:26:45}\\
+\end{center}
+\end{titlepage}
+\pagenumbering{arabic}
+\hypersetup{pageanchor=true,citecolor=blue}
diff --git a/libopencm3/doc/sam3x/Doxyfile b/libopencm3/doc/sam3x/Doxyfile
new file mode 100644
index 0000000..ce5e62a
--- /dev/null
+++ b/libopencm3/doc/sam3x/Doxyfile
@@ -0,0 +1,37 @@
+# HTML Documentation for SAM3X code level
+
+# 14 September 2012
+# (C) Ken Sarkies
+# 09 February 2014
+# (C) Felix Held
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_sam3x.log
+
+INPUT = ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/sam/3x \
+ ../../include/libopencm3/sam/common
+
+INPUT += ../../lib/sam/3x \
+ ../../lib/sam/common
+
+EXCLUDE =
+
+EXCLUDE_PATTERNS = *_common_3n3s.h
+
+LAYOUT_FILE = DoxygenLayout_sam3x.xml
+
+GENERATE_TAGFILE = sam3x.tag
+
+ENABLE_PREPROCESSING = YES
+
+
diff --git a/libopencm3/doc/sam3x/Doxyfile_latex b/libopencm3/doc/sam3x/Doxyfile_latex
new file mode 100644
index 0000000..11e0105
--- /dev/null
+++ b/libopencm3/doc/sam3x/Doxyfile_latex
@@ -0,0 +1,39 @@
+# LaTeX Documentation for SAM3X code level
+
+# 14 September 2012
+# (C) Ken Sarkies
+# 09 February 2014
+# (C) Felix Held
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_sam3x_latex.log
+
+INPUT = ../../include/libopencm3/docmain.dox \
+ ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/sam/3x \
+ ../../include/libopencm3/sam/common
+
+INPUT += ../../lib/sam/3x \
+ ../../lib/sam/common
+
+EXCLUDE =
+
+EXCLUDE_PATTERNS = *_common_3n3s.h
+
+LAYOUT_FILE = DoxygenLayout_sam3x.xml
+
+GENERATE_HTML = NO
+
+GENERATE_LATEX = YES
+
+LATEX_HEADER = header_sam3x.tex
+
diff --git a/libopencm3/doc/sam3x/DoxygenLayout_sam3x.xml b/libopencm3/doc/sam3x/DoxygenLayout_sam3x.xml
new file mode 100644
index 0000000..717d3c1
--- /dev/null
+++ b/libopencm3/doc/sam3x/DoxygenLayout_sam3x.xml
@@ -0,0 +1,206 @@
+
+
+
+
+
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diff --git a/libopencm3/doc/sam3x/header_sam3a.tex b/libopencm3/doc/sam3x/header_sam3a.tex
new file mode 100644
index 0000000..b3c7e4e
--- /dev/null
+++ b/libopencm3/doc/sam3x/header_sam3a.tex
@@ -0,0 +1,61 @@
+\documentclass{book}
+\usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry}
+\usepackage{makeidx}
+\usepackage{natbib}
+\usepackage{graphicx}
+\usepackage{multicol}
+\usepackage{float}
+\usepackage{listings}
+\usepackage{color}
+\usepackage{ifthen}
+\usepackage[table]{xcolor}
+\usepackage{textcomp}
+\usepackage{alltt}
+\usepackage{ifpdf}
+\ifpdf
+\usepackage[pdftex,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\else
+\usepackage[ps2pdf,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\usepackage{pspicture}
+\fi
+\usepackage[utf8]{inputenc}
+\usepackage{mathptmx}
+\usepackage[scaled=.90]{helvet}
+\usepackage{courier}
+\usepackage{sectsty}
+\usepackage{amssymb}
+\usepackage[titles]{tocloft}
+\usepackage{doxygen}
+\lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left }
+\makeindex
+\setcounter{tocdepth}{3}
+\renewcommand{\footrulewidth}{0.4pt}
+\renewcommand{\familydefault}{\sfdefault}
+\hfuzz=15pt
+\setlength{\emergencystretch}{15pt}
+\hbadness=750
+\tolerance=750
+\begin{document}
+\hypersetup{pageanchor=false,citecolor=blue}
+\begin{titlepage}
+\vspace*{7cm}
+\begin{center}
+{\Huge libopencm3: API Reference\\ Atmel SAM3X ARM Cortex M3 Series}\\
+\vspace*{1cm}
+{\large Generated by Doxygen 1.8.2}\\
+\vspace*{0.5cm}
+{\small Thu Sep 13 2012 23:26:45}\\
+\end{center}
+\end{titlepage}
+\pagenumbering{arabic}
+\hypersetup{pageanchor=true,citecolor=blue}
diff --git a/libopencm3/doc/stm32f0/Doxyfile b/libopencm3/doc/stm32f0/Doxyfile
new file mode 100644
index 0000000..725499d
--- /dev/null
+++ b/libopencm3/doc/stm32f0/Doxyfile
@@ -0,0 +1,38 @@
+# HTML Documentation for STM32F1 code level
+
+# 14 September 2012
+# (C) Ken Sarkies
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_stm32f0.log
+
+INPUT = ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/stm32/f0 \
+ ../../include/libopencm3/stm32/common
+
+INPUT += ../../lib/stm32/f0 \
+ ../../lib/stm32/common
+
+EXCLUDE = ../../include/libopencm3/stm32/f0/usb.h \
+ ../../include/libopencm3/stm32/f0/usb_desc.h
+
+EXCLUDE_PATTERNS = *_common_*f24.h *_common_*f24.c \
+ *_common_*f234.h *_common_*f234.c \
+ *_common_*f124.h *_common_*f124.c
+
+LAYOUT_FILE = DoxygenLayout_stm32f0.xml
+
+GENERATE_TAGFILE = stm32f0.tag
+
+ENABLE_PREPROCESSING = YES
+
+
diff --git a/libopencm3/doc/stm32f0/Doxyfile_latex b/libopencm3/doc/stm32f0/Doxyfile_latex
new file mode 100644
index 0000000..f62818d
--- /dev/null
+++ b/libopencm3/doc/stm32f0/Doxyfile_latex
@@ -0,0 +1,40 @@
+# LaTeX Documentation for STM32F1 code level
+
+# 14 September 2012
+# (C) Ken Sarkies
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_stm32f0_latex.log
+
+INPUT = ../../include/libopencm3/docmain.dox \
+ ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/stm32/f0 \
+ ../../include/libopencm3/stm32/common
+
+INPUT += ../../lib/stm32/f0 \
+ ../../lib/stm32/common
+
+EXCLUDE = ../../include/libopencm3/stm32/f0/doc-stm32f0.h \
+ ../../include/libopencm3/stm32/f0/usb.h \
+ ../../include/libopencm3/stm32/f0/usb_desc.h \
+ ../../include/libopencm3/stm32/f0/nvic_f0.h
+
+EXCLUDE_PATTERNS = *_common_f24.h *_common_f24.c
+
+LAYOUT_FILE = DoxygenLayout_stm32f0.xml
+
+GENERATE_HTML = NO
+
+GENERATE_LATEX = YES
+
+LATEX_HEADER = header_stm32f0.tex
+
diff --git a/libopencm3/doc/stm32f0/DoxygenLayout_stm32f0.xml b/libopencm3/doc/stm32f0/DoxygenLayout_stm32f0.xml
new file mode 100644
index 0000000..07b09bc
--- /dev/null
+++ b/libopencm3/doc/stm32f0/DoxygenLayout_stm32f0.xml
@@ -0,0 +1,206 @@
+
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diff --git a/libopencm3/doc/stm32f0/header_stm32f0.tex b/libopencm3/doc/stm32f0/header_stm32f0.tex
new file mode 100644
index 0000000..6de861d
--- /dev/null
+++ b/libopencm3/doc/stm32f0/header_stm32f0.tex
@@ -0,0 +1,61 @@
+\documentclass{book}
+\usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry}
+\usepackage{makeidx}
+\usepackage{natbib}
+\usepackage{graphicx}
+\usepackage{multicol}
+\usepackage{float}
+\usepackage{listings}
+\usepackage{color}
+\usepackage{ifthen}
+\usepackage[table]{xcolor}
+\usepackage{textcomp}
+\usepackage{alltt}
+\usepackage{ifpdf}
+\ifpdf
+\usepackage[pdftex,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\else
+\usepackage[ps2pdf,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\usepackage{pspicture}
+\fi
+\usepackage[utf8]{inputenc}
+\usepackage{mathptmx}
+\usepackage[scaled=.90]{helvet}
+\usepackage{courier}
+\usepackage{sectsty}
+\usepackage{amssymb}
+\usepackage[titles]{tocloft}
+\usepackage{doxygen}
+\lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left }
+\makeindex
+\setcounter{tocdepth}{3}
+\renewcommand{\footrulewidth}{0.4pt}
+\renewcommand{\familydefault}{\sfdefault}
+\hfuzz=15pt
+\setlength{\emergencystretch}{15pt}
+\hbadness=750
+\tolerance=750
+\begin{document}
+\hypersetup{pageanchor=false,citecolor=blue}
+\begin{titlepage}
+\vspace*{7cm}
+\begin{center}
+{\Huge libopencm3: API Reference\\ STM STM32F0 ARM Cortex M0 Series}\\
+\vspace*{1cm}
+{\large Generated by Doxygen 1.8.2}\\
+\vspace*{0.5cm}
+{\small Thu Sep 13 2012 23:26:45}\\
+\end{center}
+\end{titlepage}
+\pagenumbering{arabic}
+\hypersetup{pageanchor=true,citecolor=blue}
diff --git a/libopencm3/doc/stm32f0/index.html b/libopencm3/doc/stm32f0/index.html
new file mode 100644
index 0000000..7715877
--- /dev/null
+++ b/libopencm3/doc/stm32f0/index.html
@@ -0,0 +1,8 @@
+
+
+
+
+
+ Documentation index
+
+
diff --git a/libopencm3/doc/stm32f1/Doxyfile b/libopencm3/doc/stm32f1/Doxyfile
new file mode 100644
index 0000000..6a816af
--- /dev/null
+++ b/libopencm3/doc/stm32f1/Doxyfile
@@ -0,0 +1,39 @@
+# HTML Documentation for STM32F1 code level
+
+# 14 September 2012
+# (C) Ken Sarkies
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_stm32f1.log
+
+INPUT = ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/stm32/f1 \
+ ../../include/libopencm3/stm32/common
+
+INPUT += ../../lib/stm32/f1 \
+ ../../lib/stm32/common
+
+EXCLUDE = ../../include/libopencm3/stm32/f1/usb.h \
+ ../../include/libopencm3/stm32/f1/usb_desc.h
+
+EXCLUDE_PATTERNS = *_common_*f24.h *_common_*f24.c \
+ *_common_*f234.h *_common_*f234.c \
+ *_common_*f024.h *_common_*f024.c \
+ *_common_*f03.h *_common_*f03.c
+
+LAYOUT_FILE = DoxygenLayout_stm32f1.xml
+
+GENERATE_TAGFILE = stm32f1.tag
+
+ENABLE_PREPROCESSING = YES
+
+
diff --git a/libopencm3/doc/stm32f1/Doxyfile_latex b/libopencm3/doc/stm32f1/Doxyfile_latex
new file mode 100644
index 0000000..97c32e7
--- /dev/null
+++ b/libopencm3/doc/stm32f1/Doxyfile_latex
@@ -0,0 +1,40 @@
+# LaTeX Documentation for STM32F1 code level
+
+# 14 September 2012
+# (C) Ken Sarkies
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_stm32f1_latex.log
+
+INPUT = ../../include/libopencm3/docmain.dox \
+ ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/stm32/f1 \
+ ../../include/libopencm3/stm32/common
+
+INPUT += ../../lib/stm32/f1 \
+ ../../lib/stm32/common
+
+EXCLUDE = ../../include/libopencm3/stm32/f1/doc-stm32f1.h \
+ ../../include/libopencm3/stm32/f1/usb.h \
+ ../../include/libopencm3/stm32/f1/usb_desc.h \
+ ../../include/libopencm3/stm32/f1/nvic_f1.h
+
+EXCLUDE_PATTERNS = *_common_f24.h *_common_f24.c
+
+LAYOUT_FILE = DoxygenLayout_stm32f1.xml
+
+GENERATE_HTML = NO
+
+GENERATE_LATEX = YES
+
+LATEX_HEADER = header_stm32f1.tex
+
diff --git a/libopencm3/doc/stm32f1/DoxygenLayout_stm32f1.xml b/libopencm3/doc/stm32f1/DoxygenLayout_stm32f1.xml
new file mode 100644
index 0000000..9d5fea7
--- /dev/null
+++ b/libopencm3/doc/stm32f1/DoxygenLayout_stm32f1.xml
@@ -0,0 +1,206 @@
+
+
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diff --git a/libopencm3/doc/stm32f1/header_stm32f1.tex b/libopencm3/doc/stm32f1/header_stm32f1.tex
new file mode 100644
index 0000000..19fb8db
--- /dev/null
+++ b/libopencm3/doc/stm32f1/header_stm32f1.tex
@@ -0,0 +1,61 @@
+\documentclass{book}
+\usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry}
+\usepackage{makeidx}
+\usepackage{natbib}
+\usepackage{graphicx}
+\usepackage{multicol}
+\usepackage{float}
+\usepackage{listings}
+\usepackage{color}
+\usepackage{ifthen}
+\usepackage[table]{xcolor}
+\usepackage{textcomp}
+\usepackage{alltt}
+\usepackage{ifpdf}
+\ifpdf
+\usepackage[pdftex,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\else
+\usepackage[ps2pdf,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\usepackage{pspicture}
+\fi
+\usepackage[utf8]{inputenc}
+\usepackage{mathptmx}
+\usepackage[scaled=.90]{helvet}
+\usepackage{courier}
+\usepackage{sectsty}
+\usepackage{amssymb}
+\usepackage[titles]{tocloft}
+\usepackage{doxygen}
+\lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left }
+\makeindex
+\setcounter{tocdepth}{3}
+\renewcommand{\footrulewidth}{0.4pt}
+\renewcommand{\familydefault}{\sfdefault}
+\hfuzz=15pt
+\setlength{\emergencystretch}{15pt}
+\hbadness=750
+\tolerance=750
+\begin{document}
+\hypersetup{pageanchor=false,citecolor=blue}
+\begin{titlepage}
+\vspace*{7cm}
+\begin{center}
+{\Huge libopencm3: API Reference\\ STM STM32F1 ARM Cortex M3 Series}\\
+\vspace*{1cm}
+{\large Generated by Doxygen 1.8.2}\\
+\vspace*{0.5cm}
+{\small Thu Sep 13 2012 23:26:45}\\
+\end{center}
+\end{titlepage}
+\pagenumbering{arabic}
+\hypersetup{pageanchor=true,citecolor=blue}
diff --git a/libopencm3/doc/stm32f1/index.html b/libopencm3/doc/stm32f1/index.html
new file mode 100644
index 0000000..7715877
--- /dev/null
+++ b/libopencm3/doc/stm32f1/index.html
@@ -0,0 +1,8 @@
+
+
+
+
+
+ Documentation index
+
+
diff --git a/libopencm3/doc/stm32f2/Doxyfile b/libopencm3/doc/stm32f2/Doxyfile
new file mode 100644
index 0000000..5c35763
--- /dev/null
+++ b/libopencm3/doc/stm32f2/Doxyfile
@@ -0,0 +1,38 @@
+# HTML Documentation for STM32F2 code level
+
+# 14 September 2012
+# (C) Ken Sarkies
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_stm32f2.log
+
+INPUT = ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/stm32/f2 \
+ ../../include/libopencm3/stm32/common
+
+INPUT += ../../lib/stm32/f2 \
+ ../../lib/stm32/common
+
+EXCLUDE =
+
+EXCLUDE_PATTERNS = *_common_f13.h *_common_f13.c \
+ *_common_*f013.h *_common_*f013.c \
+ *_common_*f01.h *_common_*f01.c \
+ *_common_*f03.h *_common_*f03.c
+
+LAYOUT_FILE = DoxygenLayout_stm32f2.xml
+
+GENERATE_TAGFILE = stm32f2.tag
+
+ENABLE_PREPROCESSING = YES
+
+
diff --git a/libopencm3/doc/stm32f2/Doxyfile_latex b/libopencm3/doc/stm32f2/Doxyfile_latex
new file mode 100644
index 0000000..dad6848
--- /dev/null
+++ b/libopencm3/doc/stm32f2/Doxyfile_latex
@@ -0,0 +1,37 @@
+# LaTeX Documentation for STM32F2 code level
+
+# 14 September 2012
+# (C) Ken Sarkies
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_stm32f2_latex.log
+
+INPUT = ../../include/libopencm3/docmain.dox \
+ ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/stm32/f2 \
+ ../../include/libopencm3/stm32/common
+
+INPUT += ../../lib/stm32/f2 \
+ ../../lib/stm32/common
+
+EXCLUDE = ../../include/libopencm3/stm32/f2/doc-stm32f2.h
+
+EXCLUDE_PATTERNS =
+
+LAYOUT_FILE = DoxygenLayout_stm32f2.xml
+
+GENERATE_HTML = NO
+
+GENERATE_LATEX = YES
+
+LATEX_HEADER = header_stm32f2.tex
+
diff --git a/libopencm3/doc/stm32f2/DoxygenLayout_stm32f2.xml b/libopencm3/doc/stm32f2/DoxygenLayout_stm32f2.xml
new file mode 100644
index 0000000..cd23ccd
--- /dev/null
+++ b/libopencm3/doc/stm32f2/DoxygenLayout_stm32f2.xml
@@ -0,0 +1,206 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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diff --git a/libopencm3/doc/stm32f2/header_stm32f2.tex b/libopencm3/doc/stm32f2/header_stm32f2.tex
new file mode 100644
index 0000000..d65c4f0
--- /dev/null
+++ b/libopencm3/doc/stm32f2/header_stm32f2.tex
@@ -0,0 +1,61 @@
+\documentclass{book}
+\usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry}
+\usepackage{makeidx}
+\usepackage{natbib}
+\usepackage{graphicx}
+\usepackage{multicol}
+\usepackage{float}
+\usepackage{listings}
+\usepackage{color}
+\usepackage{ifthen}
+\usepackage[table]{xcolor}
+\usepackage{textcomp}
+\usepackage{alltt}
+\usepackage{ifpdf}
+\ifpdf
+\usepackage[pdftex,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\else
+\usepackage[ps2pdf,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\usepackage{pspicture}
+\fi
+\usepackage[utf8]{inputenc}
+\usepackage{mathptmx}
+\usepackage[scaled=.90]{helvet}
+\usepackage{courier}
+\usepackage{sectsty}
+\usepackage{amssymb}
+\usepackage[titles]{tocloft}
+\usepackage{doxygen}
+\lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left }
+\makeindex
+\setcounter{tocdepth}{3}
+\renewcommand{\footrulewidth}{0.4pt}
+\renewcommand{\familydefault}{\sfdefault}
+\hfuzz=15pt
+\setlength{\emergencystretch}{15pt}
+\hbadness=750
+\tolerance=750
+\begin{document}
+\hypersetup{pageanchor=false,citecolor=blue}
+\begin{titlepage}
+\vspace*{7cm}
+\begin{center}
+{\Huge libopencm3: API Reference\\ STM STM32F2 ARM Cortex M3 Series}\\
+\vspace*{1cm}
+{\large Generated by Doxygen 1.8.2}\\
+\vspace*{0.5cm}
+{\small Thu Sep 13 2012 23:26:45}\\
+\end{center}
+\end{titlepage}
+\pagenumbering{arabic}
+\hypersetup{pageanchor=true,citecolor=blue}
diff --git a/libopencm3/doc/stm32f2/index.html b/libopencm3/doc/stm32f2/index.html
new file mode 100644
index 0000000..7715877
--- /dev/null
+++ b/libopencm3/doc/stm32f2/index.html
@@ -0,0 +1,8 @@
+
+
+
+
+
+ Documentation index
+
+
diff --git a/libopencm3/doc/stm32f3/Doxyfile b/libopencm3/doc/stm32f3/Doxyfile
new file mode 100644
index 0000000..0bc511c
--- /dev/null
+++ b/libopencm3/doc/stm32f3/Doxyfile
@@ -0,0 +1,33 @@
+# HTML Documentation for STM32F3 code level
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_stm32f3.log
+
+INPUT = ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/stm32/f3 \
+ ../../include/libopencm3/stm32/common
+
+INPUT += ../../lib/stm32/f3 \
+ ../../lib/stm32/common
+
+EXCLUDE = ../../include/libopencm3/stm32/f3/usb.h \
+ ../../include/libopencm3/stm32/f3/usb_desc.h
+
+EXCLUDE_PATTERNS = *_common_*f*24.h *_common_*f*24.c \
+ *_common_*f01.h *_common_*f01.c \
+ *_common_bcd.h *_common_bcd.c
+
+LAYOUT_FILE = DoxygenLayout_stm32f3.xml
+
+GENERATE_TAGFILE = stm32f3.tag
+
+ENABLE_PREPROCESSING = YES
diff --git a/libopencm3/doc/stm32f3/Doxyfile_latex b/libopencm3/doc/stm32f3/Doxyfile_latex
new file mode 100644
index 0000000..a9dc0f6
--- /dev/null
+++ b/libopencm3/doc/stm32f3/Doxyfile_latex
@@ -0,0 +1,40 @@
+# LaTeX Documentation for STM32F3 code level
+
+# 14 September 2012
+# (C) Ken Sarkies
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_stm32f3_latex.log
+
+INPUT = ../../include/libopencm3/docmain.dox \
+ ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/stm32/f3 \
+ ../../include/libopencm3/stm32/common
+
+INPUT += ../../lib/stm32/f3 \
+ ../../lib/stm32/common
+
+EXCLUDE = ../../include/libopencm3/stm32/f3/doc-stm32f3.h \
+ ../../include/libopencm3/stm32/f3/usb.h \
+ ../../include/libopencm3/stm32/f3/usb_desc.h \
+ ../../include/libopencm3/stm32/f3/nvic_f3.h
+
+EXCLUDE_PATTERNS = *_common_f24.h *_common_f24.c
+
+LAYOUT_FILE = DoxygenLayout_stm32f1.xml
+
+GENERATE_HTML = NO
+
+GENERATE_LATEX = YES
+
+LATEX_HEADER = header_stm32f3.tex
+
diff --git a/libopencm3/doc/stm32f3/DoxygenLayout_stm32f3.xml b/libopencm3/doc/stm32f3/DoxygenLayout_stm32f3.xml
new file mode 100644
index 0000000..107a9c4
--- /dev/null
+++ b/libopencm3/doc/stm32f3/DoxygenLayout_stm32f3.xml
@@ -0,0 +1,206 @@
+
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diff --git a/libopencm3/doc/stm32f3/header_stm32f3.tex b/libopencm3/doc/stm32f3/header_stm32f3.tex
new file mode 100644
index 0000000..0755c0a
--- /dev/null
+++ b/libopencm3/doc/stm32f3/header_stm32f3.tex
@@ -0,0 +1,61 @@
+\documentclass{book}
+\usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry}
+\usepackage{makeidx}
+\usepackage{natbib}
+\usepackage{graphicx}
+\usepackage{multicol}
+\usepackage{float}
+\usepackage{listings}
+\usepackage{color}
+\usepackage{ifthen}
+\usepackage[table]{xcolor}
+\usepackage{textcomp}
+\usepackage{alltt}
+\usepackage{ifpdf}
+\ifpdf
+\usepackage[pdftex,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\else
+\usepackage[ps2pdf,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\usepackage{pspicture}
+\fi
+\usepackage[utf8]{inputenc}
+\usepackage{mathptmx}
+\usepackage[scaled=.90]{helvet}
+\usepackage{courier}
+\usepackage{sectsty}
+\usepackage{amssymb}
+\usepackage[titles]{tocloft}
+\usepackage{doxygen}
+\lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left }
+\makeindex
+\setcounter{tocdepth}{3}
+\renewcommand{\footrulewidth}{0.4pt}
+\renewcommand{\familydefault}{\sfdefault}
+\hfuzz=15pt
+\setlength{\emergencystretch}{15pt}
+\hbadness=750
+\tolerance=750
+\begin{document}
+\hypersetup{pageanchor=false,citecolor=blue}
+\begin{titlepage}
+\vspace*{7cm}
+\begin{center}
+{\Huge libopencm3: API Reference\\ STM STM32F3 ARM Cortex M3 Series}\\
+\vspace*{1cm}
+{\large Generated by Doxygen 1.8.2}\\
+\vspace*{0.5cm}
+{\small Thu Sep 13 2012 23:26:45}\\
+\end{center}
+\end{titlepage}
+\pagenumbering{arabic}
+\hypersetup{pageanchor=true,citecolor=blue}
diff --git a/libopencm3/doc/stm32f3/index.html b/libopencm3/doc/stm32f3/index.html
new file mode 100644
index 0000000..7715877
--- /dev/null
+++ b/libopencm3/doc/stm32f3/index.html
@@ -0,0 +1,8 @@
+
+
+
+
+
+ Documentation index
+
+
diff --git a/libopencm3/doc/stm32f4/Doxyfile b/libopencm3/doc/stm32f4/Doxyfile
new file mode 100644
index 0000000..11bcb38
--- /dev/null
+++ b/libopencm3/doc/stm32f4/Doxyfile
@@ -0,0 +1,38 @@
+# HTML Documentation for STM32F4 code level
+
+# 14 September 2012
+# (C) Ken Sarkies
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_stm32f4.log
+
+INPUT = ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/stm32/f4 \
+ ../../include/libopencm3/stm32/common
+
+INPUT += ../../lib/stm32/f4 \
+ ../../lib/stm32/common
+
+EXCLUDE =
+
+EXCLUDE_PATTERNS = *_common_f*3.h *_common_f*3.c \
+ *_common_*f013.h *_common_*f013.c \
+ *_common_*f01.h *_common_*f01.c \ \
+ *_common_*f03.h *_common_*f03.c
+
+LAYOUT_FILE = DoxygenLayout_stm32f4.xml
+
+GENERATE_TAGFILE = stm32f4.tag
+
+ENABLE_PREPROCESSING = YES
+
+
diff --git a/libopencm3/doc/stm32f4/Doxyfile_latex b/libopencm3/doc/stm32f4/Doxyfile_latex
new file mode 100644
index 0000000..e93248c
--- /dev/null
+++ b/libopencm3/doc/stm32f4/Doxyfile_latex
@@ -0,0 +1,37 @@
+# LaTeX Documentation for STM32F4 code level
+
+# 14 September 2012
+# (C) Ken Sarkies
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_stm32f4_latex.log
+
+INPUT = ../../include/libopencm3/docmain.dox \
+ ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/stm32/f4 \
+ ../../include/libopencm3/stm32/common
+
+INPUT += ../../lib/stm32/f4 \
+ ../../lib/stm32/common
+
+EXCLUDE = ../../include/libopencm3/stm32/f4/doc-stm32f4.h
+
+EXCLUDE_PATTERNS =
+
+LAYOUT_FILE = DoxygenLayout_stm32f4.xml
+
+GENERATE_HTML = NO
+
+GENERATE_LATEX = YES
+
+LATEX_HEADER = header_stm32f4.tex
+
diff --git a/libopencm3/doc/stm32f4/DoxygenLayout_stm32f4.xml b/libopencm3/doc/stm32f4/DoxygenLayout_stm32f4.xml
new file mode 100644
index 0000000..58f014f
--- /dev/null
+++ b/libopencm3/doc/stm32f4/DoxygenLayout_stm32f4.xml
@@ -0,0 +1,206 @@
+
+
+
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diff --git a/libopencm3/doc/stm32f4/header_stm32f4.tex b/libopencm3/doc/stm32f4/header_stm32f4.tex
new file mode 100644
index 0000000..97cc35f
--- /dev/null
+++ b/libopencm3/doc/stm32f4/header_stm32f4.tex
@@ -0,0 +1,61 @@
+\documentclass{book}
+\usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry}
+\usepackage{makeidx}
+\usepackage{natbib}
+\usepackage{graphicx}
+\usepackage{multicol}
+\usepackage{float}
+\usepackage{listings}
+\usepackage{color}
+\usepackage{ifthen}
+\usepackage[table]{xcolor}
+\usepackage{textcomp}
+\usepackage{alltt}
+\usepackage{ifpdf}
+\ifpdf
+\usepackage[pdftex,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\else
+\usepackage[ps2pdf,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\usepackage{pspicture}
+\fi
+\usepackage[utf8]{inputenc}
+\usepackage{mathptmx}
+\usepackage[scaled=.90]{helvet}
+\usepackage{courier}
+\usepackage{sectsty}
+\usepackage{amssymb}
+\usepackage[titles]{tocloft}
+\usepackage{doxygen}
+\lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left }
+\makeindex
+\setcounter{tocdepth}{3}
+\renewcommand{\footrulewidth}{0.4pt}
+\renewcommand{\familydefault}{\sfdefault}
+\hfuzz=15pt
+\setlength{\emergencystretch}{15pt}
+\hbadness=750
+\tolerance=750
+\begin{document}
+\hypersetup{pageanchor=false,citecolor=blue}
+\begin{titlepage}
+\vspace*{7cm}
+\begin{center}
+{\Huge libopencm3: API Reference\\ STM STM32F4 ARM Cortex M4 Series}\\
+\vspace*{1cm}
+{\large Generated by Doxygen 1.8.2}\\
+\vspace*{0.5cm}
+{\small Thu Sep 13 2012 23:26:45}\\
+\end{center}
+\end{titlepage}
+\pagenumbering{arabic}
+\hypersetup{pageanchor=true,citecolor=blue}
diff --git a/libopencm3/doc/stm32f4/index.html b/libopencm3/doc/stm32f4/index.html
new file mode 100644
index 0000000..7715877
--- /dev/null
+++ b/libopencm3/doc/stm32f4/index.html
@@ -0,0 +1,8 @@
+
+
+
+
+
+ Documentation index
+
+
diff --git a/libopencm3/doc/stm32l1/Doxyfile b/libopencm3/doc/stm32l1/Doxyfile
new file mode 100644
index 0000000..34908e8
--- /dev/null
+++ b/libopencm3/doc/stm32l1/Doxyfile
@@ -0,0 +1,43 @@
+# HTML Documentation for STM32L1 code level
+
+# 15 December 2012
+# (C) Ken Sarkies
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_stm32l1.log
+
+INPUT = ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/stm32/l1 \
+ ../../include/libopencm3/stm32/common
+
+INPUT += ../../lib/stm32/l1 \
+ ../../lib/stm32/common
+
+EXCLUDE = ../../include/libopencm3/stm32/common/gpio_common_f24.h \
+ ../../include/libopencm3/stm32/common/timer_common_f24.h \
+ ../../include/libopencm3/stm32/common/crypto_common_f24.h \
+ ../../include/libopencm3/stm32/common/hash_common_f24.h
+
+EXCLUDE += ../../lib/stm32/common/gpio_common_f24.c \
+ ../../lib/stm32/common/timer_common_f24.c \
+ ../../lib/stm32/common/crypto_common_f24.c \
+ ../../lib/stm32/common/hash_common_f24.c
+
+EXCLUDE_PATTERNS =
+
+LAYOUT_FILE = DoxygenLayout_stm32l1.xml
+
+GENERATE_TAGFILE = stm32l1.tag
+
+ENABLE_PREPROCESSING = YES
+
+
diff --git a/libopencm3/doc/stm32l1/Doxyfile_latex b/libopencm3/doc/stm32l1/Doxyfile_latex
new file mode 100644
index 0000000..51d217f
--- /dev/null
+++ b/libopencm3/doc/stm32l1/Doxyfile_latex
@@ -0,0 +1,40 @@
+# LaTeX Documentation for STM32L1 code level
+
+# 14 September 2012
+# (C) Ken Sarkies
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_stm32l1_latex.log
+
+INPUT = ../../include/libopencm3/docmain.dox \
+ ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/stm32/l1 \
+ ../../include/libopencm3/stm32/common
+
+INPUT += ../../lib/stm32/l1 \
+ ../../lib/stm32/common
+
+EXCLUDE = ../../include/libopencm3/stm32/l1/doc-stm32l1.h \
+ ../../include/libopencm3/stm32/common/gpio_common_f24.h
+
+EXCLUDE += ../../lib/stm32/common/gpio_common_f24.c
+
+EXCLUDE_PATTERNS =
+
+LAYOUT_FILE = DoxygenLayout_stm32l1.xml
+
+GENERATE_HTML = NO
+
+GENERATE_LATEX = YES
+
+LATEX_HEADER = header_stm32l1.tex
+
diff --git a/libopencm3/doc/stm32l1/DoxygenLayout_stm32l1.xml b/libopencm3/doc/stm32l1/DoxygenLayout_stm32l1.xml
new file mode 100644
index 0000000..46fef45
--- /dev/null
+++ b/libopencm3/doc/stm32l1/DoxygenLayout_stm32l1.xml
@@ -0,0 +1,206 @@
+
+
+
+
+
+
+
+
+
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diff --git a/libopencm3/doc/stm32l1/header_stm32l1.tex b/libopencm3/doc/stm32l1/header_stm32l1.tex
new file mode 100644
index 0000000..edf6907
--- /dev/null
+++ b/libopencm3/doc/stm32l1/header_stm32l1.tex
@@ -0,0 +1,61 @@
+\documentclass{book}
+\usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry}
+\usepackage{makeidx}
+\usepackage{natbib}
+\usepackage{graphicx}
+\usepackage{multicol}
+\usepackage{float}
+\usepackage{listings}
+\usepackage{color}
+\usepackage{ifthen}
+\usepackage[table]{xcolor}
+\usepackage{textcomp}
+\usepackage{alltt}
+\usepackage{ifpdf}
+\ifpdf
+\usepackage[pdftex,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\else
+\usepackage[ps2pdf,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\usepackage{pspicture}
+\fi
+\usepackage[utf8]{inputenc}
+\usepackage{mathptmx}
+\usepackage[scaled=.90]{helvet}
+\usepackage{courier}
+\usepackage{sectsty}
+\usepackage{amssymb}
+\usepackage[titles]{tocloft}
+\usepackage{doxygen}
+\lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left }
+\makeindex
+\setcounter{tocdepth}{3}
+\renewcommand{\footrulewidth}{0.4pt}
+\renewcommand{\familydefault}{\sfdefault}
+\hfuzz=15pt
+\setlength{\emergencystretch}{15pt}
+\hbadness=750
+\tolerance=750
+\begin{document}
+\hypersetup{pageanchor=false,citecolor=blue}
+\begin{titlepage}
+\vspace*{7cm}
+\begin{center}
+{\Huge libopencm3: API Reference\\ STM STM32L1 ARM Cortex M3 Series}\\
+\vspace*{1cm}
+{\large Generated by Doxygen 1.8.2}\\
+\vspace*{0.5cm}
+{\small Thu Sep 13 2012 23:26:45}\\
+\end{center}
+\end{titlepage}
+\pagenumbering{arabic}
+\hypersetup{pageanchor=true,citecolor=blue}
diff --git a/libopencm3/doc/stm32l1/index.html b/libopencm3/doc/stm32l1/index.html
new file mode 100644
index 0000000..7715877
--- /dev/null
+++ b/libopencm3/doc/stm32l1/index.html
@@ -0,0 +1,8 @@
+
+
+
+
+
+ Documentation index
+
+
diff --git a/libopencm3/doc/usb/Doxyfile b/libopencm3/doc/usb/Doxyfile
new file mode 100644
index 0000000..fcd2745
--- /dev/null
+++ b/libopencm3/doc/usb/Doxyfile
@@ -0,0 +1,31 @@
+# HTML Documentation for USB code level
+
+# 10 March 2013
+# (C) Ken Sarkies
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_usb.log
+
+INPUT = ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/usb
+
+INPUT += ../../lib/usb
+
+EXCLUDE_PATTERNS =
+
+LAYOUT_FILE = DoxygenLayout_usb.xml
+
+GENERATE_TAGFILE = usb.tag
+
+ENABLE_PREPROCESSING = NO
+
+
diff --git a/libopencm3/doc/usb/Doxyfile_latex b/libopencm3/doc/usb/Doxyfile_latex
new file mode 100644
index 0000000..00392aa
--- /dev/null
+++ b/libopencm3/doc/usb/Doxyfile_latex
@@ -0,0 +1,40 @@
+# LaTeX Documentation for USB code level
+
+# 10 March 2013
+# (C) Ken Sarkies
+
+#---------------------------------------------------------------------------
+# Common Include File
+#---------------------------------------------------------------------------
+
+@INCLUDE = ../Doxyfile_common
+
+#---------------------------------------------------------------------------
+# Local settings
+#---------------------------------------------------------------------------
+
+WARN_LOGFILE = doxygen_usb_latex.log
+
+WARN_LOGFILE = doxygen_usb.log
+
+INPUT = ../../include/libopencm3/license.dox \
+ ../../include/libopencm3/usb
+
+INPUT += ../../lib/usb
+
+EXCLUDE_PATTERNS =
+
+LAYOUT_FILE = DoxygenLayout_usb.xml
+
+TAGFILES =
+
+GENERATE_TAGFILE = usb.tag
+
+ENABLE_PREPROCESSING = NO
+
+GENERATE_HTML = NO
+
+GENERATE_LATEX = YES
+
+LATEX_HEADER = header_usb.tex
+
diff --git a/libopencm3/doc/usb/DoxygenLayout_usb.xml b/libopencm3/doc/usb/DoxygenLayout_usb.xml
new file mode 100644
index 0000000..befab61
--- /dev/null
+++ b/libopencm3/doc/usb/DoxygenLayout_usb.xml
@@ -0,0 +1,206 @@
+
+
+
+
+
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diff --git a/libopencm3/doc/usb/header_usb.tex b/libopencm3/doc/usb/header_usb.tex
new file mode 100644
index 0000000..5b90252
--- /dev/null
+++ b/libopencm3/doc/usb/header_usb.tex
@@ -0,0 +1,61 @@
+\documentclass{book}
+\usepackage[a4paper,top=2.5cm,bottom=2.5cm,left=2.5cm,right=2.5cm]{geometry}
+\usepackage{makeidx}
+\usepackage{natbib}
+\usepackage{graphicx}
+\usepackage{multicol}
+\usepackage{float}
+\usepackage{listings}
+\usepackage{color}
+\usepackage{ifthen}
+\usepackage[table]{xcolor}
+\usepackage{textcomp}
+\usepackage{alltt}
+\usepackage{ifpdf}
+\ifpdf
+\usepackage[pdftex,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\else
+\usepackage[ps2pdf,
+ pagebackref=true,
+ colorlinks=true,
+ linkcolor=blue,
+ unicode
+ ]{hyperref}
+\usepackage{pspicture}
+\fi
+\usepackage[utf8]{inputenc}
+\usepackage{mathptmx}
+\usepackage[scaled=.90]{helvet}
+\usepackage{courier}
+\usepackage{sectsty}
+\usepackage{amssymb}
+\usepackage[titles]{tocloft}
+\usepackage{doxygen}
+\lstset{language=C++,inputencoding=utf8,basicstyle=\footnotesize,breaklines=true,breakatwhitespace=true,tabsize=4,numbers=left }
+\makeindex
+\setcounter{tocdepth}{3}
+\renewcommand{\footrulewidth}{0.4pt}
+\renewcommand{\familydefault}{\sfdefault}
+\hfuzz=15pt
+\setlength{\emergencystretch}{15pt}
+\hbadness=750
+\tolerance=750
+\begin{document}
+\hypersetup{pageanchor=false,citecolor=blue}
+\begin{titlepage}
+\vspace*{7cm}
+\begin{center}
+{\Huge libopencm3: API Reference\\ Cortex M3 Generic USB}\\
+\vspace*{1cm}
+{\large Generated by Doxygen 1.8.2}\\
+\vspace*{0.5cm}
+{\small Thu 10 March 2013 23:26:45}\\
+\end{center}
+\end{titlepage}
+\pagenumbering{arabic}
+\hypersetup{pageanchor=true,citecolor=blue}
diff --git a/libopencm3/include/libopencm3/cm3/assert.h b/libopencm3/include/libopencm3/cm3/assert.h
new file mode 100644
index 0000000..f1aabc3
--- /dev/null
+++ b/libopencm3/include/libopencm3/cm3/assert.h
@@ -0,0 +1,137 @@
+/** @defgroup debugging Debugging
+
+@brief Macros and functions to aid in debugging
+
+@version 1.0.0
+
+@date 25 September 2012
+
+Two preprocessor defines control the behavior of assertion check macros in
+this module. They allow the choice between generated code size and ease of
+debugging.
+
+If NDEBUG is defined, all assertion checks are disabled and macros do not
+generate any code.
+
+If CM3_ASSERT_VERBOSE is defined, information regarding the position of
+assertion checks will be stored in the binary, allowing for more
+informative error messages, but also significantly increased code size. As
+default assertion checks do not use this information it is only useful if
+the application linked with libopencm3 defines its own
+cm3_assert_failed_verbose() implementation.
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Tomaz Solc
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+/**@{*/
+
+#ifndef LIBOPENCM3_CM3_ASSERT_H
+#define LIBOPENCM3_CM3_ASSERT_H
+
+#include
+
+#define CM3_LIKELY(expr) (__builtin_expect(!!(expr), 1))
+
+#ifdef NDEBUG
+# define cm3_assert(expr) (void)0
+# define cm3_assert_not_reached() do { } while (1)
+#else
+# ifdef CM3_ASSERT_VERBOSE
+# define cm3_assert(expr) do { \
+ if (CM3_LIKELY(expr)) { \
+ (void)0; \
+ } else { \
+ cm3_assert_failed_verbose( \
+ __FILE__, __LINE__, \
+ __func__, #expr); \
+ } \
+ } while (0)
+# define cm3_assert_not_reached() \
+ cm3_assert_failed_verbose( \
+ __FILE__, __LINE__, \
+ __func__, 0)
+# else
+/** @brief Check if assertion is true.
+ *
+ * If NDEBUG macro is defined, this macro generates no code. Otherwise
+ * cm3_assert_failed() or cm3_assert_failed_verbose() is called if assertion
+ * is false.
+ *
+ * The purpose of this macro is to aid in debugging libopencm3 and
+ * applications using it. It can be used for example to check if function
+ * arguments are within expected ranges and stop execution in case an
+ * unexpected state is reached.
+ *
+ * @param expr expression to check */
+# define cm3_assert(expr) do { \
+ if (CM3_LIKELY(expr)) { \
+ (void)0; \
+ } else { \
+ cm3_assert_failed(); \
+ } \
+ } while (0)
+/** @brief Check if unreachable code is reached.
+ *
+ * If NDEBUG macro is defined, this macro generates code for an infinite loop.
+ * Otherwise cm3_assert_failed() or cm3_assert_failed_verbose() is called if
+ * the macro is ever reached.
+ *
+ * The purpose of this macro is to aid in debugging libopencm3 and
+ * applications using it. It can be used for example to stop execution if an
+ * unreachable portion of code is reached. */
+# define cm3_assert_not_reached() cm3_assert_failed()
+# endif
+#endif
+
+BEGIN_DECLS
+
+/** @brief Called on a failed assertion.
+ *
+ * Halts execution in an infinite loop. This function never returns.
+ *
+ * Defined as a weak symbol, so applications can define their own
+ * implementation. Usually, a custom implementation of this function should
+ * report an error in some way (print a message to a debug console, display,
+ * LED, ...) and halt execution or reboot the device. */
+void cm3_assert_failed(void) __attribute__((__noreturn__));
+
+/** @brief Called on a failed assertion with verbose messages enabled.
+ *
+ * Halts execution in an infinite loop. This function never returns.
+ *
+ * Defined as a weak symbol, so applications can define their own
+ * implementation. Usually, a custom implementation of this function should
+ * report an error in some way (print a message to a debug console, display,
+ * LED, ...) and halt execution or reboot the device.
+ *
+ * @param file File name where the failed assertion occurred
+ * @param line Line number where the failed assertion occurred
+ * @param func Name of the function where the failed assertion occurred
+ * @param assert_expr Expression that evaluated to false (can be NULL) */
+void cm3_assert_failed_verbose(const char *file, int line, const char *func,
+ const char *assert_expr) __attribute__((__noreturn__));
+
+END_DECLS
+
+#endif
+
+/**@}*/
diff --git a/libopencm3/include/libopencm3/cm3/common.h b/libopencm3/include/libopencm3/cm3/common.h
new file mode 100644
index 0000000..a7a8df8
--- /dev/null
+++ b/libopencm3/include/libopencm3/cm3/common.h
@@ -0,0 +1,96 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LIBOPENCM3_CM3_COMMON_H
+#define LIBOPENCM3_CM3_COMMON_H
+
+#include
+#include
+
+/* This must be placed around external function declaration for C++
+ * support. */
+#ifdef __cplusplus
+# define BEGIN_DECLS extern "C" {
+# define END_DECLS }
+#else
+# define BEGIN_DECLS
+# define END_DECLS
+#endif
+
+/* Full-featured deprecation attribute with fallback for older compilers. */
+
+#ifdef __GNUC__
+# if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ > 4)
+# define LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x)))
+# else
+# define LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated))
+# endif
+#else
+# define LIBOPENCM3_DEPRECATED(x)
+#endif
+
+
+/* Generic memory-mapped I/O accessor functions */
+#define MMIO8(addr) (*(volatile uint8_t *)(addr))
+#define MMIO16(addr) (*(volatile uint16_t *)(addr))
+#define MMIO32(addr) (*(volatile uint32_t *)(addr))
+#define MMIO64(addr) (*(volatile uint64_t *)(addr))
+
+/* Generic bit-band I/O accessor functions */
+#define BBIO_SRAM(addr, bit) \
+ MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4)
+
+#define BBIO_PERIPH(addr, bit) \
+ MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4)
+
+/* Generic bit definition */
+#define BIT0 (1<<0)
+#define BIT1 (1<<1)
+#define BIT2 (1<<2)
+#define BIT3 (1<<3)
+#define BIT4 (1<<4)
+#define BIT5 (1<<5)
+#define BIT6 (1<<6)
+#define BIT7 (1<<7)
+#define BIT8 (1<<8)
+#define BIT9 (1<<9)
+#define BIT10 (1<<10)
+#define BIT11 (1<<11)
+#define BIT12 (1<<12)
+#define BIT13 (1<<13)
+#define BIT14 (1<<14)
+#define BIT15 (1<<15)
+#define BIT16 (1<<16)
+#define BIT17 (1<<17)
+#define BIT18 (1<<18)
+#define BIT19 (1<<19)
+#define BIT20 (1<<20)
+#define BIT21 (1<<21)
+#define BIT22 (1<<22)
+#define BIT23 (1<<23)
+#define BIT24 (1<<24)
+#define BIT25 (1<<25)
+#define BIT26 (1<<26)
+#define BIT27 (1<<27)
+#define BIT28 (1<<28)
+#define BIT29 (1<<29)
+#define BIT30 (1<<30)
+#define BIT31 (1<<31)
+
+#endif
diff --git a/libopencm3/include/libopencm3/cm3/cortex.h b/libopencm3/include/libopencm3/cm3/cortex.h
new file mode 100644
index 0000000..eb9cb09
--- /dev/null
+++ b/libopencm3/include/libopencm3/cm3/cortex.h
@@ -0,0 +1,278 @@
+/** @defgroup CM3_cortex_defines Cortex Core Defines
+ *
+ * @brief libopencm3 Defined Constants and Types for the Cortex Core
+ *
+ * @ingroup CM3_defines
+ *
+ * @version 1.0.0
+ *
+ * LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2013 Ben Gamari
+ * Copyright (C) 2013 Frantisek Burian
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LIBOPENCM3_CORTEX_H
+#define LIBOPENCM3_CORTEX_H
+
+/**@{*/
+
+/*---------------------------------------------------------------------------*/
+/** @brief Cortex M Enable interrupts
+ *
+ * Disable the interrupt mask and enable interrupts globally
+ */
+static inline void cm_enable_interrupts(void)
+{
+ __asm__("CPSIE I\n");
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Cortex M Disable interrupts
+ *
+ * Mask all interrupts globally
+ */
+static inline void cm_disable_interrupts(void)
+{
+ __asm__("CPSID I\n");
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Cortex M Enable faults
+ *
+ * Disable the HardFault mask and enable fault interrupt globally
+ */
+static inline void cm_enable_faults(void)
+{
+ __asm__("CPSIE F\n");
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Cortex M Disable faults
+ *
+ * Mask the HardFault interrupt globally
+ */
+static inline void cm_disable_faults(void)
+{
+ __asm__("CPSID F\n");
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Cortex M Check if interrupts are masked
+ *
+ * Checks, if interrupts are masked (disabled).
+ *
+ * @returns true, if interrupts are disabled.
+ */
+__attribute__((always_inline))
+static inline bool cm_is_masked_interrupts(void)
+{
+ register uint32_t result;
+ __asm__ ("MRS %0, PRIMASK" : "=r" (result));
+ return result;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Cortex M Check if Fault interrupt is masked
+ *
+ * Checks, if HardFault interrupt is masked (disabled).
+ *
+ * @returns bool true, if HardFault interrupt is disabled.
+ */
+__attribute__((always_inline))
+static inline bool cm_is_masked_faults(void)
+{
+ register uint32_t result;
+ __asm__ ("MRS %0, FAULTMASK" : "=r" (result));
+ return result;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Cortex M Mask interrupts
+ *
+ * This function switches the mask of the interrupts. If mask is true, the
+ * interrupts will be disabled. The result of this function can be used for
+ * restoring previous state of the mask.
+ *
+ * @param[in] mask bool New state of the interrupt mask
+ * @returns bool old state of the interrupt mask
+ */
+__attribute__((always_inline))
+static inline bool cm_mask_interrupts(bool mask)
+{
+ register bool old;
+ __asm__ __volatile__("MRS %0, PRIMASK" : "=r" (old));
+ __asm__ __volatile__("" : : : "memory");
+ __asm__ __volatile__("MSR PRIMASK, %0" : : "r" (mask));
+ return old;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Cortex M Mask HardFault interrupt
+ *
+ * This function switches the mask of the HardFault interrupt. If mask is true,
+ * the HardFault interrupt will be disabled. The result of this function can be
+ * used for restoring previous state of the mask.
+ *
+ * @param[in] mask bool New state of the HardFault interrupt mask
+ * @returns bool old state of the HardFault interrupt mask
+ */
+__attribute__((always_inline))
+static inline bool cm_mask_faults(bool mask)
+{
+ register bool old;
+ __asm__ __volatile__ ("MRS %0, FAULTMASK" : "=r" (old));
+ __asm__ __volatile__ ("" : : : "memory");
+ __asm__ __volatile__ ("MSR FAULTMASK, %0" : : "r" (mask));
+ return old;
+}
+
+/**@}*/
+
+/*===========================================================================*/
+/** @defgroup CM3_cortex_atomic_defines Cortex Core Atomic support Defines
+ *
+ * @brief Atomic operation support
+ *
+ * @ingroup CM3_cortex_defines
+ */
+/**@{*/
+
+#if !defined(__DOXYGEN__)
+/* Do not populate this definition outside */
+static inline bool __cm_atomic_set(bool *val)
+{
+ return cm_mask_interrupts(*val);
+}
+
+#define __CM_SAVER(state) \
+ __val = state, \
+ __save __attribute__((__cleanup__(__cm_atomic_set))) = \
+ __cm_atomic_set(&__val)
+
+#endif /* !defined(__DOXYGEN) */
+
+
+/*---------------------------------------------------------------------------*/
+/** @brief Cortex M Atomic Declare block
+ *
+ * This macro disables interrupts for the next command or block of code. The
+ * interrupt mask is automatically restored after exit of the boundary of the
+ * code block. Therefore restore of interrupt is done automatically after call
+ * of return or goto control sentence jumping outside of the block.
+ *
+ * @warning The usage of sentences break or continue is prohibited in the block
+ * due to implementation of this macro!
+ *
+ * @note It is safe to use this block inside normal code and in interrupt
+ * routine.
+ *
+ * @example 1: Basic usage of atomic block
+ *
+ * @code
+ * uint64_t value; // This value is used somewhere in interrupt
+ *
+ * ...
+ *
+ * CM_ATOMIC_BLOCK() { // interrupts are masked in this block
+ * value = value * 1024 + 651; // access value as atomic
+ * } // interrupts is restored automatically
+ * @endcode
+ *
+ * @example 2: Use of return inside block:
+ *
+ * @code
+ * uint64_t value; // This value is used somewhere in interrupt
+ *
+ * ...
+ *
+ * uint64_t allocval(void)
+ * {
+ * CM_ATOMIC_BLOCK() { // interrupts are masked in this block
+ * value = value * 1024 + 651; // do long atomic operation
+ * return value; // interrupts is restored automatically
+ * }
+ * }
+ * @endcode
+ */
+#if defined(__DOXYGEN__)
+#define CM_ATOMIC_BLOCK()
+#else /* defined(__DOXYGEN__) */
+#define CM_ATOMIC_BLOCK() \
+ for (bool ___CM_SAVER(true), __my = true; __my; __my = false)
+#endif /* defined(__DOXYGEN__) */
+
+/*---------------------------------------------------------------------------*/
+/** @brief Cortex M Atomic Declare context
+ *
+ * This macro disables interrupts in the current block of code from the place
+ * where it is defined to the end of the block. The interrupt mask is
+ * automatically restored after exit of the boundary of the code block.
+ * Therefore restore of interrupt is done automatically after call of return,
+ * continue, break, or goto control sentence jumping outside of the block.
+ *
+ * @note This function is intended for use in for- cycles to enable the use of
+ * break and contine sentences inside the block, and for securing the atomic
+ * reader-like functions.
+ *
+ * @note It is safe to use this block inside normal code and in interrupt
+ * routine.
+ *
+ * @example 1: Basic usage of atomic context
+ *
+ * @code
+ * uint64_t value; // This value is used somewhere in interrupt
+ *
+ * ...
+ *
+ * for (int i=0;i < 100; i++) {
+ * CM_ATOMIC_CONTEXT(); // interrupts are masked in this block
+ * value += 100; // access value as atomic
+ * if ((value % 16) == 0) {
+ * break; // restore interrupts and break cycle
+ * }
+ * } // interrupts is restored automatically
+ * @endcode
+ *
+ * @example 2: Usage of atomic context inside atomic reader fcn.
+ *
+ * @code
+ * uint64_t value; // This value is used somewhere in interrupt
+ *
+ * ...
+ *
+ * uint64_t getnextval(void)
+ * {
+ * CM_ATOMIC_CONTEXT(); // interrupts are masked in this block
+ * value = value + 3; // do long atomic operation
+ * return value; // interrupts is restored automatically
+ * }
+ * @endcode
+ */
+#if defined(__DOXYGEN__)
+#define CM_ATOMIC_CONTEXT()
+#else /* defined(__DOXYGEN__) */
+#define CM_ATOMIC_CONTEXT() bool __CM_SAVER(true)
+#endif /* defined(__DOXYGEN__) */
+
+/**@}*/
+
+
+
+#endif
diff --git a/libopencm3/include/libopencm3/cm3/doc-cm3.h b/libopencm3/include/libopencm3/cm3/doc-cm3.h
new file mode 100644
index 0000000..0f76370
--- /dev/null
+++ b/libopencm3/include/libopencm3/cm3/doc-cm3.h
@@ -0,0 +1,22 @@
+/** @mainpage libopencm3 Core CM3
+
+@version 1.0.0
+
+@date 14 September 2012
+
+API documentation for Cortex M3 core features.
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup CM3_defines CM3 Defines
+
+@brief Defined Constants and Types for Cortex M3 core features
+
+@version 1.0.0
+
+@date 14 September 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
diff --git a/libopencm3/include/libopencm3/cm3/dwt.h b/libopencm3/include/libopencm3/cm3/dwt.h
new file mode 100644
index 0000000..184b509
--- /dev/null
+++ b/libopencm3/include/libopencm3/cm3/dwt.h
@@ -0,0 +1,152 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2013 Frantisek Burian
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LIBOPENCM3_CM3_DWT_H
+#define LIBOPENCM3_CM3_DWT_H
+
+#include
+#include
+
+/*****************************************************************************/
+/* Register definitions */
+/*****************************************************************************/
+
+#define DWT_CTRL MMIO32(DWT_BASE + 0x00)
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+
+#define DWT_CYCCNT MMIO32(DWT_BASE + 0x04)
+#define DWT_CPICNT MMIO32(DWT_BASE + 0x08)
+#define DWT_EXCCNT MMIO32(DWT_BASE + 0x0C)
+#define DWT_SLEEPCNT MMIO32(DWT_BASE + 0x10)
+#define DWT_LSUCNT MMIO32(DWT_BASE + 0x14)
+#define DWT_FOLDCNT MMIO32(DWT_BASE + 0x18)
+
+#endif /* defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) */
+
+#define DWT_PCSR MMIO32(DWT_BASE + 0x1C)
+#define DWT_COMP(n) MMIO32(DWT_BASE + 0x20 + (n) * 16)
+#define DWT_MASK(n) MMIO32(DWT_BASE + 0x24 + (n) * 16)
+#define DWT_FUNCTION(n) MMIO32(DWT_BASE + 0x28 + (n) * 16)
+
+/*****************************************************************************/
+/* Register values */
+/*****************************************************************************/
+
+/* --- DWT_CTRL values ---------------------------------------------------- */
+
+#define DWT_CTRL_NUMCOMP_SHIFT 28
+#define DWT_CTRL_NUMCOMP (0x0F << DWT_CTRL_NUMCOMP_SHIFT)
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+
+#define DWT_CTRL_NOTRCPKT (1 << 27)
+#define DWT_CTRL_NOEXTTRIG (1 << 26)
+#define DWT_CTRL_NOCYCCNT (1 << 25)
+#define DWT_CTRL_NOPRFCCNT (1 << 24)
+
+#define DWT_CTRL_CYCEVTENA (1 << 22)
+#define DWT_CTRL_FOLDEVTENA (1 << 21)
+#define DWT_CTRL_LSUEVTENA (1 << 20)
+#define DWT_CTRL_SLEEPEVTENA (1 << 19)
+#define DWT_CTRL_EXCEVTENA (1 << 18)
+#define DWT_CTRL_CPIEVTENA (1 << 17)
+#define DWT_CTRL_EXCTRCENA (1 << 16)
+#define DWT_CTRL_PCSAMPLENA (1 << 12)
+
+#define DWT_CTRL_SYNCTAP_SHIFT 10
+#define DWT_CTRL_SYNCTAP (3 << DWT_CTRL_SYNCTAP_SHIFT)
+#define DWT_CTRL_SYNCTAP_DISABLED (0 << DWT_CTRL_SYNCTAP_SHIFT)
+#define DWT_CTRL_SYNCTAP_BIT24 (1 << DWT_CTRL_SYNCTAP_SHIFT)
+#define DWT_CTRL_SYNCTAP_BIT26 (2 << DWT_CTRL_SYNCTAP_SHIFT)
+#define DWT_CTRL_SYNCTAP_BIT28 (3 << DWT_CTRL_SYNCTAP_SHIFT)
+
+#define DWT_CTRL_CYCTAP (1 << 9)
+
+#define DWT_CTRL_POSTCNT_SHIFT 5
+#define DWT_CTRL_POSTCNT (0x0F << DWT_CTRL_POSTCNT_SHIFT)
+
+#define DWT_CTRL_POSTPRESET_SHIFT 1
+#define DWT_CTRL_POSTPRESET (0x0F << DWT_CTRL_POSTPRESET_SHIFT)
+
+#define DWT_CTRL_CYCCNTENA (1 << 0)
+
+#endif /* defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) */
+
+/* --- DWT_MASK(x) values -------------------------------------------------- */
+
+#define DWT_MASKx_MASK 0x0F
+
+/* --- DWT_FUNCTION(x) values ---------------------------------------------- */
+
+#define DWT_FUNCTIONx_MATCHED (1 << 24)
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+
+#define DWT_FUNCTIONx_DATAVADDR1_SHIFT 16
+#define DWT_FUNCTIONx_DATAVADDR1 (15 << DWT_FUNCTIONx_DATAVADDR1_SHIFT)
+
+#define DWT_FUNCTIONx_DATAVADDR0_SHIFT 12
+#define DWT_FUNCTIONx_DATAVADDR0 (15 << DWT_FUNCTIONx_DATAVADDR0_SHIFT)
+
+#define DWT_FUNCTIONx_DATAVSIZE_SHIFT 10
+#define DWT_FUNCTIONx_DATAVSIZE (3 << DWT_FUNCTIONx_DATAVSIZE_SHIFT)
+#define DWT_FUNCTIONx_DATAVSIZE_BYTE (0 << DWT_FUNCTIONx_DATAVSIZE_SHIFT)
+#define DWT_FUNCTIONx_DATAVSIZE_HALF (1 << DWT_FUNCTIONx_DATAVSIZE_SHIFT)
+#define DWT_FUNCTIONx_DATAVSIZE_WORD (2 << DWT_FUNCTIONx_DATAVSIZE_SHIFT)
+
+#define DWT_FUNCTIONx_LNK1ENA (1 << 9)
+#define DWT_FUNCTIONx_DATAVMATCH (1 << 8)
+#define DWT_FUNCTIONx_CYCMATCH (1 << 7)
+#define DWT_FUNCTIONx_EMITRANGE (1 << 5)
+
+#endif /* defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) */
+
+#define DWT_FUNCTIONx_FUNCTION 15
+#define DWT_FUNCTIONx_FUNCTION_DISABLED 0
+
+/* Those defined only on ARMv6 */
+#if defined(__ARM_ARCH_6M__)
+
+#define DWT_FUNCTIONx_FUNCTION_PCWATCH 4
+#define DWT_FUNCTIONx_FUNCTION_DWATCH_R 5
+#define DWT_FUNCTIONx_FUNCTION_DWATCH_W 6
+#define DWT_FUNCTIONx_FUNCTION_DWATCH_RW 7
+
+#endif /* defined(__ARM_ARCH_6M__)*/
+
+/*****************************************************************************/
+/* API definitions */
+/*****************************************************************************/
+
+/*****************************************************************************/
+/* API Functions */
+/*****************************************************************************/
+
+BEGIN_DECLS
+
+bool dwt_enable_cycle_counter(void);
+uint32_t dwt_read_cycle_counter(void);
+
+END_DECLS
+
+#endif /* LIBOPENCM3_CM3_DWT_H */
diff --git a/libopencm3/include/libopencm3/cm3/fpb.h b/libopencm3/include/libopencm3/cm3/fpb.h
new file mode 100644
index 0000000..fe624da
--- /dev/null
+++ b/libopencm3/include/libopencm3/cm3/fpb.h
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Gareth McMullin
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LIBOPENCM3_CM3_FPB_H
+#define LIBOPENCM3_CM3_FPB_H
+
+/* Cortex-M3 Flash Patch and Breakpoint (FPB) unit */
+
+/* Those defined only on ARMv7 and above */
+#if !defined(__ARM_ARCH_7M__) || !defined(__ARM_ARCH_7EM__)
+#error "Flash Patch and Breakpoint not available in CM0"
+#endif
+
+/* Note: We always use "FPB" as abbreviation, docs sometimes use only "FP". */
+
+/* --- FPB registers ------------------------------------------------------- */
+
+/* Flash Patch Control (FPB_CTRL) */
+#define FPB_CTRL MMIO32(FPB_BASE + 0)
+
+/* Flash Patch Remap (FPB_REMAP) */
+#define FPB_REMAP MMIO32(FPB_BASE + 4)
+
+/* Flash Patch Comparator (FPB_COMPx) */
+#define FPB_COMP (&MMIO32(FPB_BASE + 8))
+
+/* CoreSight Lock Status Register for this peripheral */
+#define FPB_LSR MMIO32(FPB_BASE + 0xFB4)
+/* CoreSight Lock Access Register for this peripheral */
+#define FPB_LAR MMIO32(FPB_BASE + 0xFB0)
+
+
+/* TODO: PID, CID */
+
+/* --- FPB_CTRL values ----------------------------------------------------- */
+
+/* Bits [31:15]: Reserved, read as zero, writes ignored */
+
+#define FPB_CTRL_NUM_CODE2_MASK (0x7 << 12)
+
+#define FPB_CTRL_NUM_LIT_MASK (0xf << 8)
+
+#define FPB_CTRL_NUM_CODE1_MASK (0xf << 4)
+
+/* Bits [3:2]: Reserved */
+
+#define FPB_CTRL_KEY (1 << 1)
+
+#define FPB_CTRL_ENABLE (1 << 0)
+
+/* --- FPB_REMAP values ---------------------------------------------------- */
+
+/* TODO */
+
+/* --- FPB_COMPx values ---------------------------------------------------- */
+
+#define FPB_COMP_REPLACE_REMAP (0x0 << 30)
+#define FPB_COMP_REPLACE_BREAK_LOWER (0x1 << 30)
+#define FPB_COMP_REPLACE_BREAK_UPPER (0x2 << 30)
+#define FPB_COMP_REPLACE_BREAK_BOTH (0x3 << 30)
+#define FPB_COMP_REPLACE_MASK (0x3 << 30)
+
+/* Bit 29: Reserved */
+
+/* TODO */
+
+/* Bit 1: Reserved */
+
+#define FPB_COMP_ENABLE (1 << 0)
+
+#endif
diff --git a/libopencm3/include/libopencm3/cm3/itm.h b/libopencm3/include/libopencm3/cm3/itm.h
new file mode 100644
index 0000000..8b55119
--- /dev/null
+++ b/libopencm3/include/libopencm3/cm3/itm.h
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Gareth McMullin
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LIBOPENCM3_CM3_ITM_H
+#define LIBOPENCM3_CM3_ITM_H
+
+/* Cortex-M3 Instrumentation Trace Macrocell (ITM) */
+
+/* Those defined only on ARMv7 and above */
+#if !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__)
+#error "Instrumentation Trace Macrocell not available in CM0"
+#endif
+
+/* --- ITM registers ------------------------------------------------------- */
+
+/* Stimulus Port x (ITM_STIM(x)) */
+#define ITM_STIM8(n) (MMIO8(ITM_BASE + (n*4)))
+#define ITM_STIM16(n) (MMIO16(ITM_BASE + (n*4)))
+#define ITM_STIM32(n) (MMIO32(ITM_BASE + (n*4)))
+
+/* Trace Enable ports (ITM_TER[x]) */
+#define ITM_TER (&MMIO32(ITM_BASE + 0xE00))
+
+/* Trace Privilege (ITM_TPR) */
+#define ITM_TPR MMIO32(ITM_BASE + 0xE40)
+
+/* Trace Control (ITM_TCR) */
+#define ITM_TCR MMIO32(ITM_BASE + 0xE80)
+
+/* CoreSight Lock Status Register for this peripheral */
+#define ITM_LSR MMIO32(ITM_BASE + 0xFB4)
+/* CoreSight Lock Access Register for this peripheral */
+#define ITM_LAR MMIO32(ITM_BASE + 0xFB0)
+
+/* TODO: PID, CID */
+
+/* --- ITM_STIM values ----------------------------------------------------- */
+
+/* Bits 31:0 - Write to port FIFO for forwarding as software event packet */
+/* Bits 31:1 - RAZ */
+#define ITM_STIM_FIFOREADY (1 << 0)
+
+/* --- ITM_TER values ------------------------------------------------------ */
+
+/* Bits 31:0 - Stimulus port #N is enabled with STIMENA[N] is set */
+
+/* --- ITM_TPR values ------------------------------------------------------ */
+/*
+ * Bits 31:0 - Bit [N] of PRIVMASK controls stimulus ports 8N to 8N+7
+ * 0: User access allowed to stimulus ports
+ * 1: Privileged access only to stimulus ports
+ */
+
+/* --- ITM_TCR values ------------------------------------------------------ */
+
+/* Bits 31:24 - Reserved */
+#define ITM_TCR_BUSY (1 << 23)
+#define ITM_TCR_TRACE_BUS_ID_MASK (0x3f << 16)
+/* Bits 15:10 - Reserved */
+#define ITM_TCR_TSPRESCALE_NONE (0 << 8)
+#define ITM_TCR_TSPRESCALE_DIV4 (1 << 8)
+#define ITM_TCR_TSPRESCALE_DIV16 (2 << 8)
+#define ITM_TCR_TSPRESCALE_DIV64 (3 << 8)
+#define ITM_TCR_TSPRESCALE_MASK (3 << 8)
+/* Bits 7:5 - Reserved */
+#define ITM_TCR_SWOENA (1 << 4)
+#define ITM_TCR_TXENA (1 << 3)
+#define ITM_TCR_SYNCENA (1 << 2)
+#define ITM_TCR_TSENA (1 << 1)
+#define ITM_TCR_ITMENA (1 << 0)
+
+#endif
diff --git a/libopencm3/include/libopencm3/cm3/memorymap.h b/libopencm3/include/libopencm3/cm3/memorymap.h
new file mode 100644
index 0000000..a7a5694
--- /dev/null
+++ b/libopencm3/include/libopencm3/cm3/memorymap.h
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LIBOPENCM3_CM3_MEMORYMAP_H
+#define LIBOPENCM3_CM3_MEMORYMAP_H
+
+/* --- ARM Cortex-M0, M3 and M4 specific definitions ----------------------- */
+
+/* Private peripheral bus - Internal */
+#define PPBI_BASE (0xE0000000U)
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+/* ITM: Instrumentation Trace Macrocell */
+#define ITM_BASE (PPBI_BASE + 0x0000)
+
+/* DWT: Data Watchpoint and Trace unit */
+#define DWT_BASE (PPBI_BASE + 0x1000)
+
+/* FPB: Flash Patch and Breakpoint unit */
+#define FPB_BASE (PPBI_BASE + 0x2000)
+#endif
+
+/* PPBI_BASE + 0x3000 (0xE000 3000 - 0xE000 DFFF): Reserved */
+
+#define SCS_BASE (PPBI_BASE + 0xE000)
+
+/* PPBI_BASE + 0xF000 (0xE000 F000 - 0xE003 FFFF): Reserved */
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+#define TPIU_BASE (PPBI_BASE + 0x40000)
+#endif
+
+/* --- SCS: System Control Space --- */
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+/* ITR: Interrupt Type Register */
+#define ITR_BASE (SCS_BASE + 0x0000)
+#endif
+
+/* SYS_TICK: System Timer */
+#define SYS_TICK_BASE (SCS_BASE + 0x0010)
+
+/* NVIC: Nested Vector Interrupt Controller */
+#define NVIC_BASE (SCS_BASE + 0x0100)
+
+/* SCB: System Control Block */
+#define SCB_BASE (SCS_BASE + 0x0D00)
+
+#ifdef CM0_PLUS
+/* MPU: Memory protection unit */
+#define MPU_BASE (SCS_BASE + 0x0D90)
+#endif
+
+/* Those defined only on CM0*/
+#if defined(__ARM_ARCH_6M__)
+/* DEBUG: Debug control and configuration */
+#define DEBUG_BASE (SCS_BASE + 0x0DF0)
+#endif
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+/* STE: Software Trigger Interrupt Register */
+#define STIR_BASE (SCS_BASE + 0x0F00)
+/* ID: ID space */
+#define ID_BASE (SCS_BASE + 0x0FD0)
+#endif
+
+#endif
diff --git a/libopencm3/include/libopencm3/cm3/mpu.h b/libopencm3/include/libopencm3/cm3/mpu.h
new file mode 100644
index 0000000..9efa83e
--- /dev/null
+++ b/libopencm3/include/libopencm3/cm3/mpu.h
@@ -0,0 +1,110 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2013 Frantisek Burian
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LIBOPENCM3_CM0_MPU_H
+#define LIBOPENCM3_CM0_MPU_H
+
+#ifndef CM0_PLUS
+#error "mpu is supported only on CM0+ architecture"
+#else
+
+#include
+#include
+
+/* --- SCB: Registers ------------------------------------------------------ */
+
+#define MPU_TYPE MMIO32(MPU_BASE + 0x00)
+#define MPU_CTRL MMIO32(MPU_BASE + 0x04)
+#define MPU_RNR MMIO32(MPU_BASE + 0x08)
+#define MPU_RBAR MMIO32(MPU_BASE + 0x0C)
+#define MPU_RASR MMIO32(MPU_BASE + 0x10)
+
+/* --- MPU values ---------------------------------------------------------- */
+
+/* --- MPU_TYPE values ----------------------------------------------------- */
+
+#define MPU_TYPE_IREGION_LSB 16
+#define MPU_TYPE_IREGION (0xFF << MPU_TYPE_IREGION_LSB)
+#define MPU_TYPE_DREGION_LSB 8
+#define MPU_TYPE_DREGION (0xFF << MPU_TYPE_DREGION_LSB)
+#define MPU_TYPE_SEPARATE (1<<0)
+
+/* --- MPU_CTRL values ----------------------------------------------------- */
+
+#define MPU_CTRL_PRIVDEFENA (1<<2)
+#define MPU_CTRL_HFNMIENA (1<<1)
+#define MPU_CTRL_ENABLE (1<<0)
+
+/* --- MPU_RNR values ------------------------------------------------------ */
+
+#define MPU_RNR_REGION_LSB 0
+#define MPU_RNR_REGION (0xFF << MPU_RNR_REGION_LSB)
+
+/* --- MPU_RBAR values ----------------------------------------------------- */
+
+#define MPU_RBAR_ADDR_LSB 8
+#define MPU_RBAR_ADDR (0x00FFFFFF << MPU_RBAR_REGION_LSB)
+#define MPU_RBAR_VALID (1<<4)
+#define MPU_RBAR_REGION_LSB 0
+#define MPU_RBAR_REGION (0xF << MPU_RBAR_REGION_LSB)
+
+/* --- MPU_RASR values ----------------------------------------------------- */
+
+#define MPU_RASR_ATTRS_LSB 16
+#define MPU_RASR_ATTRS (0xFFFF << MPU_RASR_ATTRS_LSB)
+#define MPU_RASR_SRD_LSB 8
+#define MPU_RASR_SRD (0xFF << MPU_RASR_SRD_LSB)
+#define MPU_RASR_SIZE_LSB 1
+#define MPU_RASR_SIZE (0x1F << MPU_RASR_SIZE_LSB)
+#define MPU_RASR_ENABLE (1 << 0)
+
+
+#define MPU_RASR_ATTR_XN (1 << 28)
+#define MPU_RASR_ATTR_AP (7 << 24)
+#define MPU_RASR_ATTR_AP_PNO_UNO (0 << 24)
+#define MPU_RASR_ATTR_AP_PRW_UNO (1 << 24)
+#define MPU_RASR_ATTR_AP_PRW_URO (2 << 24)
+#define MPU_RASR_ATTR_AP_PRW_URW (3 << 24)
+#define MPU_RASR_ATTR_AP_PRO_UNO (5 << 24)
+#define MPU_RASR_ATTR_AP_PRO_URO (6 << 24)
+#define MPU_RASR_ATTR_AP_PRO_URO (7 << 24)
+#define MPU_RASR_ATTR_TEX (7 << 19)
+#define MPU_RASR_ATTR_S (1 << 18)
+#define MPU_RASR_ATTR_C (1 << 17)
+#define MPU_RASR_ATTR_B (1 << 16)
+#define MPU_RASR_ATTR_SCB (7 << 16)
+#define MPU_RASR_ATTR_SCB_SH_STRONG (0 << 16)
+#define MPU_RASR_ATTR_SCB_SH_DEVICE (1 << 16)
+#define MPU_RASR_ATTR_SCB_NSH_WT (2 << 16)
+#define MPU_RASR_ATTR_SCB_NSH_WB (3 << 16)
+#define MPU_RASR_ATTR_SCB_SH_STRONG (4 << 16)
+#define MPU_RASR_ATTR_SCB_SH_DEVICE (5 << 16)
+#define MPU_RASR_ATTR_SCB_SH_WT (6 << 16)
+#define MPU_RASR_ATTR_SCB_SH_WB (7 << 16)
+
+/* --- MPU functions ------------------------------------------------------- */
+
+BEGIN_DECLS
+
+
+END_DECLS
+
+#endif /* CM0_PLUS */
+
+#endif
diff --git a/libopencm3/include/libopencm3/cm3/scb.h b/libopencm3/include/libopencm3/cm3/scb.h
new file mode 100644
index 0000000..0a6dcae
--- /dev/null
+++ b/libopencm3/include/libopencm3/cm3/scb.h
@@ -0,0 +1,444 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Piotr Esden-Tempski
+ * Copyright (C) 2010 Thomas Otto
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LIBOPENCM3_SCB_H
+#define LIBOPENCM3_SCB_H
+
+#include
+#include
+
+/* --- SCB: Registers ------------------------------------------------------ */
+
+/* CPUID: CPUID base register */
+#define SCB_CPUID MMIO32(SCB_BASE + 0x00)
+
+/* ICSR: Interrupt Control State Register */
+#define SCB_ICSR MMIO32(SCB_BASE + 0x04)
+
+/* VTOR: Vector Table Offset Register */
+#define SCB_VTOR MMIO32(SCB_BASE + 0x08)
+
+/* AIRCR: Application Interrupt and Reset Control Register */
+#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
+
+/* SCR: System Control Register */
+#define SCB_SCR MMIO32(SCB_BASE + 0x10)
+
+/* CCR: Configuration Control Register */
+#define SCB_CCR MMIO32(SCB_BASE + 0x14)
+
+/* SHP: System Handler Priority Registers */
+/* Note: 12 8bit registers */
+#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id)
+#define SCB_SHPR1 MMIO32(SCB_BASE + 0x18)
+#define SCB_SHPR2 MMIO32(SCB_BASE + 0x1C)
+#define SCB_SHPR3 MMIO32(SCB_BASE + 0x20)
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+/* SHCSR: System Handler Control and State Register */
+#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
+
+/* CFSR: Configurable Fault Status Registers */
+#define SCB_CFSR MMIO32(SCB_BASE + 0x28)
+
+/* HFSR: Hard Fault Status Register */
+#define SCB_HFSR MMIO32(SCB_BASE + 0x2C)
+
+/* DFSR: Debug Fault Status Register */
+#define SCB_DFSR MMIO32(SCB_BASE + 0x30)
+
+/* MMFAR: Memory Manage Fault Address Register */
+#define SCB_MMFAR MMIO32(SCB_BASE + 0x34)
+
+/* BFAR: Bus Fault Address Register */
+#define SCB_BFAR MMIO32(SCB_BASE + 0x38)
+
+/* AFSR: Auxiliary Fault Status Register */
+#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
+
+/* ID_PFR0: Processor Feature Register 0 */
+#define SCB_ID_PFR0 MMIO32(SCB_BASE + 0x40)
+
+/* ID_PFR1: Processor Feature Register 1 */
+#define SCB_ID_PFR1 MMIO32(SCB_BASE + 0x44)
+
+/* ID_DFR0: Debug Features Register 0 */
+#define SCB_ID_DFR0 MMIO32(SCB_BASE + 0x48)
+
+/* ID_AFR0: Auxiliary Features Register 0 */
+#define SCB_ID_AFR0 MMIO32(SCB_BASE + 0x4C)
+
+/* ID_MMFR0: Memory Model Feature Register 0 */
+#define SCB_ID_MMFR0 MMIO32(SCB_BASE + 0x50)
+
+/* ID_MMFR1: Memory Model Feature Register 1 */
+#define SCB_ID_MMFR1 MMIO32(SCB_BASE + 0x54)
+
+/* ID_MMFR2: Memory Model Feature Register 2 */
+#define SCB_ID_MMFR2 MMIO32(SCB_BASE + 0x58)
+
+/* ID_MMFR3: Memory Model Feature Register 3 */
+#define SCB_ID_MMFR3 MMIO32(SCB_BASE + 0x5C)
+
+/* ID_ISAR0: Instruction Set Attributes Register 0 */
+#define SCB_ID_ISAR0 MMIO32(SCB_BASE + 0x60)
+
+/* ID_ISAR1: Instruction Set Attributes Register 1 */
+#define SCB_ID_ISAR1 MMIO32(SCB_BASE + 0x64)
+
+/* ID_ISAR2: Instruction Set Attributes Register 2 */
+#define SCB_ID_ISAR2 MMIO32(SCB_BASE + 0x68)
+
+/* ID_ISAR3: Instruction Set Attributes Register 3 */
+#define SCB_ID_ISAR3 MMIO32(SCB_BASE + 0x6C)
+
+/* ID_ISAR4: Instruction Set Attributes Register 4 */
+#define SCB_ID_ISAR4 MMIO32(SCB_BASE + 0x70)
+
+/* CPACR: Coprocessor Access Control Register */
+#define SCB_CPACR MMIO32(SCB_BASE + 0x88)
+
+/* FPCCR: Floating-Point Context Control Register */
+#define SCB_FPCCR MMIO32(SCB_BASE + 0x234)
+
+/* FPCAR: Floating-Point Context Address Register */
+#define SCB_FPCAR MMIO32(SCB_BASE + 0x238)
+
+/* FPDSCR: Floating-Point Default Status Control Register */
+#define SCB_FPDSCR MMIO32(SCB_BASE + 0x23C)
+
+/* MVFR0: Media and Floating-Point Feature Register 0 */
+#define SCB_MVFR0 MMIO32(SCB_BASE + 0x240)
+
+/* MVFR1: Media and Floating-Point Feature Register 1 */
+#define SCB_MVFR1 MMIO32(SCB_BASE + 0x244)
+#endif
+
+/* --- SCB values ---------------------------------------------------------- */
+
+/* --- SCB_CPUID values ---------------------------------------------------- */
+
+/* Implementer[31:24]: Implementer code */
+#define SCB_CPUID_IMPLEMENTER_LSB 24
+#define SCB_CPUID_IMPLEMENTER (0xFF << SCB_CPUID_IMPLEMENTER_LSB)
+/* Variant[23:20]: Variant number */
+#define SCB_CPUID_VARIANT_LSB 20
+#define SCB_CPUID_VARIANT (0xF << SCB_CPUID_VARIANT_LSB)
+/* Constant[19:16]: Reads as 0xF (ARMv7-M) M3, M4 */
+/* Constant[19:16]: Reads as 0xC (ARMv6-M) M0, M0+ */
+#define SCB_CPUID_CONSTANT_LSB 16
+#define SCB_CPUID_CONSTANT (0xF << SCB_CPUID_CONSTANT_LSB)
+#define SCB_CPUID_CONSTANT_ARMV6 (0xC << SCB_CPUID_CONSTANT_LSB)
+#define SCB_CPUID_CONSTANT_ARMV7 (0xF << SCB_CPUID_CONSTANT_LSB)
+
+/* PartNo[15:4]: Part number of the processor */
+#define SCB_CPUID_PARTNO_LSB 4
+#define SCB_CPUID_PARTNO (0xFFF << SCB_CPUID_PARTNO_LSB)
+/* Revision[3:0]: Revision number */
+#define SCB_CPUID_REVISION_LSB 0
+#define SCB_CPUID_REVISION (0xF << SCB_CPUID_REVISION_LSB)
+
+/* --- SCB_ICSR values ----------------------------------------------------- */
+
+/* NMIPENDSET: NMI set-pending bit */
+#define SCB_ICSR_NMIPENDSET (1 << 31)
+/* Bits [30:29]: reserved - must be kept cleared */
+/* PENDSVSET: PendSV set-pending bit */
+#define SCB_ICSR_PENDSVSET (1 << 28)
+/* PENDSVCLR: PendSV clear-pending bit */
+#define SCB_ICSR_PENDSVCLR (1 << 27)
+/* PENDSTSET: SysTick exception set-pending bit */
+#define SCB_ICSR_PENDSTSET (1 << 26)
+/* PENDSTCLR: SysTick exception clear-pending bit */
+#define SCB_ICSR_PENDSTCLR (1 << 25)
+/* Bit 24: reserved - must be kept cleared */
+/* Bit 23: reserved for debug - reads as 0 when not in debug mode */
+#define SCB_ICSR_ISRPREEMPT (1 << 23)
+/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */
+#define SCB_ICSR_ISRPENDING (1 << 22)
+/* VECTPENDING[21:12] Pending vector */
+#define SCB_ICSR_VECTPENDING_LSB 12
+#define SCB_ICSR_VECTPENDING (0x1FF << SCB_ICSR_VECTPENDING_LSB)
+/* RETOBASE: Return to base level */
+#define SCB_ICSR_RETOBASE (1 << 11)
+/* Bits [10:9]: reserved - must be kept cleared */
+/* VECTACTIVE[8:0] Active vector */
+#define SCB_ICSR_VECTACTIVE_LSB 0
+#define SCB_ICSR_VECTACTIVE (0x1FF << SCB_ICSR_VECTACTIVE_LSB)
+
+
+/* --- SCB_VTOR values ----------------------------------------------------- */
+
+/* IMPLEMENTATION DEFINED */
+
+#if defined(__ARM_ARCH_6M__)
+
+#define SCB_VTOR_TBLOFF_LSB 7
+#define SCB_VTOR_TBLOFF (0x1FFFFFF << SCB_VTOR_TBLOFF_LSB)
+
+#elif defined(CM1)
+/* VTOR not defined there */
+
+#elif defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+
+/* Bits [31:30]: reserved - must be kept cleared */
+/* TBLOFF[29:9]: Vector table base offset field */
+/* inconsistent datasheet - LSB could be 11 */
+/* BUG: TBLOFF is in the ARMv6 Architecture reference manual defined from b7 */
+#define SCB_VTOR_TBLOFF_LSB 9
+#define SCB_VTOR_TBLOFF (0x7FFFFF << SCB_VTOR_TBLOFF_LSB)
+
+#endif
+
+/* --- SCB_AIRCR values ---------------------------------------------------- */
+
+/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */
+#define SCB_AIRCR_VECTKEYSTAT_LSB 16
+#define SCB_AIRCR_VECTKEYSTAT (0xFFFF << SCB_AIRCR_VECTKEYSTAT_LSB)
+#define SCB_AIRCR_VECTKEY (0x05FA << SCB_AIRCR_VECTKEYSTAT_LSB)
+
+/* ENDIANESS Data endianness bit */
+#define SCB_AIRCR_ENDIANESS (1 << 15)
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+/* Bits [14:11]: reserved - must be kept cleared */
+/* PRIGROUP[10:8]: Interrupt priority grouping field */
+#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8)
+#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8)
+#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8)
+#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8)
+#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8)
+#define SCB_AIRCR_PRIGROUP_MASK (0x7 << 8)
+#define SCB_AIRCR_PRIGROUP_SHIFT 8
+/* Bits [7:3]: reserved - must be kept cleared */
+#endif
+
+/* SYSRESETREQ System reset request */
+#define SCB_AIRCR_SYSRESETREQ (1 << 2)
+/* VECTCLRACTIVE */
+#define SCB_AIRCR_VECTCLRACTIVE (1 << 1)
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+/* VECTRESET */
+#define SCB_AIRCR_VECTRESET (1 << 0)
+#endif
+
+/* --- SCB_SCR values ------------------------------------------------------ */
+
+/* Bits [31:5]: reserved - must be kept cleared */
+/* SEVEONPEND Send Event on Pending bit */
+#define SCB_SCR_SEVEONPEND (1 << 4)
+/* Bit 3: reserved - must be kept cleared */
+/* SLEEPDEEP */
+#define SCB_SCR_SLEEPDEEP (1 << 2)
+/* SLEEPONEXIT */
+#define SCB_SCR_SLEEPONEXIT (1 << 1)
+/* Bit 0: reserved - must be kept cleared */
+
+/* --- SCB_CCR values ------------------------------------------------------ */
+
+/* Bits [31:10]: reserved - must be kept cleared */
+/* STKALIGN */
+#define SCB_CCR_STKALIGN (1 << 9)
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+/* BFHFNMIGN */
+#define SCB_CCR_BFHFNMIGN (1 << 8)
+/* Bits [7:5]: reserved - must be kept cleared */
+/* DIV_0_TRP */
+#define SCB_CCR_DIV_0_TRP (1 << 4)
+#endif
+
+/* UNALIGN_TRP */
+#define SCB_CCR_UNALIGN_TRP (1 << 3)
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+/* Bit 2: reserved - must be kept cleared */
+/* USERSETMPEND */
+#define SCB_CCR_USERSETMPEND (1 << 1)
+/* NONBASETHRDENA */
+#define SCB_CCR_NONBASETHRDENA (1 << 0)
+#endif
+
+/* These numbers are designed to be used with the SCB_SHPR() macro */
+/* SCB_SHPR1 */
+#define SCB_SHPR_PRI_4_MEMMANAGE 0
+#define SCB_SHPR_PRI_5_BUSFAULT 1
+#define SCB_SHPR_PRI_6_USAGEFAULT 2
+#define SCB_SHPR_PRI_7_RESERVED 3
+/* SCB_SHPR2 */
+#define SCB_SHPR_PRI_8_RESERVED 4
+#define SCB_SHPR_PRI_9_RESERVED 5
+#define SCB_SHPR_PRI_10_RESERVED 6
+#define SCB_SHPR_PRI_11_SVCALL 7
+/* SCB_SHPR3 */
+#define SCB_SHPR_PRI_12_RESERVED 8
+#define SCB_SHPR_PRI_13_RESERVED 9
+#define SCB_SHPR_PRI_14_PENDSV 10
+#define SCB_SHPR_PRI_15_SYSTICK 11
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+/* --- SCB_SHCSR values ---------------------------------------------------- */
+
+/* Bits [31:19]: reserved - must be kept cleared */
+/* USGFAULTENA: Usage fault enable */
+#define SCB_SHCSR_USGFAULTENA (1 << 18)
+/* BUSFAULTENA: Bus fault enable */
+#define SCB_SHCSR_BUSFAULTENA (1 << 17)
+/* MEMFAULTENA: Memory management fault enable */
+#define SCB_SHCSR_MEMFAULTENA (1 << 16)
+/* SVCALLPENDED: SVC call pending */
+#define SCB_SHCSR_SVCALLPENDED (1 << 15)
+/* BUSFAULTPENDED: Bus fault exception pending */
+#define SCB_SHCSR_BUSFAULTPENDED (1 << 14)
+/* MEMFAULTPENDED: Memory management fault exception pending */
+#define SCB_SHCSR_MEMFAULTPENDED (1 << 13)
+/* USGFAULTPENDED: Usage fault exception pending */
+#define SCB_SHCSR_USGFAULTPENDED (1 << 12)
+/* SYSTICKACT: SysTick exception active */
+#define SCB_SHCSR_SYSTICKACT (1 << 11)
+/* PENDSVACT: PendSV exception active */
+#define SCB_SHCSR_PENDSVACT (1 << 10)
+/* Bit 9: reserved - must be kept cleared */
+/* MONITORACT: Debug monitor active */
+#define SCB_SHCSR_MONITORACT (1 << 8)
+/* SVCALLACT: SVC call active */
+#define SCB_SHCSR_SVCALLACT (1 << 7)
+/* Bits [6:4]: reserved - must be kept cleared */
+/* USGFAULTACT: Usage fault exception active */
+#define SCB_SHCSR_USGFAULTACT (1 << 3)
+/* Bit 2: reserved - must be kept cleared */
+/* BUSFAULTACT: Bus fault exception active */
+#define SCB_SHCSR_BUSFAULTACT (1 << 1)
+/* MEMFAULTACT: Memory management fault exception active */
+#define SCB_SHCSR_MEMFAULTACT (1 << 0)
+
+/* --- SCB_CFSR values ----------------------------------------------------- */
+
+/* Bits [31:26]: reserved - must be kept cleared */
+/* DIVBYZERO: Divide by zero usage fault */
+#define SCB_CFSR_DIVBYZERO (1 << 25)
+/* UNALIGNED: Unaligned access usage fault */
+#define SCB_CFSR_UNALIGNED (1 << 24)
+/* Bits [23:20]: reserved - must be kept cleared */
+/* NOCP: No coprocessor usage fault */
+#define SCB_CFSR_NOCP (1 << 19)
+/* INVPC: Invalid PC load usage fault */
+#define SCB_CFSR_INVPC (1 << 18)
+/* INVSTATE: Invalid state usage fault */
+#define SCB_CFSR_INVSTATE (1 << 17)
+/* UNDEFINSTR: Undefined instruction usage fault */
+#define SCB_CFSR_UNDEFINSTR (1 << 16)
+/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */
+#define SCB_CFSR_BFARVALID (1 << 15)
+/* Bits [14:13]: reserved - must be kept cleared */
+/* STKERR: Bus fault on stacking for exception entry */
+#define SCB_CFSR_STKERR (1 << 12)
+/* UNSTKERR: Bus fault on unstacking for a return from exception */
+#define SCB_CFSR_UNSTKERR (1 << 11)
+/* IMPRECISERR: Imprecise data bus error */
+#define SCB_CFSR_IMPRECISERR (1 << 10)
+/* PRECISERR: Precise data bus error */
+#define SCB_CFSR_PRECISERR (1 << 9)
+/* IBUSERR: Instruction bus error */
+#define SCB_CFSR_IBUSERR (1 << 8)
+/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */
+#define SCB_CFSR_MMARVALID (1 << 7)
+/* Bits [6:5]: reserved - must be kept cleared */
+/* MSTKERR: Memory manager fault on stacking for exception entry */
+#define SCB_CFSR_MSTKERR (1 << 4)
+/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */
+#define SCB_CFSR_MUNSTKERR (1 << 3)
+/* Bit 2: reserved - must be kept cleared */
+/* DACCVIOL: Data access violation flag */
+#define SCB_CFSR_DACCVIOL (1 << 1)
+/* IACCVIOL: Instruction access violation flag */
+#define SCB_CFSR_IACCVIOL (1 << 0)
+
+/* --- SCB_HFSR values ----------------------------------------------------- */
+
+/* DEBUG_VT: reserved for debug use */
+#define SCB_HFSR_DEBUG_VT (1 << 31)
+/* FORCED: Forced hard fault */
+#define SCB_HFSR_FORCED (1 << 30)
+/* Bits [29:2]: reserved - must be kept cleared */
+/* VECTTBL: Vector table hard fault */
+#define SCB_HFSR_VECTTBL (1 << 1)
+/* Bit 0: reserved - must be kept cleared */
+
+/* --- SCB_MMFAR values ---------------------------------------------------- */
+
+/* MMFAR [31:0]: Memory management fault address */
+
+/* --- SCB_BFAR values ----------------------------------------------------- */
+
+/* BFAR [31:0]: Bus fault address */
+
+/* --- SCB_CPACR values ---------------------------------------------------- */
+
+/* CPACR CPn: Access privileges values */
+#define SCB_CPACR_NONE 0 /* Access denied */
+#define SCB_CPACR_PRIV 1 /* Privileged access only */
+#define SCB_CPACR_FULL 3 /* Full access */
+
+/* CPACR [20:21]: Access privileges for coprocessor 10 */
+#define SCB_CPACR_CP10 (1 << 20)
+/* CPACR [22:23]: Access privileges for coprocessor 11 */
+#define SCB_CPACR_CP11 (1 << 22)
+#endif
+
+/* --- SCB functions ------------------------------------------------------- */
+
+BEGIN_DECLS
+
+struct scb_exception_stack_frame {
+ uint32_t r0;
+ uint32_t r1;
+ uint32_t r2;
+ uint32_t r3;
+ uint32_t r12;
+ uint32_t lr;
+ uint32_t pc;
+ uint32_t xpsr;
+} __attribute__((packed));
+
+#define SCB_GET_EXCEPTION_STACK_FRAME(f) \
+ do { \
+ asm volatile ("mov %[frameptr], sp" \
+ : [frameptr]"=r" (f)); \
+ } while (0)
+
+void scb_reset_system(void) __attribute__((noreturn, naked));
+
+/* Those defined only on ARMv7 and above */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+void scb_reset_core(void) __attribute__((noreturn, naked));
+void scb_set_priority_grouping(uint32_t prigroup);
+#endif
+
+END_DECLS
+
+#endif
diff --git a/libopencm3/include/libopencm3/cm3/scs.h b/libopencm3/include/libopencm3/cm3/scs.h
new file mode 100644
index 0000000..7bf9860
--- /dev/null
+++ b/libopencm3/include/libopencm3/cm3/scs.h
@@ -0,0 +1,350 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Gareth McMullin
+ * Copyright (C) 2012 Benjamin Vernoux
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LIBOPENCM3_CM3_SCS_H
+#define LIBOPENCM3_CM3_SCS_H
+
+/*
+ * All the definition hereafter are generic for CortexMx ARMv7-M
+ * See ARM document "ARMv7-M Architecture Reference Manual" for more details.
+ * See also ARM document "ARM Compiler toolchain Developing Software for ARM
+ * Processors" for details on System Timer/SysTick.
+ */
+
+/*
+ * The System Control Space (SCS) is a memory-mapped 4KB address space that
+ * provides 32-bit registers for configuration, status reporting and control.
+ * The SCS registers divide into the following groups:
+ * - system control and identification
+ * - the CPUID processor identification space
+ * - system configuration and status
+ * - fault reporting
+ * - a system timer, SysTick
+ * - a Nested Vectored Interrupt Controller (NVIC)
+ * - a Protected Memory System Architecture (PMSA)
+ * - system debug.
+ */
+
+/* System Handler Priority 8 bits Registers, SHPR1/2/3 */
+/* Note: 12 8bit Registers */
+#define SCS_SHPR(ipr_id) MMIO8(SCS_BASE + 0xD18 + ipr_id)
+
+/*
+ * Debug Halting Control and Status Register (DHCSR).
+ *
+ * Purpose Controls halting debug.
+ * Usage constraints: The effect of modifying the C_STEP or C_MASKINTS bit when
+ * the system is running with halting debug enabled is UNPREDICTABLE.
+ * Halting debug is enabled when C_DEBUGEN is set to 1. The system is running
+ * when S_HALT is set to 0.
+ * - When C_DEBUGEN is set to 0, the processor ignores the values of all other
+ * bits in this register.
+ * - For more information about the use of DHCSR see Debug stepping on page
+ * C1-824.
+ * Configurations Always implemented.
+ */
+/* SCS_DHCSR register */
+#define SCS_DHCSR MMIO32(SCS_BASE + 0xDF0)
+/*
+ * Debug Core Register Selector Register (DCRSR).
+ *
+ * Purpose With the DCRDR, the DCRSR provides debug access to the ARM core
+ * registers, special-purpose registers, and Floating-point extension
+ * registers. A write to DCRSR specifies the register to transfer, whether the
+ * transfer is a read or a write, and starts the transfer.
+ * Usage constraints: Only accessible in Debug state.
+ * Configurations Always implemented.
+ *
+ */
+/* SCS_DCRS register */
+#define SCS_DCRSR MMIO32(SCS_BASE + 0xDF4)
+/*
+ * Debug Core Register Data Register (DCRDR)
+ *
+ * Purpose With the DCRSR, see Debug Core Register Selector Register, the DCRDR
+ * provides debug access to the ARM core registers, special-purpose registers,
+ * and Floating-point extension registers. The DCRDR is the data register for
+ * these accesses.
+ * - Used on its own, the DCRDR provides a message passing resource between an
+ * external debugger and a debug agent running on the processor.
+ * Note:
+ * The architecture does not define any handshaking mechanism for this use of
+ * DCRDR.
+ * Usage constraints: See Use of DCRSR and DCRDR for constraints that apply to
+ * particular transfers using the DCRSR and DCRDR.
+ * Configurations Always implemented.
+ *
+ */
+/* SCS_DCRDR register */
+#define SCS_DCRDR MMIO32(SCS_BASE + 0xDF8)
+/*
+ * Debug Exception and Monitor Control Register (DEMCR).
+ *
+ * Purpose Manages vector catch behavior and DebugMonitor handling when
+ * debugging.
+ * Usage constraints:
+ * - Bits [23:16] provide DebugMonitor exception control.
+ * - Bits [15:0] provide Debug state, halting debug, control.
+ * Configurations Always implemented.
+ *
+ */
+/* SCS_DEMCR register */
+#define SCS_DEMCR MMIO32(SCS_BASE + 0xDFC)
+
+/* Debug Halting Control and Status Register (DHCSR) */
+#define SCS_DHCSR_DBGKEY 0xA05F0000
+#define SCS_DHCSR_C_DEBUGEN 0x00000001
+#define SCS_DHCSR_C_HALT 0x00000002
+#define SCS_DHCSR_C_STEP 0x00000004
+#define SCS_DHCSR_C_MASKINTS 0x00000008
+#define SCS_DHCSR_C_SNAPSTALL 0x00000020
+#define SCS_DHCSR_S_REGRDY 0x00010000
+#define SCS_DHCSR_S_HALT 0x00020000
+#define SCS_DHCSR_S_SLEEP 0x00040000
+#define SCS_DHCSR_S_LOCKUP 0x00080000
+#define SCS_DHCSR_S_RETIRE_ST 0x01000000
+#define SCS_DHCSR_S_RESET_ST 0x02000000
+
+/* Debug Core Register Selector Register (DCRSR) */
+#define SCS_DCRSR_REGSEL_MASK 0x0000001F
+#define SCS_DCRSR_REGSEL_XPSR 0x00000010
+#define SCS_DCRSR_REGSEL_MSP 0x00000011
+#define SCS_DCRSR_REGSEL_PSP 0x00000012
+
+/* Debug Exception and Monitor Control Register (DEMCR) */
+/* Bits 31:25 - Reserved */
+#define SCS_DEMCR_TRCENA (1 << 24)
+/* Bits 23:20 - Reserved */
+#define SCS_DEMCR_MON_REQ (1 << 19)
+#define SCS_DEMCR_MON_STEP (1 << 18)
+#define SCS_DEMCR_VC_MON_PEND (1 << 17)
+#define SCS_DEMCR_VC_MON_EN (1 << 16)
+/* Bits 15:11 - Reserved */
+#define SCS_DEMCR_VC_HARDERR (1 << 10)
+#define SCS_DEMCR_VC_INTERR (1 << 9)
+#define SCS_DEMCR_VC_BUSERR (1 << 8)
+#define SCS_DEMCR_VC_STATERR (1 << 7)
+#define SCS_DEMCR_VC_CHKERR (1 << 6)
+#define SCS_DEMCR_VC_NOCPERR (1 << 5)
+#define SCS_DEMCR_VC_MMERR (1 << 4)
+/* Bits 3:1 - Reserved */
+#define SCS_DEMCR_VC_CORERESET (1 << 0)
+
+/*
+ * System Control Space (SCS) => System timer register support in the SCS.
+ * To configure SysTick, load the interval required between SysTick events to
+ * the SysTick Reload Value register. The timer interrupt, or COUNTFLAG bit in
+ * the SysTick Control and Status register, is activated on the transition from
+ * 1 to 0, therefore it activates every n+1 clock ticks. If you require a
+ * period of 100, write 99 to the SysTick Reload Value register. The SysTick
+ * Reload Value register supports values between 0x1 and 0x00FFFFFF.
+ *
+ * If you want to use SysTick to generate an event at a timed interval, for
+ * example 1ms, you can use the SysTick Calibration Value Register to scale
+ * your value for the Reload register. The SysTick Calibration Value Register
+ * is a read-only register that contains the number of pulses for a period of
+ * 10ms, in the TENMS field, bits[23:0].
+ *
+ * This register also has a SKEW bit. Bit[30] == 1 indicates that the
+ * calibration for 10ms in the TENMS section is not exactly 10ms due to clock
+ * frequency. Bit[31] == 1 indicates that the reference clock is not provided.
+ */
+/*
+ * SysTick Control and Status Register (CSR).
+ * Purpose Controls the system timer and provides status data.
+ * Usage constraints: There are no usage constraints.
+ * Configurations Always implemented.
+*/
+#define SCS_SYST_CSR MMIO32(SCS_BASE + 0x10)
+
+/* SysTick Reload Value Register (CVR).
+ * Purpose Reads or clears the current counter value.
+ * Usage constraints:
+ * - Any write to the register clears the register to zero.
+ * - The counter does not provide read-modify-write protection.
+ * - Unsupported bits are read as zero
+ * Configurations Always implemented.
+ */
+#define CM_SCS_SYST_RVR MMIO32(SCS_BASE + 0x14)
+
+/* SysTick Current Value Register (RVR).
+ * Purpose Holds the reload value of the SYST_CVR.
+ * Usage constraints There are no usage constraints.
+ * Configurations Always implemented.
+ */
+#define CM_SCS_SYST_CVR MMIO32(SCS_BASE + 0x18)
+
+/*
+ * SysTick Calibration value Register(Read Only) (CALIB)
+ * Purpose Reads the calibration value and parameters for SysTick.
+ * Usage constraints: There are no usage constraints.
+ * Configurations Always implemented.
+ */
+#define CM_SCS_SYST_CALIB MMIO32(SCS_BASE + 0x1C)
+
+/* --- SCS_SYST_CSR values ----------------------------------------------- */
+/* Counter is operating. */
+#define SCS_SYST_CSR_ENABLE (BIT0)
+/* Count to 0 changes the SysTick exception status to pending. */
+#define SCS_SYST_CSR_TICKINT (BIT1)
+/* SysTick uses the processor clock. */
+#define SCS_SYST_CSR_CLKSOURCE (BIT2)
+/*
+ * Indicates whether the counter has counted to 0 since the last read of this
+ * register:
+ * 0 = Timer has not counted to 0
+ * 1 = Timer has counted to 0.
+ */
+#define SCS_SYST_CSR_COUNTFLAG (BIT16)
+
+/* --- CM_SCS_SYST_RVR values ---------------------------------------------- */
+/* Bit 0 to 23 => RELOAD The value to load into the SYST_CVR when the counter
+ * reaches 0.
+ */
+/* Bit 24 to 31 are Reserved */
+
+/* --- CM_SCS_SYST_CVR values ---------------------------------------------- */
+/* Bit0 to 31 => Reads or clears the current counter value. */
+
+/* --- CM_SCS_SYST_CALIB values -------------------------------------------- */
+/*
+ * Bit0 to 23 => TENMS Optionally, holds a reload value to be used for 10ms
+ * (100Hz) timing, subject to system clock skew errors. If this field is zero,
+ * the calibration value is not known.
+ */
+#define SCS_SYST_SYST_CALIB_TENMS_MASK (BIT24-1)
+
+/*
+ * Bit30 => SKEW Indicates whether the 10ms calibration value is exact:
+ * 0 = 10ms calibration value is exact.
+ * 1 = 10ms calibration value is inexact, because of the clock frequency
+ */
+#define SCS_SYST_SYST_CALIB_VALUE_INEXACT (BIT30)
+/*
+ * Bit31 => NOREF Indicates whether the IMPLEMENTATION DEFINED reference clock
+ * is implemented:
+ * 0 = The reference clock is implemented.
+ * 1 = The reference clock is not implemented.
+ * When this bit is 1, the CLKSOURCE bit of the SYST_CSR register is forced to
+ * 1 and cannot be cleared to 0.
+ */
+#define SCS_SYST_SYST_CALIB_REF_NOT_IMPLEMENTED (BIT31)
+
+/*
+ * System Control Space (SCS) => Data Watchpoint and Trace (DWT).
+ * See "ARMv7-M Architecture Reference Manual"
+ * (https://github.com/libopencm3/libopencm3-archive/blob/master/arm/
+ * ARMv7-M_ARM.pdf)
+ * The DWT is an optional debug unit that provides watchpoints, data tracing,
+ * and system profiling for the processor.
+ */
+/*
+ * DWT Control register
+ * Purpose Provides configuration and status information for the DWT block, and
+ * used to control features of the block
+ * Usage constraints: There are no usage constraints.
+ * Configurations Always implemented.
+ */
+#define SCS_DWT_CTRL MMIO32(DWT_BASE + 0x00)
+/*
+ * DWT_CYCCNT register
+ * Cycle Count Register (Shows or sets the value of the processor cycle
+ * counter, CYCCNT)
+ * When enabled, CYCCNT increments on each processor clock cycle. On overflow,
+ * CYCCNT wraps to zero.
+ *
+ * Purpose Shows or sets the value of the processor cycle counter, CYCCNT.
+ * Usage constraints: The DWT unit suspends CYCCNT counting when the processor
+ * is in Debug state.
+ * Configurations Implemented: only when DWT_CTRL.NOCYCCNT is RAZ, see Control
+ * register, DWT_CTRL.
+ * When DWT_CTRL.NOCYCCNT is RAO no cycle counter is implemented and this
+ * register is UNK/SBZP.
+*/
+#define SCS_DWT_CYCCNT MMIO32(DWT_BASE + 0x04)
+
+/* DWT_CPICNT register
+ * Purpose Counts additional cycles required to execute multi-cycle
+ * instructions and instruction fetch stalls.
+ * Usage constraints: The counter initializes to 0 when software enables its
+ * counter overflow event by
+ * setting the DWT_CTRL.CPIEVTENA bit to 1.
+ * Configurations Implemented: only when DWT_CTRL.NOPRFCNT is RAZ, see Control
+ * register, DWT_CTRL.
+ * If DWT_CTRL.NOPRFCNT is RAO, indicating that the implementation does not
+ * include the profiling counters, this register is UNK/SBZP.
+ */
+#define SCS_DWT_CPICNT MMIO32(DWT_BASE + 0x08)
+
+/* DWT_EXCCNT register */
+#define SCS_DWT_EXCCNT MMIO32(DWT_BASE + 0x0C)
+
+/* DWT_EXCCNT register */
+#define SCS_DWT_SLEEPCNT MMIO32(DWT_BASE + 0x10)
+
+/* DWT_EXCCNT register */
+#define SCS_DWT_LSUCNT MMIO32(DWT_BASE + 0x14)
+
+/* DWT_EXCCNT register */
+#define SCS_DWT_FOLDCNT MMIO32(DWT_BASE + 0x18)
+
+/* DWT_PCSR register */
+#define SCS_DWT_PCSR MMIO32(DWT_BASE + 0x18)
+
+/* CoreSight Lock Status Register for this peripheral */
+#define SCS_DWT_LSR MMIO32(SCS_DWT_BASE + 0xFB4)
+/* CoreSight Lock Access Register for this peripheral */
+#define SCS_DWT_LAR MMIO32(SCS_DWT_BASE + 0xFB0)
+
+/* --- SCS_DWT_CTRL values ------------------------------------------------- */
+/*
+ * Enables CYCCNT:
+ * 0 = Disabled, 1 = Enabled
+ * This bit is UNK/SBZP if the NOCYCCNT bit is RAO.
+ */
+#define SCS_DWT_CTRL_CYCCNTENA (BIT0)
+
+/* CoreSight Lock Status Register lock status bit */
+#define SCS_LSR_SLK (1<<1)
+/* CoreSight Lock Status Register lock availability bit */
+#define SCS_LSR_SLI (1<<0)
+/* CoreSight Lock Access key, common for all */
+#define SCS_LAR_KEY 0xC5ACCE55
+
+/* TODO bit definition values for other DWT_XXX register */
+
+/* Macro to be called at startup to enable SCS & Cycle Counter */
+#define SCS_DWT_CYCLE_COUNTER_ENABLED() ((SCS_DEMCR |= SCS_DEMCR_TRCENA)\
+ (SCS_DWT_CTRL |= SCS_DWT_CTRL_CYCCNTENA))
+
+#define SCS_SYSTICK_DISABLED() (SCS_SYST_CSR = 0)
+
+/* Macro to be called at startup to Enable CortexMx SysTick (but IRQ not
+ * enabled)
+ */
+#define SCS_SYSTICK_ENABLED() (SCS_SYST_CSR = (SCS_SYST_CSR_ENABLE | \
+ SCS_SYST_CSR_CLKSOURCE))
+
+/* Macro to be called at startup to Enable CortexMx SysTick and IRQ */
+#define SCS_SYSTICK_AND_IRQ_ENABLED() (SCS_SYST_CSR = (SCS_SYST_CSR_ENABLE | \
+ SCS_SYST_CSR_CLKSOURCE | \
+ SCS_SYST_CSR_TICKINT))
+
+#endif
diff --git a/libopencm3/include/libopencm3/cm3/sync.h b/libopencm3/include/libopencm3/cm3/sync.h
new file mode 100644
index 0000000..e80e348
--- /dev/null
+++ b/libopencm3/include/libopencm3/cm3/sync.h
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Fergus Noble
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LIBOPENCM3_CM3_SYNC_H
+#define LIBOPENCM3_CM3_SYNC_H
+
+#include "common.h"
+
+void __dmb(void);
+
+/* Implements synchronisation primitives as discussed in the ARM document
+ * DHT0008A (ID081709) "ARM Synchronization Primitives" and the ARM v7-M
+ * Architecture Reference Manual.
+*/
+
+/* --- Exclusive load and store instructions ------------------------------- */
+
+/* Those are defined only on CM3 or CM4 */
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
+
+uint32_t __ldrex(volatile uint32_t *addr);
+uint32_t __strex(uint32_t val, volatile uint32_t *addr);
+
+/* --- Convenience functions ----------------------------------------------- */
+
+/* Here we implement some simple synchronisation primitives. */
+
+typedef uint32_t mutex_t;
+
+#define MUTEX_UNLOCKED 0
+#define MUTEX_LOCKED 1
+
+void mutex_lock(mutex_t *m);
+void mutex_unlock(mutex_t *m);
+
+#endif
+
+#endif
diff --git a/libopencm3/include/libopencm3/cm3/systick.h b/libopencm3/include/libopencm3/cm3/systick.h
new file mode 100644
index 0000000..a355b0f
--- /dev/null
+++ b/libopencm3/include/libopencm3/cm3/systick.h
@@ -0,0 +1,134 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Thomas Otto
+ * Copyright (C) 2012 Benjamin Vernoux
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+/** @defgroup CM3_systick_defines SysTick Defines
+ *
+ * @brief libopencm3 Defined Constants and Types for the Cortex SysTick
+ *
+ * @ingroup CM3_defines
+ *
+ * @version 1.0.0
+ *
+ * @author @htmlonly © @endhtmlonly 2010 Thomas Otto
+ *
+ * @date 19 August 2012
+ *
+ * LGPL License Terms @ref lgpl_license
+ */
+
+/**
+ * @note this file has been not following the register naming scheme, the
+ * correct names defined, and the old ones stay there for compatibility with
+ * old software (will be deprecated in the future)
+ */
+
+/**@{*/
+
+#ifndef LIBOPENCM3_SYSTICK_H
+#define LIBOPENCM3_SYSTICK_H
+
+#include
+#include
+
+/* --- SYSTICK registers --------------------------------------------------- */
+
+/* Control and status register (STK_CTRL) */
+#define STK_CSR MMIO32(SYS_TICK_BASE + 0x00)
+
+/* reload value register (STK_LOAD) */
+#define STK_RVR MMIO32(SYS_TICK_BASE + 0x04)
+
+/* current value register (STK_VAL) */
+#define STK_CVR MMIO32(SYS_TICK_BASE + 0x08)
+
+/* calibration value register (STK_CALIB) */
+#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C)
+
+/* --- STK_CSR values ------------------------------------------------------ */
+/* Bits [31:17] Reserved, must be kept cleared. */
+/* COUNTFLAG: */
+#define STK_CSR_COUNTFLAG (1 << 16)
+
+/* Bits [15:3] Reserved, must be kept cleared. */
+/* CLKSOURCE: Clock source selection */
+#define STK_CSR_CLKSOURCE_LSB 2
+#define STK_CSR_CLKSOURCE (1 << STK_CSR_CLKSOURCE_LSB)
+
+/** @defgroup systick_clksource Clock source selection
+@ingroup CM3_systick_defines
+
+@{*/
+#if defined(__ARM_ARCH_6M__)
+#define STK_CSR_CLKSOURCE_EXT (0 << STK_CSR_CLKSOURCE_LSB)
+#define STK_CSR_CLKSOURCE_AHB (1 << STK_CSR_CLKSOURCE_LSB)
+#else
+#define STK_CSR_CLKSOURCE_AHB_DIV8 (0 << STK_CSR_CLKSOURCE_LSB)
+#define STK_CSR_CLKSOURCE_AHB (1 << STK_CSR_CLKSOURCE_LSB)
+#endif
+/**@}*/
+
+/* TICKINT: SysTick exception request enable */
+#define STK_CSR_TICKINT (1 << 1)
+/* ENABLE: Counter enable */
+#define STK_CSR_ENABLE (1 << 0)
+
+/* --- STK_RVR values ------------------------------------------------------ */
+/* Bits [31:24] Reserved, must be kept cleared. */
+/* RELOAD[23:0]: RELOAD value */
+#define STK_RVR_RELOAD 0x00FFFFFF
+
+
+/* --- STK_CVR values ------------------------------------------------------ */
+/* Bits [31:24] Reserved, must be kept cleared. */
+/* CURRENT[23:0]: Current counter value */
+#define STK_CVR_CURRENT 0x00FFFFFF
+
+
+/* --- STK_CALIB values ---------------------------------------------------- */
+/* NOREF: NOREF flag */
+#define STK_CALIB_NOREF (1 << 31)
+/* SKEW: SKEW flag */
+#define STK_CALIB_SKEW (1 << 30)
+/* Bits [29:24] Reserved, must be kept cleared. */
+/* TENMS[23:0]: Calibration value */
+#define STK_CALIB_TENMS 0x00FFFFFF
+
+/* --- Function Prototypes ------------------------------------------------- */
+
+BEGIN_DECLS
+
+void systick_set_reload(uint32_t value);
+bool systick_set_frequency(uint32_t freq, uint32_t ahb);
+uint32_t systick_get_reload(void);
+uint32_t systick_get_value(void);
+void systick_set_clocksource(uint8_t clocksource);
+void systick_interrupt_enable(void);
+void systick_interrupt_disable(void);
+void systick_counter_enable(void);
+void systick_counter_disable(void);
+uint8_t systick_get_countflag(void);
+void systick_clear(void);
+
+uint32_t systick_get_calib(void);
+
+END_DECLS
+
+#endif
+/**@}*/
+
diff --git a/libopencm3/include/libopencm3/cm3/tpiu.h b/libopencm3/include/libopencm3/cm3/tpiu.h
new file mode 100644
index 0000000..ff21511
--- /dev/null
+++ b/libopencm3/include/libopencm3/cm3/tpiu.h
@@ -0,0 +1,97 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Gareth McMullin
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LIBOPENCM3_CM3_TPIU_H
+#define LIBOPENCM3_CM3_TPIU_H
+
+/* Cortex-M3 Trace Port Interface Unit (TPIU) */
+
+/* Those defined only on ARMv7 and above */
+#if !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__)
+#error "Trace Port Interface Unit not available in CM0"
+#endif
+
+/* --- TPIU registers ------------------------------------------------------ */
+
+/* Supported Synchronous Port Size (TPIU_SSPSR) */
+#define TPIU_SSPSR MMIO32(TPIU_BASE + 0x000)
+
+/* Current Synchronous Port Size (TPIU_CSPSR) */
+#define TPIU_CSPSR MMIO32(TPIU_BASE + 0x004)
+
+/* Asynchronous Clock Prescaler (TPIU_ACPR) */
+#define TPIU_ACPR MMIO32(TPIU_BASE + 0x010)
+
+/* Selected Pin Protocol (TPIU_SPPR) */
+#define TPIU_SPPR MMIO32(TPIU_BASE + 0x0F0)
+
+/* Formatter and Flush Status Register (TPIU_FFSR) */
+#define TPIU_FFSR MMIO32(TPIU_BASE + 0x300)
+
+/* Formatter and Flush Control Register (TPIU_FFCR) */
+#define TPIU_FFCR MMIO32(TPIU_BASE + 0x304)
+
+/* (TPIU_DEVID) */
+#define TPIU_DEVID MMIO32(TPIU_BASE + 0xFC8)
+
+/* CoreSight Lock Status Register for this peripheral */
+#define TPIU_LSR MMIO32(TPIU_BASE + 0xFB4)
+/* CoreSight Lock Access Register for this peripheral */
+#define TPIU_LAR MMIO32(TPIU_BASE + 0xFB0)
+
+/* TODO: PID, CID */
+
+/* --- TPIU_ACPR values ---------------------------------------------------- */
+
+/* Bits 31:16 - Reserved */
+/* Bits 15:0 - SWO output clock = Asynchronous_Reference_Clock/(value +1) */
+
+/* --- TPIU_SPPR values ---------------------------------------------------- */
+
+/* Bits 31:2 - Reserved */
+#define TPIU_SPPR_SYNC (0x0)
+#define TPIU_SPPR_ASYNC_MANCHESTER (0x1)
+#define TPIU_SPPR_ASYNC_NRZ (0x2)
+
+/* --- TPIU_FFSR values ---------------------------------------------------- */
+
+/* Bits 31:4 - Reserved */
+#define TPIU_FFSR_FTNONSTOP (1 << 3)
+#define TPIU_FFSR_TCPRESENT (1 << 2)
+#define TPIU_FFSR_FTSTOPPED (1 << 1)
+#define TPIU_FFSR_FLINPROG (1 << 0)
+
+/* --- TPIU_FFCR values ---------------------------------------------------- */
+
+/* Bits 31:9 - Reserved */
+#define TPIU_FFCR_TRIGIN (1 << 8)
+/* Bits 7:2 - Reserved */
+#define TPIU_FFCR_ENFCONT (1 << 1)
+/* Bit 0 - Reserved */
+
+/* --- TPIU_DEVID values ---------------------------------------------------- */
+/* Bits 31:16 - Reserved */
+/* Bits 15:12 - Implementation defined */
+#define TPUI_DEVID_NRZ_SUPPORTED (1 << 11)
+#define TPUI_DEVID_MANCHESTER_SUPPORTED (1 << 10)
+/* Bit 9 - RAZ, indicated that trace data and clock are supported */
+#define TPUI_DEVID_FIFO_SIZE_MASK (7 << 6)
+/* Bits 5:0 - Implementation defined */
+
+#endif
diff --git a/libopencm3/include/libopencm3/cm3/vector.h b/libopencm3/include/libopencm3/cm3/vector.h
new file mode 100644
index 0000000..17ebb15
--- /dev/null
+++ b/libopencm3/include/libopencm3/cm3/vector.h
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 chrysn
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+/** @file
+ *
+ * Definitions for handling vector tables.
+ *
+ * This implements d0002_efm32_cortex-m3_reference_manual.pdf's figure 2.2
+ * (from the EFM32 documentation at
+ * http://www.energymicro.com/downloads/datasheets), and was seen analogously
+ * in other ARM implementations' libopencm3 files.
+ *
+ * The structure of the vector table is implemented independently of the system
+ * vector table starting at memory position 0x0, as it can be relocated to
+ * other memory locations too.
+ *
+ * The exact size of a vector interrupt table depends on the number of
+ * interrupts IRQ_COUNT, which is defined per family.
+ */
+
+#ifndef LIBOPENCM3_VECTOR_H
+#define LIBOPENCM3_VECTOR_H
+
+#include
+#include
+
+/** Type of an interrupt function. Only used to avoid hard-to-read function
+ * pointers in the efm32_vector_table_t struct. */
+typedef void (*vector_table_entry_t)(void);
+
+typedef struct {
+ unsigned int *initial_sp_value; /**< Initial stack pointer value. */
+ vector_table_entry_t reset;
+ vector_table_entry_t nmi;
+ vector_table_entry_t hard_fault;
+ vector_table_entry_t memory_manage_fault; /* not in CM0 */
+ vector_table_entry_t bus_fault; /* not in CM0 */
+ vector_table_entry_t usage_fault; /* not in CM0 */
+ vector_table_entry_t reserved_x001c[4];
+ vector_table_entry_t sv_call;
+ vector_table_entry_t debug_monitor; /* not in CM0 */
+ vector_table_entry_t reserved_x0034;
+ vector_table_entry_t pend_sv;
+ vector_table_entry_t systick;
+ vector_table_entry_t irq[NVIC_IRQ_COUNT];
+} vector_table_t;
+
+#endif
diff --git a/libopencm3/include/libopencm3/docmain.dox b/libopencm3/include/libopencm3/docmain.dox
new file mode 100644
index 0000000..f85aeb8
--- /dev/null
+++ b/libopencm3/include/libopencm3/docmain.dox
@@ -0,0 +1,21 @@
+/** @mainpage libopencm3 Developer Documentation
+
+@version 1.0.0
+
+@date 7 September 2012
+
+ * The libopencm3 project (previously known as libopenstm32) aims to create
+ * a free/libre/open-source (GPL v3, or later) firmware library for various
+ * ARM Cortex-M3 microcontrollers, including ST STM32, Toshiba TX03,
+ * Atmel SAM3U, NXP LPC1000 and others.
+ *
+ * @par ""
+ *
+ * See the libopencm3 wiki for
+ * more information.
+
+LGPL License Terms @ref lgpl_license
+*/
+
+
+
diff --git a/libopencm3/include/libopencm3/efm32/efm32g/doc-efm32g.h b/libopencm3/include/libopencm3/efm32/efm32g/doc-efm32g.h
new file mode 100644
index 0000000..747cb51
--- /dev/null
+++ b/libopencm3/include/libopencm3/efm32/efm32g/doc-efm32g.h
@@ -0,0 +1,32 @@
+/** @mainpage libopencm3 EFM32 Gecko
+
+@version 1.0.0
+
+@date 11 November 2012
+
+API documentation for Energy Micro EFM32 Gecko Cortex M3 series.
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup EFM32G EFM32 Gecko
+Libraries for Energy Micro EFM32 Gecko series.
+
+@version 1.0.0
+
+@date 11 November 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup EFM32G_defines EFM32 Gecko Defines
+
+@brief Defined Constants and Types for the Energy Micro EFM32 Gecko series
+
+@version 1.0.0
+
+@date 11 November 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
diff --git a/libopencm3/include/libopencm3/efm32/efm32g/irq.json b/libopencm3/include/libopencm3/efm32/efm32g/irq.json
new file mode 100644
index 0000000..59cc38b
--- /dev/null
+++ b/libopencm3/include/libopencm3/efm32/efm32g/irq.json
@@ -0,0 +1,38 @@
+{
+ "_source": "The names and sequence are taken from d0001_efm32g_reference_manual.pdf table 4.1.",
+ "irqs": [
+ "dma",
+ "gpio_even",
+ "timer0",
+ "usart0_rx",
+ "usart0_tx",
+ "acmp01",
+ "adc0",
+ "dac0",
+ "i2c0",
+ "gpio_odd",
+ "timer1",
+ "timer2",
+ "usart1_rx",
+ "usart1_tx",
+ "usart2_rx",
+ "usart2_tx",
+ "uart0_rx",
+ "uart0_tx",
+ "leuart0",
+ "leuart1",
+ "letimer0",
+ "pcnt0",
+ "pcnt1",
+ "pcnt2",
+ "rtc",
+ "cmu",
+ "vcmp",
+ "lcd",
+ "msc",
+ "aes"
+ ],
+ "partname_humanreadable": "EFM32 Gecko series",
+ "partname_doxygen": "EFM32G",
+ "includeguard": "LIBOPENCM3_EFM32G_NVIC_H"
+}
diff --git a/libopencm3/include/libopencm3/efm32/efm32gg/doc-efm32gg.h b/libopencm3/include/libopencm3/efm32/efm32gg/doc-efm32gg.h
new file mode 100644
index 0000000..aacb17b
--- /dev/null
+++ b/libopencm3/include/libopencm3/efm32/efm32gg/doc-efm32gg.h
@@ -0,0 +1,32 @@
+/** @mainpage libopencm3 EFM32 Giant Gecko
+
+@version 1.0.0
+
+@date 11 November 2012
+
+API documentation for Energy Micro EFM32 Giant Gecko Cortex M3 series.
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup EFM32GG EFM32 Giant Gecko
+Libraries for Energy Micro EFM32 Giant Gecko series.
+
+@version 1.0.0
+
+@date 11 November 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup EFM32GG_defines EFM32 Giant Gecko Defines
+
+@brief Defined Constants and Types for the Energy Micro EFM32 Giant Gecko series
+
+@version 1.0.0
+
+@date 11 November 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
diff --git a/libopencm3/include/libopencm3/efm32/efm32gg/irq.json b/libopencm3/include/libopencm3/efm32/efm32gg/irq.json
new file mode 100644
index 0000000..43e7e8c
--- /dev/null
+++ b/libopencm3/include/libopencm3/efm32/efm32gg/irq.json
@@ -0,0 +1,46 @@
+{
+ "_source": "The names and sequence are taken from d0053_efm32gg_refreence_manual.pdf table 4.1.",
+ "irqs": [
+ "dma",
+ "gpio_even",
+ "timer0",
+ "usart0_rx",
+ "usart0_tx",
+ "usb",
+ "acmp01",
+ "adc0",
+ "dac0",
+ "i2c0",
+ "i2c1",
+ "gpio_odd",
+ "timer1",
+ "timer2",
+ "timer3",
+ "usart1_rx",
+ "usart1_tx",
+ "lesense",
+ "usart2_rx",
+ "usart2_tx",
+ "uart0_rx",
+ "uart0_tx",
+ "uart1_rx",
+ "uart1_tx",
+ "leuart0",
+ "leuart1",
+ "letimer0",
+ "pcnt0",
+ "pcnt1",
+ "pcnt2",
+ "rtc",
+ "burtc",
+ "cmu",
+ "vcmp",
+ "lcd",
+ "msc",
+ "aes",
+ "ebi"
+ ],
+ "partname_humanreadable": "EFM32 Giant Gecko series",
+ "partname_doxygen": "EFM32GG",
+ "includeguard": "LIBOPENCM3_EFM32GG_NVIC_H"
+}
diff --git a/libopencm3/include/libopencm3/efm32/efm32lg/doc-efm32lg.h b/libopencm3/include/libopencm3/efm32/efm32lg/doc-efm32lg.h
new file mode 100644
index 0000000..7721239
--- /dev/null
+++ b/libopencm3/include/libopencm3/efm32/efm32lg/doc-efm32lg.h
@@ -0,0 +1,33 @@
+/** @mainpage libopencm3 EFM32 Leopard Gecko
+
+@version 1.0.0
+
+@date 4 March 2013
+
+API documentation for Energy Micro EFM32 Leopard Gecko Cortex M3 series.
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup EFM32LG EFM32 LeopardGecko
+Libraries for Energy Micro EFM32 Leopard Gecko series.
+
+@version 1.0.0
+
+@date 4 March 2013
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup EFM32LG_defines EFM32 Leopard Gecko Defines
+
+@brief Defined Constants and Types for the Energy Micro EFM32 Leopard Gecko
+series
+
+@version 1.0.0
+
+@date 4 March 2013
+
+LGPL License Terms @ref lgpl_license
+*/
+
diff --git a/libopencm3/include/libopencm3/efm32/efm32lg/irq.json b/libopencm3/include/libopencm3/efm32/efm32lg/irq.json
new file mode 100644
index 0000000..beb036d
--- /dev/null
+++ b/libopencm3/include/libopencm3/efm32/efm32lg/irq.json
@@ -0,0 +1,46 @@
+{
+ "_source": "The names and sequence are taken from d0183_efm32lg_reference_manual.pdf table 4.1.",
+ "irqs": [
+ "dma",
+ "gpio_even",
+ "timer0",
+ "usart0_rx",
+ "usart0_tx",
+ "usb",
+ "acmp01",
+ "adc0",
+ "dac0",
+ "i2c0",
+ "i2c1",
+ "gpio_odd",
+ "timer1",
+ "timer2",
+ "timer3",
+ "usart1_rx",
+ "usart1_tx",
+ "lesense",
+ "usart2_rx",
+ "usart2_tx",
+ "uart0_rx",
+ "uart0_tx",
+ "uart1_rx",
+ "uart1_tx",
+ "leuart0",
+ "leuart1",
+ "letimer0",
+ "pcnt0",
+ "pcnt1",
+ "pcnt2",
+ "rtc",
+ "burtc",
+ "cmu",
+ "vcmp",
+ "lcd",
+ "msc",
+ "aes",
+ "ebi"
+ ],
+ "partname_humanreadable": "EFM32 Leopard Gecko series",
+ "partname_doxygen": "EFM32LG",
+ "includeguard": "LIBOPENCM3_EFM32LG_NVIC_H"
+}
diff --git a/libopencm3/include/libopencm3/efm32/efm32tg/doc-efm32tg.h b/libopencm3/include/libopencm3/efm32/efm32tg/doc-efm32tg.h
new file mode 100644
index 0000000..799048c
--- /dev/null
+++ b/libopencm3/include/libopencm3/efm32/efm32tg/doc-efm32tg.h
@@ -0,0 +1,32 @@
+/** @mainpage libopencm3 EFM32 Tiny Gecko
+
+@version 1.0.0
+
+@date 4 March 2013
+
+API documentation for Energy Micro EFM32 Tiny Gecko Cortex M3 series.
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup EFM32TG EFM32 TinyGecko
+Libraries for Energy Micro EFM32 Tiny Gecko series.
+
+@version 1.0.0
+
+@date 4 March 2013
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup EFM32TG_defines EFM32 Tiny Gecko Defines
+
+@brief Defined Constants and Types for the Energy Micro EFM32 Tiny Gecko series
+
+@version 1.0.0
+
+@date 4 March 2013
+
+LGPL License Terms @ref lgpl_license
+*/
+
diff --git a/libopencm3/include/libopencm3/efm32/efm32tg/irq.json b/libopencm3/include/libopencm3/efm32/efm32tg/irq.json
new file mode 100644
index 0000000..95efa85
--- /dev/null
+++ b/libopencm3/include/libopencm3/efm32/efm32tg/irq.json
@@ -0,0 +1,31 @@
+{
+ "_source": "The names and sequence are taken from d0034_efm32tg_reference_manual.pdf table 4.1.",
+ "irqs": [
+ "dma",
+ "gpio_even",
+ "timer0",
+ "usart0_rx",
+ "usart0_tx",
+ "acmp01",
+ "adc0",
+ "dac0",
+ "i2c0",
+ "gpio_odd",
+ "timer1",
+ "usart1_rx",
+ "usart1_tx",
+ "lesense",
+ "leuart0",
+ "letimer0",
+ "pcnt0",
+ "rtc",
+ "cmu",
+ "vcmp",
+ "lcd",
+ "msc",
+ "aes"
+ ],
+ "partname_humanreadable": "EFM32 Tiny Gecko series",
+ "partname_doxygen": "EFM32TG",
+ "includeguard": "LIBOPENCM3_EFM32TG_NVIC_H"
+}
diff --git a/libopencm3/include/libopencm3/efm32/efm32tg/memorymap.h b/libopencm3/include/libopencm3/efm32/efm32tg/memorymap.h
new file mode 100644
index 0000000..d17bb60
--- /dev/null
+++ b/libopencm3/include/libopencm3/efm32/efm32tg/memorymap.h
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 chrysn
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+/** @file
+ *
+ * Layout of the system address space of Tiny Gecko devices.
+ *
+ * This reflects d0034_efm32tg_reference_manual.pdf figure 5.2.
+ */
+
+/* The common cortex-m3 definitions were verified from
+ * d0034_efm32tg_reference_manual.pdf figure 5.2. The CM3 ROM Table seems to be
+ * missing there. The details (everything based on SCS_BASE) was verified from
+ * d0002_efm32_cortex-m3_reference_manual.pdf table 4.1, and seems to fit, but
+ * there are discrepancies. */
+#include
+
+#define CODE_BASE (0x00000000U)
+
+#define SRAM_BASE (0x20000000U)
+#define SRAM_BASE_BITBAND (0x22000000U)
+
+#define PERIPH_BASE (0x40000000U)
+#define PERIPH_BASE_BITBAND (0x42000000U)
+
+/* Details of the "Code" section */
+
+#define FLASH_BASE (CODE_BASE + 0x00000000)
+#define USERDATA_BASE (CODE_BASE + 0x0fe00000)
+#define LOCKBITS_BASE (CODE_BASE + 0x0fe04000)
+#define CHIPCONFIG_BASE (CODE_BASE + 0x0fe08000)
+#define CODESPACESRAM_BASE (CODE_BASE + 0x10000000)
+
+/* Tiny Gecko peripherial definitions */
+
+#define VCMP_BASE (PERIPH_BASE + 0x00000000)
+#define ACMP0_BASE (PERIPH_BASE + 0x00001000)
+#define ACMP1_BASE (PERIPH_BASE + 0x00001400)
+#define ADC_BASE (PERIPH_BASE + 0x00002000)
+#define DAC0_BASE (PERIPH_BASE + 0x00004000)
+#define GPIO_BASE (PERIPH_BASE + 0x00006000) /**< @see gpio.h */
+#define I2C0_BASE (PERIPH_BASE + 0x0000a000)
+#define USART0_BASE (PERIPH_BASE + 0x0000c000)
+#define USART1_BASE (PERIPH_BASE + 0x0000c400)
+#define TIMER0_BASE (PERIPH_BASE + 0x00010000)
+#define TIMER1_BASE (PERIPH_BASE + 0x00010400)
+#define RTC_BASE (PERIPH_BASE + 0x00080000)
+#define LETIMER0_BASE (PERIPH_BASE + 0x00082000)
+#define LEUART0_BASE (PERIPH_BASE + 0x00084000)
+#define PCNT0_BASE (PERIPH_BASE + 0x00086000)
+#define WDOG_BASE (PERIPH_BASE + 0x00088000)
+#define LCD_BASE (PERIPH_BASE + 0x0008a000)
+#define LESENSE_BASE (PERIPH_BASE + 0x0008c000)
+#define MSC_BASE (PERIPH_BASE + 0x000c0000)
+#define DMA_BASE (PERIPH_BASE + 0x000c2000)
+#define EMU_BASE (PERIPH_BASE + 0x000c6000)
+#define CMU_BASE (PERIPH_BASE + 0x000c8000) /**< @see cmu.h */
+#define RMU_BASE (PERIPH_BASE + 0x000ca000)
+#define PRS_BASE (PERIPH_BASE + 0x000cc000)
+#define AES_BASE (PERIPH_BASE + 0x000e0000)
diff --git a/libopencm3/include/libopencm3/efm32/memorymap.h b/libopencm3/include/libopencm3/efm32/memorymap.h
new file mode 100644
index 0000000..ff0e544
--- /dev/null
+++ b/libopencm3/include/libopencm3/efm32/memorymap.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 chrysn
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+/** @file
+ *
+ * Dispatcher for the base address definitions, depending on the particular
+ * Gecko family.
+ *
+ * @see tinygecko/memorymap.h
+ */
+
+#ifndef LIBOPENCM3_EFM32_MEMORYMAP_H
+#define LIBOPENCM3_EFM32_MEMORYMAP_H
+
+#ifdef TINYGECKO
+# include
+#else
+# error "efm32 family not defined."
+#endif
+
+#endif
diff --git a/libopencm3/include/libopencm3/ethernet/mac.h b/libopencm3/include/libopencm3/ethernet/mac.h
new file mode 100644
index 0000000..b047e4d
--- /dev/null
+++ b/libopencm3/include/libopencm3/ethernet/mac.h
@@ -0,0 +1,46 @@
+/** @defgroup ethernet_mac_defines MAC Generic Defines
+ *
+ * @brief Defined Constants and Types for the Ethernet MAC
+ *
+ * @ingroup ETH
+ *
+ * @version 1.0.0
+ *
+ * @author @htmlonly © @endhtmlonly 2013 Frantisek Burian
+ *
+ * @date 1 September 2013
+ *
+ * LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2013 Frantisek Burian
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+/**@{*/
+
+#if defined(STM32F1)
+# include
+#elif defined(STM32F4)
+# include
+#else
+# error "stm32 family not defined."
+#endif
+
+/**@}*/
+
+
diff --git a/libopencm3/include/libopencm3/ethernet/mac_stm32fxx7.h b/libopencm3/include/libopencm3/ethernet/mac_stm32fxx7.h
new file mode 100644
index 0000000..a14a911
--- /dev/null
+++ b/libopencm3/include/libopencm3/ethernet/mac_stm32fxx7.h
@@ -0,0 +1,752 @@
+/** @defgroup ethernet_mac_stm32fxx7_defines MAC STM32Fxx7 Defines
+ *
+ * @brief Defined Constants and Types for the Ethernet MAC for STM32Fxx7
+ * chips
+ *
+ * @ingroup ETH
+ *
+ * @version 1.0.0
+ *
+ * @author @htmlonly © @endhtmlonly 2013 Frantisek Burian
+ *
+ * @date 1 September 2013
+ *
+ * LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2013 Frantisek Burian
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LIBOPENCM3_ETHERNET_H
+#define LIBOPENCM3_ETHERNET_H
+
+#include
+#include
+
+/**@{*/
+
+/* Ethernet MAC registers */
+#define ETH_MACCR MMIO32(ETHERNET_BASE + 0x00)
+#define ETH_MACFFR MMIO32(ETHERNET_BASE + 0x04)
+#define ETH_MACHTHR MMIO32(ETHERNET_BASE + 0x08)
+#define ETH_MACHTLR MMIO32(ETHERNET_BASE + 0x0C)
+#define ETH_MACMIIAR MMIO32(ETHERNET_BASE + 0x10)
+#define ETH_MACMIIDR MMIO32(ETHERNET_BASE + 0x14)
+#define ETH_MACFCR MMIO32(ETHERNET_BASE + 0x18)
+#define ETH_MACVLANTR MMIO32(ETHERNET_BASE + 0x1C)
+#define ETH_MACRWUFFR MMIO32(ETHERNET_BASE + 0x28)
+#define ETH_MACPMTCSR MMIO32(ETHERNET_BASE + 0x2C)
+/* not available on F1 ?*/
+#define ETH_MACDBGR MMIO32(ETHERNET_BASE + 0x34)
+#define ETH_MACSR MMIO32(ETHERNET_BASE + 0x38)
+#define ETH_MACIMR MMIO32(ETHERNET_BASE + 0x3C)
+
+/* i=[0..3] */
+#define ETH_MACAHR(i) MMIO32(ETHERNET_BASE + 0x40+i*8)
+/* i=[0..3] */
+#define ETH_MACALR(i) MMIO32(ETHERNET_BASE + 0x44+i*8)
+
+/* Ethernet MMC registers */
+#define ETH_MMCCR MMIO32(ETHERNET_BASE + 0x100)
+#define ETH_MMCRIR MMIO32(ETHERNET_BASE + 0x104)
+#define ETH_MMCTIR MMIO32(ETHERNET_BASE + 0x108)
+#define ETH_MMCRIMR MMIO32(ETHERNET_BASE + 0x10C)
+#define ETH_MMCTIMR MMIO32(ETHERNET_BASE + 0x110)
+#define ETH_MMCTGFSCCR MMIO32(ETHERNET_BASE + 0x14C)
+#define ETH_MMCTGFMSCCR MMIO32(ETHERNET_BASE + 0x150)
+#define ETH_MMCTGFCR MMIO32(ETHERNET_BASE + 0x168)
+#define ETH_MMCRFCECR MMIO32(ETHERNET_BASE + 0x194)
+#define ETH_MMCRFAECR MMIO32(ETHERNET_BASE + 0x198)
+#define ETH_MMCRGUFCR MMIO32(ETHERNET_BASE + 0x1C4)
+
+/* Ethrenet IEEE 1588 time stamp registers */
+#define ETH_PTPTSCR MMIO32(ETHERNET_BASE + 0x700)
+#define ETH_PTPSSIR MMIO32(ETHERNET_BASE + 0x704)
+#define ETH_PTPTSHR MMIO32(ETHERNET_BASE + 0x708)
+#define ETH_PTPTSLR MMIO32(ETHERNET_BASE + 0x70C)
+#define ETH_PTPTSHUR MMIO32(ETHERNET_BASE + 0x710)
+#define ETH_PTPTSLUR MMIO32(ETHERNET_BASE + 0x714)
+#define ETH_PTPTSAR MMIO32(ETHERNET_BASE + 0x718)
+#define ETH_PTPTTHR MMIO32(ETHERNET_BASE + 0x71C)
+#define ETH_PTPTTLR MMIO32(ETHERNET_BASE + 0x720)
+/* not available on F1 ?*/
+#define ETH_PTPTSSR MMIO32(ETHERNET_BASE + 0x728)
+
+/* Ethernet DMA registers */
+#define ETH_DMABMR MMIO32(ETHERNET_BASE + 0x1000)
+#define ETH_DMATPDR MMIO32(ETHERNET_BASE + 0x1004)
+#define ETH_DMARPDR MMIO32(ETHERNET_BASE + 0x1008)
+#define ETH_DMARDLAR MMIO32(ETHERNET_BASE + 0x100C)
+#define ETH_DMATDLAR MMIO32(ETHERNET_BASE + 0x1010)
+#define ETH_DMASR MMIO32(ETHERNET_BASE + 0x1014)
+#define ETH_DMAOMR MMIO32(ETHERNET_BASE + 0x1018)
+#define ETH_DMAIER MMIO32(ETHERNET_BASE + 0x101C)
+#define ETH_DMAMFBOCR MMIO32(ETHERNET_BASE + 0x1020)
+#define ETH_DMACHTDR MMIO32(ETHERNET_BASE + 0x1048)
+#define ETH_DMACHRDR MMIO32(ETHERNET_BASE + 0x104C)
+#define ETH_DMACHTBAR MMIO32(ETHERNET_BASE + 0x1050)
+#define ETH_DMACHRBAR MMIO32(ETHERNET_BASE + 0x1054)
+
+/* Ethernet Buffer Descriptors */
+#define ETH_DES(n, base) MMIO32((base) + (n)*4)
+#define ETH_DES0(base) ETH_DES(0, base)
+#define ETH_DES1(base) ETH_DES(1, base)
+#define ETH_DES2(base) ETH_DES(2, base)
+#define ETH_DES3(base) ETH_DES(3, base)
+
+/* Ethernet Extended buffer Descriptors */
+#define ETH_DES4(base) ETH_DES(4, base)
+#define ETH_DES5(base) ETH_DES(5, base)
+#define ETH_DES6(base) ETH_DES(6, base)
+#define ETH_DES7(base) ETH_DES(7, base)
+
+/*---------------------------------------------------------------------------*/
+/* MACCR --------------------------------------------------------------------*/
+
+#define ETH_MACCR_RE (1<<2)
+#define ETH_MACCR_TE (1<<3)
+#define ETH_MACCR_DC (1<<4)
+
+#define ETH_MACCR_BL_SHIFT 5
+#define ETH_MACCR_BL (3 << ETH_MACCR_BL_SHIFT)
+#define ETH_MACCR_BL_MIN10 (0 << ETH_MACCR_BL_SHIFT)
+#define ETH_MACCR_BL_MIN8 (1 << ETH_MACCR_BL_SHIFT)
+#define ETH_MACCR_BL_MIN4 (2 << ETH_MACCR_BL_SHIFT)
+#define ETH_MACCR_BL_MIN1 (3 << ETH_MACCR_BL_SHIFT)
+
+#define ETH_MACCR_APCS (1<<7)
+#define ETH_MACCR_RD (1<<9)
+#define ETH_MACCR_IPCO (1<<10)
+#define ETH_MACCR_DM (1<<11)
+#define ETH_MACCR_LM (1<<12)
+#define ETH_MACCR_ROD (1<<13)
+#define ETH_MACCR_FES (1<<14)
+#define ETH_MACCR_CSD (1<<16)
+
+#define ETH_MACCR_IFG_SHIFT 17
+#define ETH_MACCR_IFG (7<Defined Constants and Types for the Ethernet PHY
+ *
+ * @ingroup ETH
+ *
+ * @version 1.0.0
+ *
+ * @author @htmlonly © @endhtmlonly 2013 Frantisek Burian
+ *
+ * @date 1 September 2013
+ *
+ * LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2013 Frantisek Burian
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+#ifndef LIBOPENCM3_PHY_H
+#define LIBOPENCM3_PHY_H
+
+#include
+
+/**@{*/
+
+/* Registers */
+
+#define PHY_REG_BCR 0x00
+#define PHY_REG_BSR 0x01
+#define PHY_REG_ID1 0x02
+#define PHY_REG_ID2 0x03
+#define PHY_REG_ANTX 0x04
+#define PHY_REG_ANRX 0x05
+#define PHY_REG_ANEXP 0x06
+#define PHY_REG_ANNPTX 0x07
+#define PHY_REG_ANNPRX 0x08
+
+#define PHY_REG_BCR_COLTEST (1<<7)
+#define PHY_REG_BCR_FD (1<<8)
+#define PHY_REG_BCR_ANRST (1<<9)
+#define PHY_REG_BCR_ISOLATE (1<<10)
+#define PHY_REG_BCR_POWERDN (1<<11)
+#define PHY_REG_BCR_AN (1<<12)
+#define PHY_REG_BCR_100M (1<<13)
+#define PHY_REG_BCR_LOOPBACK (1<<14)
+#define PHY_REG_BCR_RESET (1<<15)
+
+#define PHY_REG_BSR_JABBER (1<<1)
+#define PHY_REG_BSR_UP (1<<2)
+#define PHY_REG_BSR_FAULT (1<<4)
+#define PHY_REG_BSR_ANDONE (1<<5)
+
+
+enum phy_status {
+ LINK_DOWN,
+ LINK_HD_10M,
+ LINK_HD_100M,
+ LINK_HD_1000M,
+ LINK_HD_10000M,
+ LINK_FD_10M,
+ LINK_FD_100M,
+ LINK_FD_1000M,
+ LINK_FD_10000M,
+};
+
+void phy_reset(void);
+bool phy_link_isup(void);
+
+enum phy_status phy_link_status(void);
+
+void phy_autoneg_force(enum phy_status mode);
+void phy_autoneg_enable(void);
+
+/**@}*/
+
+
+#endif /* LIBOPENCM3_PHY_H__ */
diff --git a/libopencm3/include/libopencm3/ethernet/phy_ksz8051mll.h b/libopencm3/include/libopencm3/ethernet/phy_ksz8051mll.h
new file mode 100644
index 0000000..a7f9865
--- /dev/null
+++ b/libopencm3/include/libopencm3/ethernet/phy_ksz8051mll.h
@@ -0,0 +1,60 @@
+/** @defgroup ethernet_phy_ksz8051mll_defines PHY KSZ8051mll Defines
+ *
+ * @brief Defined Constants and Types for the Ethernet PHY KSZ8051mll
+ * chips
+ *
+ * @ingroup ETH
+ *
+ * @version 1.0.0
+ *
+ * @author @htmlonly © @endhtmlonly 2013 Frantisek Burian
+ *
+ * @date 1 September 2013
+ *
+ * LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2013 Frantisek Burian
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LIBOPENCM3_PHY_KSZ8051MLL_H
+#define LIBOPENCM3_PHY_KSZ8051MLL_H
+
+#include
+
+/**@{*/
+
+/* Registers */
+
+#define PHY_REG_AFECTRL 0x11
+#define PHY_REG_RXERCTR 0x15
+#define PHY_REG_STRAPOVRD 0x16
+#define PHY_REG_STRAPSTAT 0x17
+#define PHY_REG_ECR 0x18
+
+#define PHY_REG_ICSR 0x1B
+
+#define PHY_REG_LINKMD 0x1D
+
+#define PHY_REG_CR1 0x1E
+#define PHY_REG_CR2 0x1E
+
+/**@}*/
+
+
+#endif /* LIBOPENCM3_PHY_KSZ8051MLL_H__ */
diff --git a/libopencm3/include/libopencm3/license.dox b/libopencm3/include/libopencm3/license.dox
new file mode 100644
index 0000000..3aa9331
--- /dev/null
+++ b/libopencm3/include/libopencm3/license.dox
@@ -0,0 +1,16 @@
+/** @page lgpl_license libopencm3 License
+
+libopencm3 is free software: you can redistribute it and/or modify
+it under the terms of the GNU Lesser General Public License as published by the Free
+Software Foundation, either version 3 of the License, or (at your option) any
+later version.
+
+libopencm3 is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details.
+
+You should have received a copy of the GNU Lesser General Public License along with this
+program. If not, see .
+
+*/
+
diff --git a/libopencm3/include/libopencm3/lm3s/doc-lm3s.h b/libopencm3/include/libopencm3/lm3s/doc-lm3s.h
new file mode 100644
index 0000000..1a4ecb8
--- /dev/null
+++ b/libopencm3/include/libopencm3/lm3s/doc-lm3s.h
@@ -0,0 +1,32 @@
+/** @mainpage libopencm3 LM3S
+
+@version 1.0.0
+
+@date 14 September 2012
+
+API documentation for TI Stellaris LM3S Cortex M3 series.
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup LM3Sxx LM3S
+Libraries for TI Stellaris LM3S series.
+
+@version 1.0.0
+
+@date 7 September 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup LM3Sxx_defines LM3S Defines
+
+@brief Defined Constants and Types for the LM3S series
+
+@version 1.0.0
+
+@date 14 September 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
diff --git a/libopencm3/include/libopencm3/lm3s/gpio.h b/libopencm3/include/libopencm3/lm3s/gpio.h
new file mode 100644
index 0000000..8b12078
--- /dev/null
+++ b/libopencm3/include/libopencm3/lm3s/gpio.h
@@ -0,0 +1,99 @@
+/** @defgroup gpio_defines General Purpose I/O Defines
+
+@brief Defined Constants and Types for the LM3S General Purpose I/O
+
+@ingroup LM3Sxx_defines
+
+@version 1.0.0
+
+@author @htmlonly © @endhtmlonly 2011
+Gareth McMullin
+
+@date 10 March 2013
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Gareth McMullin
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LM3S_GPIO_H
+#define LM3S_GPIO_H
+
+/**@{*/
+
+#include
+#include
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* GPIO port base addresses (for convenience) */
+#define GPIOA GPIOA_APB_BASE
+#define GPIOB GPIOB_APB_BASE
+#define GPIOC GPIOC_APB_BASE
+#define GPIOD GPIOD_APB_BASE
+#define GPIOE GPIOE_APB_BASE
+#define GPIOF GPIOF_APB_BASE
+#define GPIOG GPIOG_APB_BASE
+#define GPIOH GPIOH_APB_BASE
+
+/* GPIO number definitions (for convenience) */
+#define GPIO0 (1 << 0)
+#define GPIO1 (1 << 1)
+#define GPIO2 (1 << 2)
+#define GPIO3 (1 << 3)
+#define GPIO4 (1 << 4)
+#define GPIO5 (1 << 5)
+#define GPIO6 (1 << 6)
+#define GPIO7 (1 << 7)
+
+/* --- GPIO registers ------------------------------------------------------ */
+
+#define GPIO_DATA(port) (&MMIO32(port + 0x000))
+#define GPIO_DIR(port) MMIO32(port + 0x400)
+#define GPIO_IS(port) MMIO32(port + 0x404)
+#define GPIO_IBE(port) MMIO32(port + 0x408)
+#define GPIO_IEV(port) MMIO32(port + 0x40c)
+#define GPIO_IM(port) MMIO32(port + 0x410)
+#define GPIO_RIS(port) MMIO32(port + 0x414)
+#define GPIO_MIS(port) MMIO32(port + 0x418)
+#define GPIO_ICR(port) MMIO32(port + 0x41c)
+#define GPIO_AFSEL(port) MMIO32(port + 0x420)
+#define GPIO_DR2R(port) MMIO32(port + 0x500)
+#define GPIO_DR4R(port) MMIO32(port + 0x504)
+#define GPIO_DR8R(port) MMIO32(port + 0x508)
+#define GPIO_ODR(port) MMIO32(port + 0x50c)
+#define GPIO_PUR(port) MMIO32(port + 0x510)
+#define GPIO_PDR(port) MMIO32(port + 0x514)
+#define GPIO_SLR(port) MMIO32(port + 0x518)
+#define GPIO_DEN(port) MMIO32(port + 0x51c)
+#define GPIO_LOCK(port) MMIO32(port + 0x520)
+#define GPIO_CR(port) MMIO32(port + 0x524)
+#define GPIO_AMSEL(port) MMIO32(port + 0x528)
+
+BEGIN_DECLS
+
+void gpio_set(uint32_t gpioport, uint8_t gpios);
+void gpio_clear(uint32_t gpioport, uint8_t gpios);
+
+END_DECLS
+
+/**@}*/
+
+#endif
+
diff --git a/libopencm3/include/libopencm3/lm3s/irq.json b/libopencm3/include/libopencm3/lm3s/irq.json
new file mode 100644
index 0000000..0d8dcfc
--- /dev/null
+++ b/libopencm3/include/libopencm3/lm3s/irq.json
@@ -0,0 +1,126 @@
+{
+ "_comment": [
+ "Although this says LM3S, the interrupt table applies to the",
+ "LM4F as well Some interrupt vectores marked as reserved in LM3S are",
+ "used in LM4F, and some vectors in LM3S are marked reserved for LM4F.",
+ "However, the common vectors are identical, and we can safely use the",
+ "same interrupt table. Reserved vectors will never be triggered, so",
+ "having them is perfectly safe."
+ ],
+ "irqs": {
+ "0": "GPIOA",
+ "1": "GPIOB",
+ "2": "GPIOC",
+ "3": "GPIOD",
+ "4": "GPIOE",
+ "5": "UART0",
+ "6": "UART1",
+ "7": "SSI0",
+ "8": "I2C0",
+ "9": "PWM0_FAULT",
+ "10": "PWM0_0",
+ "11": "PWM0_1",
+ "12": "PWM0_2",
+ "13": "QEI0",
+ "14": "ADC0SS0",
+ "15": "ADC0SS1",
+ "16": "ADC0SS2",
+ "17": "ADC0SS3",
+ "18": "WATCHDOG",
+ "19": "TIMER0A",
+ "20": "TIMER0B",
+ "21": "TIMER1A",
+ "22": "TIMER1B",
+ "23": "TIMER2A",
+ "24": "TIMER2B",
+ "25": "COMP0",
+ "26": "COMP1",
+ "27": "COMP2",
+ "28": "SYSCTL",
+ "29": "FLASH",
+ "30": "GPIOF",
+ "31": "GPIOG",
+ "32": "GPIOH",
+ "33": "UART2",
+ "34": "SSI1",
+ "35": "TIMER3A",
+ "36": "TIMER3B",
+ "37": "I2C1",
+ "38": "QEI1",
+ "39": "CAN0",
+ "40": "CAN1",
+ "41": "CAN2",
+ "42": "ETH",
+ "43": "HIBERNATE",
+ "44": "USB0",
+ "45": "PWM0_3",
+ "46": "UDMA",
+ "47": "UDMAERR",
+ "48": "ADC1SS0",
+ "49": "ADC1SS1",
+ "50": "ADC1SS2",
+ "51": "ADC1SS3",
+ "52": "I2S0",
+ "53": "EPI0",
+ "54": "GPIOJ",
+ "55": "GPIOK",
+ "56": "GPIOL",
+ "57": "SSI2",
+ "58": "SSI3",
+ "59": "UART3",
+ "60": "UART4",
+ "61": "UART5",
+ "62": "UART6",
+ "63": "UART7",
+ "68": "I2C2",
+ "69": "I2C3",
+ "70": "TIMER4A",
+ "71": "TIMER4B",
+ "92": "TIMER5A",
+ "93": "TIMER5B",
+ "94": "WTIMER0A",
+ "95": "WTIMER0B",
+ "96": "WTIMER1A",
+ "97": "WTIMER1B",
+ "98": "WTIMER2A",
+ "99": "WTIMER2B",
+ "100": "WTIMER3A",
+ "101": "WTIMER3B",
+ "102": "WTIMER4A",
+ "103": "WTIMER4B",
+ "104": "WTIMER5A",
+ "105": "WTIMER5B",
+ "106": "SYSEXC",
+ "107": "PECI0",
+ "108": "LPC0",
+ "109": "I2C4",
+ "110": "I2C5",
+ "111": "GPIOM",
+ "112": "GPION",
+ "114": "FAN0",
+ "116": "GPIOP0",
+ "117": "GPIOP1",
+ "118": "GPIOP2",
+ "119": "GPIOP3",
+ "120": "GPIOP4",
+ "121": "GPIOP5",
+ "122": "GPIOP6",
+ "123": "GPIOP7",
+ "124": "GPIOQ0",
+ "125": "GPIOQ1",
+ "126": "GPIOQ2",
+ "127": "GPIOQ3",
+ "128": "GPIOQ4",
+ "129": "GPIOQ5",
+ "130": "GPIOQ6",
+ "131": "GPIOQ7",
+ "134": "PWM1_0",
+ "135": "PWM1_1",
+ "136": "PWM1_2",
+ "137": "PWM1_3",
+ "138": "PWM1_FAULT"
+ },
+ "partname_humanreadable": "LM3S series",
+ "partname_doxygen": "LM3S",
+ "includeguard": "LIBOPENCM3_LM3S_NVIC_H"
+}
diff --git a/libopencm3/include/libopencm3/lm3s/memorymap.h b/libopencm3/include/libopencm3/lm3s/memorymap.h
new file mode 100644
index 0000000..df5d6e3
--- /dev/null
+++ b/libopencm3/include/libopencm3/lm3s/memorymap.h
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Gareth McMullin
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LM3S_MEMORYMAP_H
+#define LM3S_MEMORYMAP_H
+
+#include
+
+/* --- LM3S specific peripheral definitions ----------------------------- */
+
+#define GPIOA_APB_BASE (0x40004000U)
+#define GPIOB_APB_BASE (0x40005000U)
+#define GPIOC_APB_BASE (0x40006000U)
+#define GPIOD_APB_BASE (0x40007000U)
+#define GPIOE_APB_BASE (0x40024000U)
+#define GPIOF_APB_BASE (0x40025000U)
+#define GPIOG_APB_BASE (0x40026000U)
+#define GPIOH_APB_BASE (0x40027000U)
+
+#define GPIOA_BASE (0x40058000U)
+#define GPIOB_BASE (0x40059000U)
+#define GPIOC_BASE (0x4005A000U)
+#define GPIOD_BASE (0x4005B000U)
+#define GPIOE_BASE (0x4005C000U)
+#define GPIOF_BASE (0x4005D000U)
+#define GPIOG_BASE (0x4005E000U)
+#define GPIOH_BASE (0x4005F000U)
+
+#define SYSTEMCONTROL_BASE (0x400FE000U)
+
+#endif
diff --git a/libopencm3/include/libopencm3/lm3s/systemcontrol.h b/libopencm3/include/libopencm3/lm3s/systemcontrol.h
new file mode 100644
index 0000000..dd02f0f
--- /dev/null
+++ b/libopencm3/include/libopencm3/lm3s/systemcontrol.h
@@ -0,0 +1,81 @@
+/** @defgroup systemcontrol_defines System Control
+
+@brief Defined Constants and Types for the LM3S System Control
+
+@ingroup LM3Sxx_defines
+
+@version 1.0.0
+
+@author @htmlonly © @endhtmlonly 2011
+Gareth McMullin
+
+@date 10 March 2013
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Gareth McMullin
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LM3S_SYSTEMCONTROL_H
+#define LM3S_SYSTEMCONTROL_H
+
+/**@{*/
+
+#include
+
+#define SYSTEMCONTROL_DID0 MMIO32(SYSTEMCONTROL_BASE + 0x000)
+#define SYSTEMCONTROL_DID1 MMIO32(SYSTEMCONTROL_BASE + 0x004)
+#define SYSTEMCONTROL_DC0 MMIO32(SYSTEMCONTROL_BASE + 0x008)
+#define SYSTEMCONTROL_DC1 MMIO32(SYSTEMCONTROL_BASE + 0x010)
+#define SYSTEMCONTROL_DC2 MMIO32(SYSTEMCONTROL_BASE + 0x014)
+#define SYSTEMCONTROL_DC3 MMIO32(SYSTEMCONTROL_BASE + 0x018)
+#define SYSTEMCONTROL_DC4 MMIO32(SYSTEMCONTROL_BASE + 0x01C)
+#define SYSTEMCONTROL_DC5 MMIO32(SYSTEMCONTROL_BASE + 0x020)
+#define SYSTEMCONTROL_DC6 MMIO32(SYSTEMCONTROL_BASE + 0x024)
+#define SYSTEMCONTROL_DC7 MMIO32(SYSTEMCONTROL_BASE + 0x028)
+#define SYSTEMCONTROL_PBORCTL MMIO32(SYSTEMCONTROL_BASE + 0x030)
+#define SYSTEMCONTROL_LDORCTL MMIO32(SYSTEMCONTROL_BASE + 0x034)
+#define SYSTEMCONTROL_SRCR0 MMIO32(SYSTEMCONTROL_BASE + 0x040)
+#define SYSTEMCONTROL_SRCR1 MMIO32(SYSTEMCONTROL_BASE + 0x044)
+#define SYSTEMCONTROL_SRCR2 MMIO32(SYSTEMCONTROL_BASE + 0x048)
+#define SYSTEMCONTROL_RIS MMIO32(SYSTEMCONTROL_BASE + 0x050)
+#define SYSTEMCONTROL_IMC MMIO32(SYSTEMCONTROL_BASE + 0x054)
+#define SYSTEMCONTROL_MISC MMIO32(SYSTEMCONTROL_BASE + 0x058)
+#define SYSTEMCONTROL_RESC MMIO32(SYSTEMCONTROL_BASE + 0x05C)
+#define SYSTEMCONTROL_RCC MMIO32(SYSTEMCONTROL_BASE + 0x060)
+#define SYSTEMCONTROL_PLLCFG MMIO32(SYSTEMCONTROL_BASE + 0x064)
+#define SYSTEMCONTROL_GPIOHBCTL MMIO32(SYSTEMCONTROL_BASE + 0x06C)
+#define SYSTEMCONTROL_RCC2 MMIO32(SYSTEMCONTROL_BASE + 0x070)
+#define SYSTEMCONTROL_MOSCCTL MMIO32(SYSTEMCONTROL_BASE + 0x07C)
+#define SYSTEMCONTROL_RCGC0 MMIO32(SYSTEMCONTROL_BASE + 0x100)
+#define SYSTEMCONTROL_RCGC1 MMIO32(SYSTEMCONTROL_BASE + 0x104)
+#define SYSTEMCONTROL_RCGC2 MMIO32(SYSTEMCONTROL_BASE + 0x108)
+#define SYSTEMCONTROL_SCGC0 MMIO32(SYSTEMCONTROL_BASE + 0x110)
+#define SYSTEMCONTROL_SCGC1 MMIO32(SYSTEMCONTROL_BASE + 0x114)
+#define SYSTEMCONTROL_SCGC2 MMIO32(SYSTEMCONTROL_BASE + 0x118)
+#define SYSTEMCONTROL_DCGC0 MMIO32(SYSTEMCONTROL_BASE + 0x120)
+#define SYSTEMCONTROL_DCGC1 MMIO32(SYSTEMCONTROL_BASE + 0x124)
+#define SYSTEMCONTROL_DCGC2 MMIO32(SYSTEMCONTROL_BASE + 0x128)
+#define SYSTEMCONTROL_DSLPCLKCFG MMIO32(SYSTEMCONTROL_BASE + 0x144)
+
+/**@}*/
+
+#endif
+
diff --git a/libopencm3/include/libopencm3/lm4f/doc-lm4f.h b/libopencm3/include/libopencm3/lm4f/doc-lm4f.h
new file mode 100644
index 0000000..4877721
--- /dev/null
+++ b/libopencm3/include/libopencm3/lm4f/doc-lm4f.h
@@ -0,0 +1,32 @@
+/** @mainpage libopencm3 LM4F
+
+@version 1.0.0
+
+@date 22 November 2012
+
+API documentation for TI Stellaris LM4F Cortex M4F series.
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup LM4Fxx LM4F
+Libraries for TI Stellaris LM4F series.
+
+@version 1.0.0
+
+@date 22 November 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup LM4Fxx_defines LM4F Defines
+
+@brief Defined Constants and Types for the LM4F series
+
+@version 1.0.0
+
+@date 22 November 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
diff --git a/libopencm3/include/libopencm3/lm4f/gpio.h b/libopencm3/include/libopencm3/lm4f/gpio.h
new file mode 100644
index 0000000..5f90ad3
--- /dev/null
+++ b/libopencm3/include/libopencm3/lm4f/gpio.h
@@ -0,0 +1,380 @@
+/** @defgroup gpio_defines General Purpose I/O Defines
+ *
+ * @brief Defined Constants and Types for the LM4F General Purpose I/O
+ *
+ * @ingroup LM4Fxx_defines
+ *
+ * @version 1.0.0
+ *
+ * @author @htmlonly © @endhtmlonly 2011
+ * Gareth McMullin
+ * @author @htmlonly © @endhtmlonly 2013
+ * Alexandru Gagniuc
+ *
+ * @date 16 March 2013
+ *
+ * LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Gareth McMullin
+ * Copyright (C) 2013 Alexandru Gagniuc
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LM4F_GPIO_H
+#define LM4F_GPIO_H
+
+/**@{*/
+
+#include
+#include
+
+/* =============================================================================
+ * Convenience macros
+ * ---------------------------------------------------------------------------*/
+/** @defgroup gpio_reg_base GPIO register base addresses
+ * @{*/
+#define GPIOA GPIOA_BASE
+#define GPIOB GPIOB_BASE
+#define GPIOC GPIOC_BASE
+#define GPIOD GPIOD_BASE
+#define GPIOE GPIOE_BASE
+#define GPIOF GPIOF_BASE
+#define GPIOG GPIOG_BASE
+#define GPIOH GPIOH_BASE
+#define GPIOJ GPIOJ_BASE
+#define GPIOK GPIOK_BASE
+#define GPIOL GPIOL_BASE
+#define GPIOM GPIOM_BASE
+#define GPION GPION_BASE
+#define GPIOP GPIOP_BASE
+#define GPIOQ GPIOQ_BASE
+/** @} */
+
+/* =============================================================================
+ * GPIO number definitions (for convenience)
+ *
+ * These are usable across all GPIO registers,
+ * except GPIO_LOCK and GPIO_PCTL
+ * ---------------------------------------------------------------------------*/
+/** @defgroup gpio_pin_id GPIO pin identifiers
+ * @{*/
+#define GPIO0 (1 << 0)
+#define GPIO1 (1 << 1)
+#define GPIO2 (1 << 2)
+#define GPIO3 (1 << 3)
+#define GPIO4 (1 << 4)
+#define GPIO5 (1 << 5)
+#define GPIO6 (1 << 6)
+#define GPIO7 (1 << 7)
+#define GPIO_ALL 0xff
+/** @} */
+
+/* =============================================================================
+ * GPIO registers
+ * ---------------------------------------------------------------------------*/
+
+/* GPIO Data */
+#define GPIO_DATA(port) (&MMIO32(port + 0x000))
+
+/* GPIO Direction */
+#define GPIO_DIR(port) MMIO32(port + 0x400)
+
+/* GPIO Interrupt Sense */
+#define GPIO_IS(port) MMIO32(port + 0x404)
+
+/* GPIO Interrupt Both Edges */
+#define GPIO_IBE(port) MMIO32(port + 0x408)
+
+/* GPIO Interrupt Event */
+#define GPIO_IEV(port) MMIO32(port + 0x40c)
+
+/* GPIO Interrupt Mask */
+#define GPIO_IM(port) MMIO32(port + 0x410)
+
+/* GPIO Raw Interrupt Status */
+#define GPIO_RIS(port) MMIO32(port + 0x414)
+
+/* GPIO Masked Interrupt Status */
+#define GPIO_MIS(port) MMIO32(port + 0x418)
+
+/* GPIO Interrupt Clear */
+#define GPIO_ICR(port) MMIO32(port + 0x41c)
+
+/* GPIO Alternate Function Select */
+#define GPIO_AFSEL(port) MMIO32(port + 0x420)
+
+/* GPIO 2-mA Drive Select */
+#define GPIO_DR2R(port) MMIO32(port + 0x500)
+
+/* GPIO 4-mA Drive Select */
+#define GPIO_DR4R(port) MMIO32(port + 0x504)
+
+/* GPIO 8-mA Drive Select */
+#define GPIO_DR8R(port) MMIO32(port + 0x508)
+
+/* GPIO Open Drain Select */
+#define GPIO_ODR(port) MMIO32(port + 0x50c)
+
+/* GPIO Pull-Up Select */
+#define GPIO_PUR(port) MMIO32(port + 0x510)
+
+/* GPIO Pull-Down Select */
+#define GPIO_PDR(port) MMIO32(port + 0x514)
+
+/* GPIO Slew Rate Control Select */
+#define GPIO_SLR(port) MMIO32(port + 0x518)
+
+/* GPIO Digital Enable */
+#define GPIO_DEN(port) MMIO32(port + 0x51c)
+
+/* GPIO Lock */
+#define GPIO_LOCK(port) MMIO32(port + 0x520)
+
+/* GPIO Commit */
+#define GPIO_CR(port) MMIO32(port + 0x524)
+
+/* GPIO Analog Mode Select */
+#define GPIO_AMSEL(port) MMIO32(port + 0x528)
+
+/* GPIO Port Control */
+#define GPIO_PCTL(port) MMIO32(port + 0x52C)
+
+/* GPIO ADC Control */
+#define GPIO_ADCCTL(port) MMIO32(port + 0x530)
+
+/* GPIO DMA Control */
+#define GPIO_DMACTL(port) MMIO32(port + 0x534)
+
+/* GPIO Peripheral Identification */
+#define GPIO_PERIPH_ID4(port) MMIO32(port + 0xFD0)
+#define GPIO_PERIPH_ID5(port) MMIO32(port + 0xFD4)
+#define GPIO_PERIPH_ID6(port) MMIO32(port + 0xFD8)
+#define GPIO_PERIPH_ID7(port) MMIO32(port + 0xFDC)
+#define GPIO_PERIPH_ID0(port) MMIO32(port + 0xFE0)
+#define GPIO_PERIPH_ID1(port) MMIO32(port + 0xFE4)
+#define GPIO_PERIPH_ID2(port) MMIO32(port + 0xFE8)
+#define GPIO_PERIPH_ID3(port) MMIO32(port + 0xFEC)
+
+/* GPIO PrimeCell Identification */
+#define GPIO_PCELL_ID0(port) MMIO32(port + 0xFF0)
+#define GPIO_PCELL_ID1(port) MMIO32(port + 0xFF4)
+#define GPIO_PCELL_ID2(port) MMIO32(port + 0xFF8)
+#define GPIO_PCELL_ID3(port) MMIO32(port + 0xFFC)
+
+/* =============================================================================
+ * Convenience enums
+ * ---------------------------------------------------------------------------*/
+enum gpio_mode {
+ GPIO_MODE_OUTPUT, /**< Configure pin as output */
+ GPIO_MODE_INPUT, /**< Configure pin as input */
+ GPIO_MODE_ANALOG, /**< Configure pin as analog function */
+};
+
+enum gpio_pullup {
+ GPIO_PUPD_NONE, /**< Do not pull the pin high or low */
+ GPIO_PUPD_PULLUP, /**< Pull the pin high */
+ GPIO_PUPD_PULLDOWN, /**< Pull the pin low */
+};
+
+enum gpio_output_type {
+ GPIO_OTYPE_PP, /**< Push-pull configuration */
+ GPIO_OTYPE_OD, /**< Open drain configuration */
+};
+
+enum gpio_drive_strength {
+ GPIO_DRIVE_2MA, /**< 2mA drive */
+ GPIO_DRIVE_4MA, /**< 4mA drive */
+ GPIO_DRIVE_8MA, /**< 8mA drive */
+ GPIO_DRIVE_8MA_SLEW_CTL,/**< 8mA drive with slew rate control */
+};
+
+enum gpio_trigger {
+ GPIO_TRIG_LVL_LOW, /**< Level trigger, signal low */
+ GPIO_TRIG_LVL_HIGH, /**< Level trigger, signal high */
+ GPIO_TRIG_EDGE_FALL, /**< Falling edge trigger */
+ GPIO_TRIG_EDGE_RISE, /**< Rising edge trigger*/
+ GPIO_TRIG_EDGE_BOTH, /**< Falling and Rising edges trigger*/
+};
+/* =============================================================================
+ * Function prototypes
+ * ---------------------------------------------------------------------------*/
+BEGIN_DECLS
+
+void gpio_enable_ahb_aperture(void);
+void gpio_mode_setup(uint32_t gpioport, enum gpio_mode mode,
+ enum gpio_pullup pullup, uint8_t gpios);
+void gpio_set_output_config(uint32_t gpioport, enum gpio_output_type otype,
+ enum gpio_drive_strength drive, uint8_t gpios);
+void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint8_t gpios);
+
+void gpio_toggle(uint32_t gpioport, uint8_t gpios);
+void gpio_unlock_commit(uint32_t gpioport, uint8_t gpios);
+
+/* Let's keep these ones inlined. GPIO control should be fast */
+/** @ingroup gpio_control
+ * @{ */
+
+/**
+ * \brief Get status of a Group of Pins (atomic)
+ *
+ * Reads the level of the given pins. Bit 0 of the returned data corresponds to
+ * GPIO0 level, bit 1 to GPIO1 level. and so on. Bits corresponding to masked
+ * pins (corresponding bit of gpios parameter set to zero) are returned as 0.
+ *
+ * This is an atomic operation.
+ *
+ * @param[in] gpioport GPIO block register address base @ref gpio_reg_base
+ * @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified
+ * by OR'ing then together.
+ *
+ * @return The level of the GPIO port. The pins not specified in gpios are
+ * masked to zero.
+ */
+static inline uint8_t gpio_read(uint32_t gpioport, uint8_t gpios)
+{
+ return GPIO_DATA(gpioport)[gpios];
+}
+
+/**
+ * \brief Set level of a Group of Pins (atomic)
+ *
+ * Sets the level of the given pins. Bit 0 of the data parameter corresponds to
+ * GPIO0, bit 1 to GPIO1. and so on. Maskedpins (corresponding bit of gpios
+ * parameter set to zero) are returned not affected.
+ *
+ * This is an atomic operation.
+ *
+ * @param[in] gpioport GPIO block register address base @ref gpio_reg_base
+ * @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified
+ * by OR'ing then together.
+ * @param[in] data Level to set pin to. Bit 0 of data corresponds to GPIO0, bit
+ * 1 to GPIO1. and so on.
+ */
+static inline void gpio_write(uint32_t gpioport, uint8_t gpios, uint8_t data)
+{
+ /* ipaddr[9:2] mask the bits to be set, hence the array index */
+ GPIO_DATA(gpioport)[gpios] = data;
+}
+
+/**
+ * \brief Set a Group of Pins (atomic)
+ *
+ * Set one or more pins of the given GPIO port. This is an atomic operation.
+ *
+ * @param[in] gpioport GPIO block register address base @ref gpio_reg_base
+ * @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified
+ * by OR'ing then together.
+ */
+static inline void gpio_set(uint32_t gpioport, uint8_t gpios)
+{
+ gpio_write(gpioport, gpios, 0xff);
+}
+
+/**
+ * \brief Clear a Group of Pins (atomic)
+ *
+ * Clear one or more pins of the given GPIO port. This is an atomic operation.
+ *
+ * @param[in] gpioport GPIO block register address base @ref gpio_reg_base
+ * @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified
+ * by OR'ing then together.
+ */
+static inline void gpio_clear(uint32_t gpioport, uint8_t gpios)
+{
+ gpio_write(gpioport, gpios, 0);
+}
+
+/**
+ * \brief Read level of all pins from a port (atomic)
+ *
+ * Read the current value of the given GPIO port. This is an atomic operation.
+ *
+ * This is functionally identical to @ref gpio_read (gpioport, GPIO_ALL).
+ *
+ * @param[in] gpioport GPIO block register address base @ref gpio_reg_base
+ *
+ * @return The level of all the pins on the GPIO port.
+ */
+static inline uint8_t gpio_port_read(uint32_t gpioport)
+{
+ return gpio_read(gpioport, GPIO_ALL);
+}
+
+/**
+ * \brief Set level of of all pins from a port (atomic)
+ *
+ * Set the level of all pins on the given GPIO port. This is an atomic
+ * operation.
+ *
+ * This is functionally identical to @ref gpio_write (gpioport, GPIO_ALL, data).
+ *
+ * @param[in] gpioport GPIO block register address base @ref gpio_reg_base
+ * @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified
+ * by OR'ing then together.
+ * @param[in] data Level to set pin to. Bit 0 of data corresponds to GPIO0, bit
+ * 1 to GPIO1. and so on.
+ */
+static inline void gpio_port_write(uint32_t gpioport, uint8_t data)
+{
+ gpio_write(gpioport, GPIO_ALL, data);
+}
+/** @} */
+
+void gpio_configure_trigger(uint32_t gpioport, enum gpio_trigger trigger,
+ uint8_t gpios);
+void gpio_enable_interrupts(uint32_t gpioport, uint8_t gpios);
+void gpio_disable_interrupts(uint32_t gpioport, uint8_t gpios);
+
+
+/* Let's keep these ones inlined. GPIO. They are designed to be used in ISRs */
+/** @ingroup gpio_irq
+ * @{ */
+/** \brief Determine if interrupt is generated by the given pin
+ *
+ * @param[in] gpioport GPIO block register address base @ref gpio_reg_base
+ * @param[in] srcpins source pin or group of pins to check.
+ */
+static inline bool gpio_is_interrupt_source(uint32_t gpioport, uint8_t srcpins)
+{
+ return GPIO_MIS(gpioport) & srcpins;
+}
+
+/**
+ * \brief Mark interrupt as serviced
+ *
+ * After an interrupt is services, its flag must be cleared. If the flag is not
+ * cleared, then execution will jump back to the start of the ISR after the ISR
+ * returns.
+ *
+ * @param[in] gpioport GPIO block register address base @ref gpio_reg_base
+ * @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified
+ * by OR'ing then together.
+ */
+static inline void gpio_clear_interrupt_flag(uint32_t gpioport, uint8_t gpios)
+{
+ GPIO_ICR(gpioport) |= gpios;
+}
+
+/** @} */
+END_DECLS
+
+#endif
+
+/**@}*/
+
diff --git a/libopencm3/include/libopencm3/lm4f/memorymap.h b/libopencm3/include/libopencm3/lm4f/memorymap.h
new file mode 100644
index 0000000..9a20f6d
--- /dev/null
+++ b/libopencm3/include/libopencm3/lm4f/memorymap.h
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Gareth McMullin
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LM4F_MEMORYMAP_H
+#define LM4F_MEMORYMAP_H
+
+#include
+
+/* --- LM4F specific peripheral definitions ----------------------------- */
+
+#define GPIOA_APB_BASE (0x40004000U)
+#define GPIOB_APB_BASE (0x40005000U)
+#define GPIOC_APB_BASE (0x40006000U)
+#define GPIOD_APB_BASE (0x40007000U)
+#define GPIOE_APB_BASE (0x40024000U)
+#define GPIOF_APB_BASE (0x40025000U)
+#define GPIOG_APB_BASE (0x40026000U)
+#define GPIOH_APB_BASE (0x40027000U)
+#define GPIOJ_APB_BASE (0x4003D000U)
+
+#define GPIOA_BASE (0x40058000U)
+#define GPIOB_BASE (0x40059000U)
+#define GPIOC_BASE (0x4005A000U)
+#define GPIOD_BASE (0x4005B000U)
+#define GPIOE_BASE (0x4005C000U)
+#define GPIOF_BASE (0x4005D000U)
+#define GPIOG_BASE (0x4005E000U)
+#define GPIOH_BASE (0x4005F000U)
+#define GPIOJ_BASE (0x40060000U)
+#define GPIOK_BASE (0x40061000U)
+#define GPIOL_BASE (0x40062000U)
+#define GPIOM_BASE (0x40063000U)
+#define GPION_BASE (0x40064000U)
+#define GPIOP_BASE (0x40065000U)
+#define GPIOQ_BASE (0x40066000U)
+
+#define UART0_BASE (0x4000C000U)
+#define UART1_BASE (0x4000D000U)
+#define UART2_BASE (0x4000E000U)
+#define UART3_BASE (0x4000F000U)
+#define UART4_BASE (0x40010000U)
+#define UART5_BASE (0x40011000U)
+#define UART6_BASE (0x40012000U)
+#define UART7_BASE (0x40013000U)
+
+#define SSI0_BASE (0x40008000U)
+#define SSI1_BASE (0x40009000U)
+#define SSI2_BASE (0x4000A000U)
+#define SSI3_BASE (0x4000B000U)
+
+#define USB_BASE (0x40050000U)
+
+#define SYSCTL_BASE (0x400FE000U)
+
+#endif
diff --git a/libopencm3/include/libopencm3/lm4f/rcc.h b/libopencm3/include/libopencm3/lm4f/rcc.h
new file mode 100644
index 0000000..98a92cf
--- /dev/null
+++ b/libopencm3/include/libopencm3/lm4f/rcc.h
@@ -0,0 +1,133 @@
+/** @defgroup rcc_defines Reset and Clock Control
+
+@brief Defined Constants and Types for the LM4F Reset and Clock Control
+
+@ingroup LM4Fxx_defines
+
+@version 1.0.0
+
+@author @htmlonly © @endhtmlonly 2012
+Alexandru Gagniuc
+
+@date 10 March 2013
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Alexandru Gagniuc
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LM4F_RCC_H
+#define LM4F_RCC_H
+
+/**@{*/
+
+#include
+
+/**
+ * \brief Oscillator source values
+ *
+ * Possible values of the oscillator source.
+ */
+enum osc_src {
+ OSCSRC_MOSC = SYSCTL_RCC2_OSCSRC2_MOSC,
+ OSCSRC_PIOSC = SYSCTL_RCC2_OSCSRC2_PIOSC,
+ OSCSRC_PIOSC_D4 = SYSCTL_RCC2_OSCSRC2_PIOSC_D4,
+ OSCSRC_30K_INT = SYSCTL_RCC2_OSCSRC2_30K,
+ OSCSRC_32K_EXT = SYSCTL_RCC2_OSCSRC2_32K768,
+};
+
+/**
+ * \brief PWM clock divisor values
+ *
+ * Possible values of the binary divisor used to predivide the system clock down
+ * for use as the timing reference for the PWM module.
+ */
+enum pwm_clkdiv {
+ PWMDIV_2 = SYSCTL_RCC_PWMDIV_2,
+ PWMDIV_4 = SYSCTL_RCC_PWMDIV_4,
+ PWMDIV_8 = SYSCTL_RCC_PWMDIV_8,
+ PWMDIV_16 = SYSCTL_RCC_PWMDIV_16,
+ PWMDIV_32 = SYSCTL_RCC_PWMDIV_32,
+ PWMDIV_64 = SYSCTL_RCC_PWMDIV_64,
+};
+
+/**
+ * \brief Predefined crystal values
+ *
+ * Predefined crystal values for the XTAL field in SYSCTL_RCC.
+ * Using these predefined values in the XTAL field, the SYSCTL_PLLFREQ0 and
+ * SYSCTL_PLLFREQ1 are automatically adjusted in hardware to provide a PLL clock
+ * of 400MHz.
+ */
+enum xtal_t {
+ XTAL_4M = SYSCTL_RCC_XTAL_4M,
+ XTAL_4M_096 = SYSCTL_RCC_XTAL_4M_096,
+ XTAL_4M_9152 = SYSCTL_RCC_XTAL_4M_9152,
+ XTAL_5M = SYSCTL_RCC_XTAL_5M,
+ XTAL_5M_12 = SYSCTL_RCC_XTAL_5M_12,
+ XTAL_6M = SYSCTL_RCC_XTAL_6M,
+ XTAL_6M_144 = SYSCTL_RCC_XTAL_6M_144,
+ XTAL_7M_3728 = SYSCTL_RCC_XTAL_7M_3728,
+ XTAL_8M = SYSCTL_RCC_XTAL_8M,
+ XTAL_8M_192 = SYSCTL_RCC_XTAL_8M_192,
+ XTAL_10M = SYSCTL_RCC_XTAL_10M,
+ XTAL_12M = SYSCTL_RCC_XTAL_12M,
+ XTAL_12M_288 = SYSCTL_RCC_XTAL_12M_288,
+ XTAL_13M_56 = SYSCTL_RCC_XTAL_13M_56,
+ XTAL_14M_31818 = SYSCTL_RCC_XTAL_14M_31818,
+ XTAL_16M = SYSCTL_RCC_XTAL_16M,
+ XTAL_16M_384 = SYSCTL_RCC_XTAL_16M_384,
+ XTAL_18M = SYSCTL_RCC_XTAL_18M,
+ XTAL_20M = SYSCTL_RCC_XTAL_20M,
+ XTAL_24M = SYSCTL_RCC_XTAL_24M,
+ XTAL_25M = SYSCTL_RCC_XTAL_25M,
+};
+
+/* =============================================================================
+ * Function prototypes
+ * ---------------------------------------------------------------------------*/
+BEGIN_DECLS
+/* Low-level clock API */
+void rcc_configure_xtal(enum xtal_t xtal);
+void rcc_disable_main_osc(void);
+void rcc_disable_interal_osc(void);
+void rcc_enable_main_osc(void);
+void rcc_enable_interal_osc(void);
+void rcc_enable_rcc2(void);
+void rcc_pll_off(void);
+void rcc_pll_on(void);
+void rcc_set_osc_source(enum osc_src src);
+void rcc_pll_bypass_disable(void);
+void rcc_pll_bypass_enable(void);
+void rcc_set_pll_divisor(uint8_t div400);
+void rcc_set_pwm_divisor(enum pwm_clkdiv div);
+void rcc_usb_pll_off(void);
+void rcc_usb_pll_on(void);
+void rcc_wait_for_pll_ready(void);
+/* High-level clock API */
+void rcc_change_pll_divisor(uint8_t plldiv400);
+uint32_t rcc_get_system_clock_frequency(void);
+void rcc_sysclk_config(enum osc_src src, enum xtal_t xtal, uint8_t pll_div400);
+
+END_DECLS
+
+/**@}*/
+
+#endif /* LM4F_RCC_H */
diff --git a/libopencm3/include/libopencm3/lm4f/ssi.h b/libopencm3/include/libopencm3/lm4f/ssi.h
new file mode 100644
index 0000000..be9e4a8
--- /dev/null
+++ b/libopencm3/include/libopencm3/lm4f/ssi.h
@@ -0,0 +1,118 @@
+/** @defgroup ssi_defines Synchronous Serial Interface
+ *
+ * @brief Defined Constants and Types for the LM4F Synchronous Serial Interface (SSI)
+ *
+ * @ingroup LM4Fxx_defines
+ *
+ * @version 1.0.0
+ *
+ * @author @htmlonly © @endhtmlonly 2014
+ * Tiago Costa
+ *
+ * @date 11 June 2014
+ *
+ * LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2014 Tiago Costa
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LM4F_SSI_H
+#define LM4F_SSI_H
+
+/**@{*/
+
+#include
+#include
+
+/* =============================================================================
+ * Convenience macros
+ * ---------------------------------------------------------------------------*/
+/** @defgroup ssi_base SSI register base addresses
+ * @{*/
+#define SSI0 SSI0_BASE
+#define SSI1 SSI1_BASE
+#define SSI2 SSI2_BASE
+#define SSI3 SSI3_BASE
+/** @} */
+
+/* =============================================================================
+ * SSI registers
+ * ---------------------------------------------------------------------------*/
+
+/* SSI Control 0 */
+#define SSI_CR0(port) MMIO32(port + 0x000)
+
+/* SSI Control 1 */
+#define SSI_CR1(port) MMIO32(port + 0x004)
+
+/* SSI Data */
+#define SSI_DR(port) MMIO32(port + 0x008)
+
+/* SSI Satus */
+#define SSI_SR(port) MMIO32(port + 0x00C)
+
+/* SSI Clock Prescale */
+#define SSI_CPSR(port) MMIO32(port + 0x010)
+
+/* SSI Interrupt Mask */
+#define SSI_IM(port) MMIO32(port + 0x014)
+
+/* SSI Raw Interrupt Status */
+#define SSI_RIS(port) MMIO32(port + 0x018)
+
+/* SSI Masked Interrupt Status */
+#define SSI_MIS(port) MMIO32(port + 0x01C)
+
+/* SSI Interrupt Clear */
+#define SSI_ICR(port) MMIO32(port + 0x020)
+
+/* SSI DMA Control */
+#define SSI_DMACTL(port) MMIO32(port + 0x024)
+
+/* SSI Clock Configuration */
+#define SSI_CC(port) MMIO32(port + 0xFC8)
+
+/* SSI Peripheral Identification */
+#define SSI_PERIPH_ID4(port) MMIO32(port + 0xFD0)
+#define SSI_PERIPH_ID5(port) MMIO32(port + 0xFD4)
+#define SSI_PERIPH_ID6(port) MMIO32(port + 0xFD8)
+#define SSI_PERIPH_ID7(port) MMIO32(port + 0xFDC)
+#define SSI_PERIPH_ID0(port) MMIO32(port + 0xFE0)
+#define SSI_PERIPH_ID1(port) MMIO32(port + 0xFE4)
+#define SSI_PERIPH_ID2(port) MMIO32(port + 0xFE8)
+#define SSI_PERIPH_ID3(port) MMIO32(port + 0xFEC)
+
+/* SSI PrimeCell Identification */
+#define SSI_PCELL_ID0(port) MMIO32(port + 0xFF0)
+#define SSI_PCELL_ID1(port) MMIO32(port + 0xFF4)
+#define SSI_PCELL_ID2(port) MMIO32(port + 0xFF8)
+#define SSI_PCELL_ID3(port) MMIO32(port + 0xFFC)
+
+/* =============================================================================
+ * Function prototypes
+ * ---------------------------------------------------------------------------*/
+BEGIN_DECLS
+
+END_DECLS
+
+/**@}*/
+
+#endif /* LM4F_SSI_H */
+
\ No newline at end of file
diff --git a/libopencm3/include/libopencm3/lm4f/systemcontrol.h b/libopencm3/include/libopencm3/lm4f/systemcontrol.h
new file mode 100644
index 0000000..62e2231
--- /dev/null
+++ b/libopencm3/include/libopencm3/lm4f/systemcontrol.h
@@ -0,0 +1,743 @@
+/** @defgroup systemcontrol_defines System Control
+
+@brief Defined Constants and Types for the LM4F System Control
+
+@ingroup LM4Fxx_defines
+
+@version 1.0.0
+
+@author @htmlonly © @endhtmlonly 2012
+Alexandru Gagniuc
+
+@date 10 March 2013
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Alexandru Gagniuc
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LM4F_SYSTEMCONTROL_H
+#define LM4F_SYSTEMCONTROL_H
+
+/**@{*/
+
+#include
+#include
+
+#define SYSCTL_DID0 MMIO32(SYSCTL_BASE + 0x000)
+#define SYSCTL_DID1 MMIO32(SYSCTL_BASE + 0x004)
+#define SYSCTL_PBORCTL MMIO32(SYSCTL_BASE + 0x030)
+#define SYSCTL_LDORCTL MMIO32(SYSCTL_BASE + 0x034)
+#define SYSCTL_RIS MMIO32(SYSCTL_BASE + 0x050)
+#define SYSCTL_IMC MMIO32(SYSCTL_BASE + 0x054)
+#define SYSCTL_MISC MMIO32(SYSCTL_BASE + 0x058)
+#define SYSCTL_RESC MMIO32(SYSCTL_BASE + 0x05C)
+#define SYSCTL_RCC MMIO32(SYSCTL_BASE + 0x060)
+#define SYSCTL_PLLCFG MMIO32(SYSCTL_BASE + 0x064)
+#define SYSCTL_GPIOHBCTL MMIO32(SYSCTL_BASE + 0x06C)
+#define SYSCTL_RCC2 MMIO32(SYSCTL_BASE + 0x070)
+#define SYSCTL_MOSCCTL MMIO32(SYSCTL_BASE + 0x07C)
+#define SYSCTL_DSLPCLKCFG MMIO32(SYSCTL_BASE + 0x144)
+#define SYSCTL_SYSPROP MMIO32(SYSCTL_BASE + 0x14C)
+#define SYSCTL_PIOSCCAL MMIO32(SYSCTL_BASE + 0x150)
+#define SYSCTL_PIOSCSTAT MMIO32(SYSCTL_BASE + 0x154)
+#define SYSCTL_PLLFREQ0 MMIO32(SYSCTL_BASE + 0x160)
+#define SYSCTL_PLLFREQ1 MMIO32(SYSCTL_BASE + 0x164)
+#define SYSCTL_PLLSTAT MMIO32(SYSCTL_BASE + 0x168)
+/* Peripheral present */
+#define SYSCTL_PPWD MMIO32(SYSCTL_BASE + 0x300)
+#define SYSCTL_PPTIMER MMIO32(SYSCTL_BASE + 0x304)
+#define SYSCTL_PPGPIO MMIO32(SYSCTL_BASE + 0x308)
+#define SYSCTL_PPDMA MMIO32(SYSCTL_BASE + 0x30C)
+#define SYSCTL_PPHIB MMIO32(SYSCTL_BASE + 0x314)
+#define SYSCTL_PPUART MMIO32(SYSCTL_BASE + 0x318)
+#define SYSCTL_PPSSI MMIO32(SYSCTL_BASE + 0x31C)
+#define SYSCTL_PPI2C MMIO32(SYSCTL_BASE + 0x320)
+#define SYSCTL_PPUSB MMIO32(SYSCTL_BASE + 0x328)
+#define SYSCTL_PPCAN MMIO32(SYSCTL_BASE + 0x334)
+#define SYSCTL_PPADC MMIO32(SYSCTL_BASE + 0x338)
+#define SYSCTL_PPACMP MMIO32(SYSCTL_BASE + 0x33C)
+#define SYSCTL_PPPWM MMIO32(SYSCTL_BASE + 0x340)
+#define SYSCTL_PPQEI MMIO32(SYSCTL_BASE + 0x344)
+#define SYSCTL_PPEEPROM MMIO32(SYSCTL_BASE + 0x358)
+#define SYSCTL_PPWTIMER MMIO32(SYSCTL_BASE + 0x35C)
+/* Peripheral software reset */
+#define SYSCTL_SRWD MMIO32(SYSCTL_BASE + 0x500)
+#define SYSCTL_SRTIMER MMIO32(SYSCTL_BASE + 0x504)
+#define SYSCTL_SRGPIO MMIO32(SYSCTL_BASE + 0x508)
+#define SYSCTL_SRDMA MMIO32(SYSCTL_BASE + 0x50C)
+#define SYSCTL_SRHIB MMIO32(SYSCTL_BASE + 0x514)
+#define SYSCTL_SRUART MMIO32(SYSCTL_BASE + 0x518)
+#define SYSCTL_SRSSI MMIO32(SYSCTL_BASE + 0x51C)
+#define SYSCTL_SRI2C MMIO32(SYSCTL_BASE + 0x520)
+#define SYSCTL_SRUSB MMIO32(SYSCTL_BASE + 0x528)
+#define SYSCTL_SRCAN MMIO32(SYSCTL_BASE + 0x534)
+#define SYSCTL_SRADC MMIO32(SYSCTL_BASE + 0x538)
+#define SYSCTL_SRACMP MMIO32(SYSCTL_BASE + 0x53C)
+#define SYSCTL_SRPWM MMIO32(SYSCTL_BASE + 0x540)
+#define SYSCTL_SRQEI MMIO32(SYSCTL_BASE + 0x544)
+#define SYSCTL_SREEPROM MMIO32(SYSCTL_BASE + 0x558)
+#define SYSCTL_SRWTIMER MMIO32(SYSCTL_BASE + 0x55C)
+/* Peripheral run mode clock gating control */
+#define SYSCTL_RCGCWD MMIO32(SYSCTL_BASE + 0x600)
+#define SYSCTL_RCGCTIMER MMIO32(SYSCTL_BASE + 0x604)
+#define SYSCTL_RCGCGPIO MMIO32(SYSCTL_BASE + 0x608)
+#define SYSCTL_RCGCDMA MMIO32(SYSCTL_BASE + 0x60C)
+#define SYSCTL_RCGCHIB MMIO32(SYSCTL_BASE + 0x614)
+#define SYSCTL_RCGCUART MMIO32(SYSCTL_BASE + 0x618)
+#define SYSCTL_RCGCSSI MMIO32(SYSCTL_BASE + 0x61C)
+#define SYSCTL_RCGCI2C MMIO32(SYSCTL_BASE + 0x620)
+#define SYSCTL_RCGCUSB MMIO32(SYSCTL_BASE + 0x628)
+#define SYSCTL_RCGCCAN MMIO32(SYSCTL_BASE + 0x634)
+#define SYSCTL_RCGCADC MMIO32(SYSCTL_BASE + 0x638)
+#define SYSCTL_RCGCACMP MMIO32(SYSCTL_BASE + 0x63C)
+#define SYSCTL_RCGCPWM MMIO32(SYSCTL_BASE + 0x640)
+#define SYSCTL_RCGCQEI MMIO32(SYSCTL_BASE + 0x644)
+#define SYSCTL_RCGCEEPROM MMIO32(SYSCTL_BASE + 0x658)
+#define SYSCTL_RCGCWTIMER MMIO32(SYSCTL_BASE + 0x65C)
+/* Peripheral sleep mode clock gating control */
+#define SYSCTL_SCGCWD MMIO32(SYSCTL_BASE + 0x700)
+#define SYSCTL_SCGCTIMER MMIO32(SYSCTL_BASE + 0x704)
+#define SYSCTL_SCGCGPIO MMIO32(SYSCTL_BASE + 0x708)
+#define SYSCTL_SCGCDMA MMIO32(SYSCTL_BASE + 0x70C)
+#define SYSCTL_SCGCHIB MMIO32(SYSCTL_BASE + 0x714)
+#define SYSCTL_SCGCUART MMIO32(SYSCTL_BASE + 0x718)
+#define SYSCTL_SCGCSSI MMIO32(SYSCTL_BASE + 0x71C)
+#define SYSCTL_SCGCI2C MMIO32(SYSCTL_BASE + 0x720)
+#define SYSCTL_SCGCUSB MMIO32(SYSCTL_BASE + 0x728)
+#define SYSCTL_SCGCCAN MMIO32(SYSCTL_BASE + 0x734)
+#define SYSCTL_SCGCADC MMIO32(SYSCTL_BASE + 0x738)
+#define SYSCTL_SCGCACMP MMIO32(SYSCTL_BASE + 0x73C)
+#define SYSCTL_SCGCPWM MMIO32(SYSCTL_BASE + 0x740)
+#define SYSCTL_SCGCQEI MMIO32(SYSCTL_BASE + 0x744)
+#define SYSCTL_SCGCEEPROM MMIO32(SYSCTL_BASE + 0x758)
+#define SYSCTL_SCGCWTIMER MMIO32(SYSCTL_BASE + 0x75C)
+/* Peripheral deep-sleep mode clock gating control */
+#define SYSCTL_DCGCWD MMIO32(SYSCTL_BASE + 0x800)
+#define SYSCTL_DCGCTIMER MMIO32(SYSCTL_BASE + 0x804)
+#define SYSCTL_DCGCGPIO MMIO32(SYSCTL_BASE + 0x808)
+#define SYSCTL_DCGCDMA MMIO32(SYSCTL_BASE + 0x80C)
+#define SYSCTL_DCGCHIB MMIO32(SYSCTL_BASE + 0x814)
+#define SYSCTL_DCGCUART MMIO32(SYSCTL_BASE + 0x818)
+#define SYSCTL_DCGCSSI MMIO32(SYSCTL_BASE + 0x81C)
+#define SYSCTL_DCGCI2C MMIO32(SYSCTL_BASE + 0x820)
+#define SYSCTL_DCGCUSB MMIO32(SYSCTL_BASE + 0x828)
+#define SYSCTL_DCGCCAN MMIO32(SYSCTL_BASE + 0x834)
+#define SYSCTL_DCGCADC MMIO32(SYSCTL_BASE + 0x838)
+#define SYSCTL_DCGCACMP MMIO32(SYSCTL_BASE + 0x83C)
+#define SYSCTL_DCGCPWM MMIO32(SYSCTL_BASE + 0x840)
+#define SYSCTL_DCGCQEI MMIO32(SYSCTL_BASE + 0x844)
+#define SYSCTL_DCGCEEPROM MMIO32(SYSCTL_BASE + 0x858)
+#define SYSCTL_DCGCWTIMER MMIO32(SYSCTL_BASE + 0x85C)
+/* Peripheral ready */
+#define SYSCTL_PRWD MMIO32(SYSCTL_BASE + 0xA00)
+#define SYSCTL_PRTIMER MMIO32(SYSCTL_BASE + 0xA04)
+#define SYSCTL_PRGPIO MMIO32(SYSCTL_BASE + 0xA08)
+#define SYSCTL_PRDMA MMIO32(SYSCTL_BASE + 0xA0C)
+#define SYSCTL_PRHIB MMIO32(SYSCTL_BASE + 0xA14)
+#define SYSCTL_PRUART MMIO32(SYSCTL_BASE + 0xA18)
+#define SYSCTL_PRSSI MMIO32(SYSCTL_BASE + 0xA1C)
+#define SYSCTL_PRI2C MMIO32(SYSCTL_BASE + 0xA20)
+#define SYSCTL_PRUSB MMIO32(SYSCTL_BASE + 0xA28)
+#define SYSCTL_PRCAN MMIO32(SYSCTL_BASE + 0xA34)
+#define SYSCTL_PRADC MMIO32(SYSCTL_BASE + 0xA38)
+#define SYSCTL_PRACMP MMIO32(SYSCTL_BASE + 0xA3C)
+#define SYSCTL_PRPWM MMIO32(SYSCTL_BASE + 0xA40)
+#define SYSCTL_PRQEI MMIO32(SYSCTL_BASE + 0xA44)
+#define SYSCTL_PREEPROM MMIO32(SYSCTL_BASE + 0xA58)
+#define SYSCTL_PRWTIMER MMIO32(SYSCTL_BASE + 0xA5C)
+/* =============================================================================
+ * System Control Legacy Registers
+ * ---------------------------------------------------------------------------*/
+#ifdef LM4F_LEGACY_SYSCTL
+#define SYSCTL_DC0 MMIO32(SYSCTL_BASE + 0x008)
+#define SYSCTL_DC1 MMIO32(SYSCTL_BASE + 0x010)
+#define SYSCTL_DC2 MMIO32(SYSCTL_BASE + 0x014)
+#define SYSCTL_DC3 MMIO32(SYSCTL_BASE + 0x018)
+#define SYSCTL_DC4 MMIO32(SYSCTL_BASE + 0x01C)
+#define SYSCTL_DC5 MMIO32(SYSCTL_BASE + 0x020)
+#define SYSCTL_DC6 MMIO32(SYSCTL_BASE + 0x024)
+#define SYSCTL_DC7 MMIO32(SYSCTL_BASE + 0x028)
+#define SYSCTL_DC8 MMIO32(SYSCTL_BASE + 0x02C)
+#define SYSCTL_SRCR0 MMIO32(SYSCTL_BASE + 0x040)
+#define SYSCTL_SRCR1 MMIO32(SYSCTL_BASE + 0x044)
+#define SYSCTL_SRCR2 MMIO32(SYSCTL_BASE + 0x048)
+#define SYSCTL_RCGC0 MMIO32(SYSCTL_BASE + 0x100)
+#define SYSCTL_RCGC1 MMIO32(SYSCTL_BASE + 0x104)
+#define SYSCTL_RCGC2 MMIO32(SYSCTL_BASE + 0x108)
+#define SYSCTL_SCGC0 MMIO32(SYSCTL_BASE + 0x110)
+#define SYSCTL_SCGC1 MMIO32(SYSCTL_BASE + 0x114)
+#define SYSCTL_SCGC2 MMIO32(SYSCTL_BASE + 0x118)
+#define SYSCTL_DCGC0 MMIO32(SYSCTL_BASE + 0x120)
+#define SYSCTL_DCGC1 MMIO32(SYSCTL_BASE + 0x124)
+#define SYSCTL_DCGC2 MMIO32(SYSCTL_BASE + 0x128)
+#define SYSCTL_DC9 MMIO32(SYSCTL_BASE + 0x190)
+#define SYSCTL_NVMSTAT MMIO32(SYSCTL_BASE + 0x1A0)
+#endif /* LM4F_LEGACY_SYSCTL */
+
+/* =============================================================================
+ * SYSCTL_DID0 values
+ * ---------------------------------------------------------------------------*/
+/** DID0 version */
+#define SYSCTL_DID0_VER_MASK (7 << 28)
+/** Device class */
+#define SYSCTL_DID0_CLASS_MASK (0xFF << 16)
+/** Major revision */
+#define SYSCTL_DID0_MAJOR_MASK (0xFF << 8)
+/** Minor revision */
+#define SYSCTL_DID0_MAJOR_MASK (0xFF << 8)
+
+/* =============================================================================
+ * SYSCTL_DID1 values
+ * ---------------------------------------------------------------------------*/
+/** DID1 version */
+#define SYSCTL_DID1_VER_MASK (0xF << 28)
+/** Family */
+#define SYSCTL_DID1_FAM_MASK (0xF << 24)
+/** Part number */
+#define SYSCTL_DID1_PARTNO_MASK (0xFF << 16)
+/** Pin count */
+#define SYSCTL_DID1_PINCOUNT_MASK (0x7 << 13)
+#define SYSCTL_DID1_PINCOUNT_28P (0x0 << 13)
+#define SYSCTL_DID1_PINCOUNT_48P (0x1 << 13)
+#define SYSCTL_DID1_PINCOUNT_100P (0x2 << 13)
+#define SYSCTL_DID1_PINCOUNT_64P (0x3 << 13)
+#define SYSCTL_DID1_PINCOUNT_144P (0x4 << 13)
+#define SYSCTL_DID1_PINCOUNT_157P (0x5 << 13)
+/** Temperature range */
+#define SYSCTL_DID1_TEMP_MASK (0x7 << 5)
+#define SYSCTL_DID1_TEMP_0_70 (0x0 << 5)
+#define SYSCTL_DID1_TEMP_M40_85 (0x1 << 5)
+#define SYSCTL_DID1_TEMP_M40_105 (0x2 << 5)
+/** Package */
+#define SYSCTL_DID1_PKG_MASK (0x3 << 5)
+#define SYSCTL_DID1_PKG_SOIC (0x0 << 5)
+#define SYSCTL_DID1_PKG_LQFP (0x1 << 5)
+#define SYSCTL_DID1_PKG_BGA (0x2 << 5)
+/** ROHS compliance */
+#define SYSCTL_DID1_ROHS (1 << 2)
+/** Qualification status */
+#define SYSCTL_DID1_QUAL_MASK (3 << 0)
+
+/* =============================================================================
+ * SYSCTL_PBORCTL values
+ * ---------------------------------------------------------------------------*/
+/** BOR interrupt or reset */
+#define SYSCTL_PBORCTL_BORIOR (1 << 1)
+
+/* =============================================================================
+ * SYSCTL_RIS values
+ * ---------------------------------------------------------------------------*/
+/** MOSC Power Up Raw Interrupt Status */
+#define SYSCTL_RIS_MOSCPUPRIS (1 << 8)
+/** USB PLL Lock Raw Interrupt Status */
+#define SYSCTL_RIS_USBPLLLRIS (1 << 7)
+/** PLL Lock Raw Interrupt Status */
+#define SYSCTL_RIS_PLLLRIS (1 << 6)
+/** Main Oscillator Failure Raw Interrupt Status */
+#define SYSCTL_RIS_MOFRIS (1 << 3)
+/** Brown-Out Reset Raw Interrupt Status */
+#define SYSCTL_RIS_BORRIS (1 << 1)
+
+/* =============================================================================
+ * SYSCTL_IMC values
+ * ---------------------------------------------------------------------------*/
+/** MOSC Power Up Raw Interrupt Status */
+#define SYSCTL_IMC_MOSCPUPIM (1 << 8)
+/** USB PLL Lock Raw Interrupt Status */
+#define SYSCTL_IMC_USBPLLLIM (1 << 7)
+/** PLL Lock Raw Interrupt Status */
+#define SYSCTL_IMC_PLLLIM (1 << 6)
+/** Main Oscillator Failure Raw Interrupt Status */
+#define SYSCTL_IMC_MOFIM (1 << 3)
+/** Brown-Out Reset Raw Interrupt Status */
+#define SYSCTL_IMC_BORIM (1 << 1)
+
+/* =============================================================================
+ * SYSCTL_MISC values
+ * ---------------------------------------------------------------------------*/
+/** MOSC Power Up Raw Interrupt Status */
+#define SYSCTL_MISC_MOSCPUPMIS (1 << 8)
+/** USB PLL Lock Raw Interrupt Status */
+#define SYSCTL_MISC_USBPLLLMIS (1 << 7)
+/** PLL Lock Raw Interrupt Status */
+#define SYSCTL_MISC_PLLLMIS (1 << 6)
+/** Main Oscillator Failure Raw Interrupt Status */
+#define SYSCTL_MISC_MOFMIS (1 << 3)
+/** Brown-Out Reset Raw Interrupt Status */
+#define SYSCTL_MISC_BORMIS (1 << 1)
+
+/* =============================================================================
+ * SYSCTL_RESC values
+ * ---------------------------------------------------------------------------*/
+/** MOSC Failure Reset */
+#define SYSCTL_RESC_MOSCFAIL (1 << 18)
+/** Watchdog Timer 1 Reset */
+#define SYSCTL_RESC_WDT1 (1 << 5)
+/** Software Reset */
+#define SYSCTL_RESC_SW (1 << 4)
+/** Watchdog Timer 0 Reset */
+#define SYSCTL_RESC_WDT0 (1 << 3)
+/** Brown-Out Reset */
+#define SYSCTL_RESC_BOR (1 << 2)
+/** Power-On Reset */
+#define SYSCTL_RESC_POR (1 << 1)
+/** External Reset */
+#define SYSCTL_RESC_EXT (1 << 0)
+
+/* =============================================================================
+ * SYSCTL_RCC values
+ * ---------------------------------------------------------------------------*/
+/** Auto Clock Gating */
+#define SYSCTL_RCC_ACG (1 << 27)
+/** System Clock Divisor */
+#define SYSCTL_RCC_SYSDIV_MASK (0xF << 23)
+/** Enable System Clock Divider */
+#define SYSCTL_RCC_USESYSDIV (1 << 22)
+/** Enable PWM Clock Divisor */
+#define SYSCTL_RCC_USEPWMDIV (1 << 20)
+/** PWM Unit Clock Divisor */
+#define SYSCTL_RCC_PWMDIV_MASK (0xF << 17)
+#define SYSCTL_RCC_PWMDIV_2 (0x0 << 17)
+#define SYSCTL_RCC_PWMDIV_4 (0x1 << 17)
+#define SYSCTL_RCC_PWMDIV_8 (0x2 << 17)
+#define SYSCTL_RCC_PWMDIV_16 (0x3 << 17)
+#define SYSCTL_RCC_PWMDIV_32 (0x4 << 17)
+#define SYSCTL_RCC_PWMDIV_64 (0x5 << 17)
+/** PLL Power Down */
+#define SYSCTL_RCC_PWRDN (1 << 13)
+/** PLL Bypass */
+#define SYSCTL_RCC_BYPASS (1 << 11)
+/** Crystal Value */
+#define SYSCTL_RCC_XTAL_MASK (0x1F << 6)
+#define SYSCTL_RCC_XTAL_4M (0x06 << 6)
+#define SYSCTL_RCC_XTAL_4M_096 (0x07 << 6)
+#define SYSCTL_RCC_XTAL_4M_9152 (0x08 << 6)
+#define SYSCTL_RCC_XTAL_5M (0x09 << 6)
+#define SYSCTL_RCC_XTAL_5M_12 (0x0A << 6)
+#define SYSCTL_RCC_XTAL_6M (0x0B << 6)
+#define SYSCTL_RCC_XTAL_6M_144 (0x0C << 6)
+#define SYSCTL_RCC_XTAL_7M_3728 (0x0D << 6)
+#define SYSCTL_RCC_XTAL_8M (0x0E << 6)
+#define SYSCTL_RCC_XTAL_8M_192 (0x0F << 6)
+#define SYSCTL_RCC_XTAL_10M (0x10 << 6)
+#define SYSCTL_RCC_XTAL_12M (0x11 << 6)
+#define SYSCTL_RCC_XTAL_12M_288 (0x12 << 6)
+#define SYSCTL_RCC_XTAL_13M_56 (0x13 << 6)
+#define SYSCTL_RCC_XTAL_14M_31818 (0x14 << 6)
+#define SYSCTL_RCC_XTAL_16M (0x15 << 6)
+#define SYSCTL_RCC_XTAL_16M_384 (0x16 << 6)
+#define SYSCTL_RCC_XTAL_18M (0x17 << 6)
+#define SYSCTL_RCC_XTAL_20M (0x18 << 6)
+#define SYSCTL_RCC_XTAL_24M (0x19 << 6)
+#define SYSCTL_RCC_XTAL_25M (0x1A << 6)
+/** Oscillator Source */
+#define SYSCTL_RCC_OSCSRC_MASK (0x3 << 4)
+#define SYSCTL_RCC_OSCSRC_MOSC (0x0 << 4)
+#define SYSCTL_RCC_OSCSRC_PIOSC (0x1 << 4)
+#define SYSCTL_RCC_OSCSRC_PIOSC_D4 (0x2 << 4)
+#define SYSCTL_RCC_OSCSRC_30K (0x3 << 4)
+/** Precision Internal Oscillator Disable */
+#define SYSCTL_RCC_IOSCDIS (1 << 1)
+/** Main Oscillator Disable */
+#define SYSCTL_RCC_MOSCDIS (1 << 0)
+
+/* =============================================================================
+ * SYSCTL_GPIOHBCTL values
+ * ---------------------------------------------------------------------------*/
+#define SYSCTL_GPIOHBCTL_PORTQ (1 << 14)
+#define SYSCTL_GPIOHBCTL_PORTP (1 << 13)
+#define SYSCTL_GPIOHBCTL_PORTN (1 << 12)
+#define SYSCTL_GPIOHBCTL_PORTM (1 << 11)
+#define SYSCTL_GPIOHBCTL_PORTL (1 << 10)
+#define SYSCTL_GPIOHBCTL_PORTK (1 << 9)
+#define SYSCTL_GPIOHBCTL_PORTJ (1 << 8)
+#define SYSCTL_GPIOHBCTL_PORTH (1 << 7)
+#define SYSCTL_GPIOHBCTL_PORTG (1 << 6)
+#define SYSCTL_GPIOHBCTL_PORTF (1 << 5)
+#define SYSCTL_GPIOHBCTL_PORTE (1 << 4)
+#define SYSCTL_GPIOHBCTL_PORTD (1 << 3)
+#define SYSCTL_GPIOHBCTL_PORTC (1 << 2)
+#define SYSCTL_GPIOHBCTL_PORTB (1 << 1)
+#define SYSCTL_GPIOHBCTL_PORTA (1 << 0)
+
+/* =============================================================================
+ * SYSCTL_RCC2 values
+ * ---------------------------------------------------------------------------*/
+/** RCC2 overides RCC */
+#define SYSCTL_RCC2_USERCC2 (1 << 31)
+/** Divide PLL as 400 MHz vs. 200 MHz */
+#define SYSCTL_RCC2_DIV400 (1 << 30)
+/** Auto Clock Gating */
+#define SYSCTL_RCC2_ACG (1 << 27)
+/** System Clock Divisor 2 */
+#define SYSCTL_RCC2_SYSDIV2_MASK (0x3F << 23)
+/** Additional LSB for SYSDIV2 */
+#define SYSCTL_RCC2_SYSDIV2LSB (1 << 22)
+/** System clock divisor mask when RCC2_DIV400 is set */
+#define SYSCTL_RCC2_SYSDIV400_MASK (0x7F << 22)
+/** Power-Down USB PLL */
+#define SYSCTL_RCC2_USBPWRDN (1 << 14)
+/** PLL Power Down 2 */
+#define SYSCTL_RCC2_PWRDN2 (1 << 13)
+/** PLL Bypass 2 */
+#define SYSCTL_RCC2_BYPASS2 (1 << 11)
+/** Oscillator Source 2 */
+#define SYSCTL_RCC2_OSCSRC2_MASK (0x7 << 4)
+#define SYSCTL_RCC2_OSCSRC2_MOSC (0x0 << 4)
+#define SYSCTL_RCC2_OSCSRC2_PIOSC (0x1 << 4)
+#define SYSCTL_RCC2_OSCSRC2_PIOSC_D4 (0x2 << 4)
+#define SYSCTL_RCC2_OSCSRC2_30K (0x3 << 4)
+#define SYSCTL_RCC2_OSCSRC2_32K768 (0x7 << 4)
+
+/* =============================================================================
+ * SYSCTL_MOSCCTL values
+ * ---------------------------------------------------------------------------*/
+/** No Crystal Connected */
+#define SYSCTL_MOSCCTL_NOXTAL (1 << 2)
+/** MOSC Failure Action */
+#define SYSCTL_MOSCCTL_MOSCIM (1 << 1)
+/** Clock Validation for MOSC */
+#define SYSCTL_MOSCCTL_CVAL (1 << 0)
+
+/* =============================================================================
+ * SYSCTL_DSLPCLKCFG values
+ * ---------------------------------------------------------------------------*/
+/*TODO*/
+
+/* =============================================================================
+ * SYSCTL_SYSPROP values
+ * ---------------------------------------------------------------------------*/
+/** FPU present */
+#define SYSCTL_SYSPROP_FPU (1 << 0)
+
+/* =============================================================================
+ * SYSCTL_PIOSCCAL values
+ * ---------------------------------------------------------------------------*/
+/** Use User Trim Value */
+#define SYSCTL_PIOSCCAL_UTEN (1 << 31)
+/** Start calibration */
+#define SYSCTL_PIOSCCAL_CAL (1 << 9)
+/** Update trim */
+#define SYSCTL_PIOSCCAL_UPDATE (1 << 8)
+/** User Trim Value */
+#define SYSCTL_PIOSCCAL_UT_MASK (0x7F << 0)
+
+/* =============================================================================
+ * SYSCTL_PIOSCSTAT values
+ * ---------------------------------------------------------------------------*/
+/** Default Trim Value */
+#define SYSCTL_PIOSCSTAT_DT_MASK (0x7F << 16)
+/** Calibration result */
+#define SYSCTL_PIOSCSTAT_RESULT_MASK (0x3 << 8)
+/** Calibration Trim Value */
+#define SYSCTL_PIOSCSTAT_CT_MASK (0x7F << 0)
+/* =============================================================================
+ * SYSCTL_PLLFREQ0 values
+ * ---------------------------------------------------------------------------*/
+/** PLL M fractional value */
+#define SYSCTL_PLLFREQ0_MFRAC_MASK (0x3FF << 10)
+/** PLL M integer value */
+#define SYSCTL_PLLFREQ0_MINT_MASK (0x3FF << 0)
+
+/* =============================================================================
+ * SYSCTL_PLLFREQ1 values
+ * ---------------------------------------------------------------------------*/
+/** PLL Q value */
+#define SYSCTL_PLLFREQ1_Q_MASK (0x1F << 8)
+/** PLL N value */
+#define SYSCTL_PLLFREQ1_N_MASK (0x1F << 0)
+
+/* =============================================================================
+ * SYSCTL_PLLSTAT values
+ * ---------------------------------------------------------------------------*/
+/** PLL lock */
+#define SYSCTL_PLLSTAT_LOCK (1 << 0)
+
+/* =============================================================================
+ * Convenience definitions for a readable API
+ * ---------------------------------------------------------------------------*/
+/**
+ * \brief Clock enable definitions
+ *
+ * The definitions are specified in the form
+ * 31:5 register offset from SYSCTL_BASE for the clock register
+ * 4:0 bit offset for the given peripheral
+ *
+ * The names have the form [clock_type]_[periph_type]_[periph_number]
+ * Where clock_type is
+ * RCC for run clock
+ * SCC for sleep clock
+ * DCC for deep-sleep clock
+ */
+enum lm4f_clken {
+ /*
+ * Run clock control
+ */
+ RCC_WD0 = ((uint32_t)&SYSCTL_RCGCWD - SYSCTL_BASE) << 5,
+ RCC_WD1,
+
+ RCC_TIMER0 = ((uint32_t)&SYSCTL_RCGCTIMER - SYSCTL_BASE) << 5,
+ RCC_TIMER1,
+ RCC_TIMER2,
+ RCC_TIMER3,
+ RCC_TIMER4,
+ RCC_TIMER5,
+
+ RCC_GPIOA = ((uint32_t)&SYSCTL_RCGCGPIO - SYSCTL_BASE) << 5,
+ RCC_GPIOB,
+ RCC_GPIOC,
+ RCC_GPIOD,
+ RCC_GPIOE,
+ RCC_GPIOF,
+ RCC_GPIOG,
+ RCC_GPIOH,
+ RCC_GPIOJ,
+ RCC_GPIOK,
+ RCC_GPIOL,
+ RCC_GPIOM,
+ RCC_GPION,
+ RCC_GPIOP,
+ RCC_GPIOQ,
+
+ RCC_DMA = ((uint32_t)&SYSCTL_RCGCDMA - SYSCTL_BASE) << 5,
+
+ RCC_HIB = ((uint32_t)&SYSCTL_RCGCGPIO - SYSCTL_BASE) << 5,
+
+ RCC_UART0 = ((uint32_t)&SYSCTL_RCGCUART - SYSCTL_BASE) << 5,
+ RCC_UART1,
+ RCC_UART2,
+ RCC_UART3,
+ RCC_UART4,
+ RCC_UART5,
+ RCC_UART6,
+ RCC_UART7,
+
+ RCC_SSI0 = ((uint32_t)&SYSCTL_RCGCSSI - SYSCTL_BASE) << 5,
+ RCC_SSI1,
+ RCC_SSI2,
+ RCC_SSI3,
+
+ RCC_I2C0 = ((uint32_t)&SYSCTL_RCGCI2C - SYSCTL_BASE) << 5,
+ RCC_I2C1,
+ RCC_I2C2,
+ RCC_I2C3,
+ RCC_I2C4,
+ RCC_I2C5,
+
+ RCC_USB0 = ((uint32_t)&SYSCTL_RCGCUSB - SYSCTL_BASE) << 5,
+
+ RCC_CAN0 = ((uint32_t)&SYSCTL_RCGCCAN - SYSCTL_BASE) << 5,
+ RCC_CAN1,
+
+ RCC_ADC0 = ((uint32_t)&SYSCTL_RCGCADC - SYSCTL_BASE) << 5,
+ RCC_ADC1,
+
+ RCC_ACMP0 = ((uint32_t)&SYSCTL_RCGCACMP - SYSCTL_BASE) << 5,
+
+ RCC_PWM0 = ((uint32_t)&SYSCTL_RCGCPWM - SYSCTL_BASE) << 5,
+ RCC_PWM1,
+
+ RCC_QEI0 = ((uint32_t)&SYSCTL_RCGCQEI - SYSCTL_BASE) << 5,
+ RCC_QEI1,
+
+ RCC_EEPROM0 = ((uint32_t)&SYSCTL_RCGCEEPROM - SYSCTL_BASE) << 5,
+
+ RCC_WTIMER0 = ((uint32_t)&SYSCTL_RCGCWTIMER - SYSCTL_BASE) << 5,
+ RCC_WTIMER1,
+ RCC_WTIMER2,
+ RCC_WTIMER3,
+ RCC_WTIMER4,
+ RCC_WTIMER5,
+
+
+ /*
+ * Sleep clock control
+ */
+ SCC_WD0 = ((uint32_t)&SYSCTL_SCGCWD - SYSCTL_BASE) << 5,
+ SCC_WD1,
+
+ SCC_TIMER0 = ((uint32_t)&SYSCTL_SCGCTIMER - SYSCTL_BASE) << 5,
+ SCC_TIMER1,
+ SCC_TIMER2,
+ SCC_TIMER3,
+ SCC_TIMER4,
+ SCC_TIMER5,
+
+ SCC_GPIOA = ((uint32_t)&SYSCTL_SCGCGPIO - SYSCTL_BASE) << 5,
+ SCC_GPIOB,
+ SCC_GPIOC,
+ SCC_GPIOD,
+ SCC_GPIOE,
+ SCC_GPIOF,
+ SCC_GPIOG,
+ SCC_GPIOH,
+ SCC_GPIOJ,
+ SCC_GPIOK,
+ SCC_GPIOL,
+ SCC_GPIOM,
+ SCC_GPION,
+ SCC_GPIOP,
+ SCC_GPIOQ,
+
+ SCC_DMA = ((uint32_t)&SYSCTL_SCGCDMA - SYSCTL_BASE) << 5,
+
+ SCC_HIB = ((uint32_t)&SYSCTL_SCGCGPIO - SYSCTL_BASE) << 5,
+
+ SCC_UART0 = ((uint32_t)&SYSCTL_SCGCUART - SYSCTL_BASE) << 5,
+ SCC_UART1,
+ SCC_UART2,
+ SCC_UART3,
+ SCC_UART4,
+ SCC_UART5,
+ SCC_UART6,
+ SCC_UART7,
+
+ SCC_SSI0 = ((uint32_t)&SYSCTL_SCGCSSI - SYSCTL_BASE) << 5,
+ SCC_SSI1,
+ SCC_SSI2,
+ SCC_SSI3,
+
+ SCC_I2C0 = ((uint32_t)&SYSCTL_SCGCI2C - SYSCTL_BASE) << 5,
+ SCC_I2C1,
+ SCC_I2C2,
+ SCC_I2C3,
+ SCC_I2C4,
+ SCC_I2C5,
+
+ SCC_USB0 = ((uint32_t)&SYSCTL_SCGCUSB - SYSCTL_BASE) << 5,
+
+ SCC_CAN0 = ((uint32_t)&SYSCTL_SCGCCAN - SYSCTL_BASE) << 5,
+ SCC_CAN1,
+
+ SCC_ADC0 = ((uint32_t)&SYSCTL_SCGCADC - SYSCTL_BASE) << 5,
+ SCC_ADC1,
+
+ SCC_ACMP0 = ((uint32_t)&SYSCTL_SCGCACMP - SYSCTL_BASE) << 5,
+
+ SCC_PWM0 = ((uint32_t)&SYSCTL_SCGCPWM - SYSCTL_BASE) << 5,
+ SCC_PWM1,
+
+ SCC_QEI0 = ((uint32_t)&SYSCTL_SCGCQEI - SYSCTL_BASE) << 5,
+ SCC_QEI1,
+
+ SCC_EEPROM0 = ((uint32_t)&SYSCTL_SCGCEEPROM - SYSCTL_BASE) << 5,
+
+ SCC_WTIMER0 = ((uint32_t)&SYSCTL_SCGCWTIMER - SYSCTL_BASE) << 5,
+ SCC_WTIMER1,
+ SCC_WTIMER2,
+ SCC_WTIMER3,
+ SCC_WTIMER4,
+ SCC_WTIMER5,
+
+ /*
+ * Deep-sleep clock control
+ */
+ DCC_WD0 = ((uint32_t)&SYSCTL_DCGCWD - SYSCTL_BASE) << 5,
+ DCC_WD1,
+
+ DCC_TIMER0 = ((uint32_t)&SYSCTL_DCGCTIMER - SYSCTL_BASE) << 5,
+ DCC_TIMER1,
+ DCC_TIMER2,
+ DCC_TIMER3,
+ DCC_TIMER4,
+ DCC_TIMER5,
+
+ DCC_GPIOA = ((uint32_t)&SYSCTL_DCGCGPIO - SYSCTL_BASE) << 5,
+ DCC_GPIOB,
+ DCC_GPIOC,
+ DCC_GPIOD,
+ DCC_GPIOE,
+ DCC_GPIOF,
+ DCC_GPIOG,
+ DCC_GPIOH,
+ DCC_GPIOJ,
+ DCC_GPIOK,
+ DCC_GPIOL,
+ DCC_GPIOM,
+ DCC_GPION,
+ DCC_GPIOP,
+ DCC_GPIOQ,
+
+ DCC_DMA = ((uint32_t)&SYSCTL_DCGCDMA - SYSCTL_BASE) << 5,
+
+ DCC_HIB = ((uint32_t)&SYSCTL_DCGCGPIO - SYSCTL_BASE) << 5,
+
+ DCC_UART0 = ((uint32_t)&SYSCTL_DCGCUART - SYSCTL_BASE) << 5,
+ DCC_UART1,
+ DCC_UART2,
+ DCC_UART3,
+ DCC_UART4,
+ DCC_UART5,
+ DCC_UART6,
+ DCC_UART7,
+
+ DCC_SSI0 = ((uint32_t)&SYSCTL_DCGCSSI - SYSCTL_BASE) << 5,
+ DCC_SSI1,
+ DCC_SSI2,
+ DCC_SSI3,
+
+ DCC_I2C0 = ((uint32_t)&SYSCTL_DCGCI2C - SYSCTL_BASE) << 5,
+ DCC_I2C1,
+ DCC_I2C2,
+ DCC_I2C3,
+ DCC_I2C4,
+ DCC_I2C5,
+
+ DCC_USB0 = ((uint32_t)&SYSCTL_DCGCUSB - SYSCTL_BASE) << 5,
+
+ DCC_CAN0 = ((uint32_t)&SYSCTL_DCGCCAN - SYSCTL_BASE) << 5,
+ DCC_CAN1,
+
+ DCC_ADC0 = ((uint32_t)&SYSCTL_DCGCADC - SYSCTL_BASE) << 5,
+ DCC_ADC1,
+
+ DCC_ACMP0 = ((uint32_t)&SYSCTL_DCGCACMP - SYSCTL_BASE) << 5,
+
+ DCC_PWM0 = ((uint32_t)&SYSCTL_DCGCPWM - SYSCTL_BASE) << 5,
+ DCC_PWM1,
+
+ DCC_QEI0 = ((uint32_t)&SYSCTL_DCGCQEI - SYSCTL_BASE) << 5,
+ DCC_QEI1,
+
+ DCC_EEPROM0 = ((uint32_t)&SYSCTL_DCGCEEPROM - SYSCTL_BASE) << 5,
+
+ DCC_WTIMER0 = ((uint32_t)&SYSCTL_DCGCWTIMER - SYSCTL_BASE) << 5,
+ DCC_WTIMER1,
+ DCC_WTIMER2,
+ DCC_WTIMER3,
+ DCC_WTIMER4,
+ DCC_WTIMER5,
+
+};
+
+/* ============================================================================
+ * Function prototypes
+ * --------------------------------------------------------------------------*/
+BEGIN_DECLS
+
+void periph_clock_enable(enum lm4f_clken periph);
+void periph_clock_disable(enum lm4f_clken periph);
+
+END_DECLS
+
+/**@}*/
+
+#endif /* LM4F_SYSTEMCONTROL_H */
+
diff --git a/libopencm3/include/libopencm3/lm4f/uart.h b/libopencm3/include/libopencm3/lm4f/uart.h
new file mode 100644
index 0000000..5bd7e37
--- /dev/null
+++ b/libopencm3/include/libopencm3/lm4f/uart.h
@@ -0,0 +1,550 @@
+/** @defgroup uart_defines UART Control
+ *
+ * @brief Defined Constants and Types for the LM4F UART Control
+ *
+ * @ingroup LM4Fxx_defines
+ *
+ * @version 1.0.0
+ *
+ * @author @htmlonly © @endhtmlonly 2013
+ * Alexandru Gagniuc
+ *
+ * @date 07 May 2013
+ *
+ * LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Alexandru Gagniuc
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LIBOPENCM3_LM4F_UART_H
+#define LIBOPENCM3_LM4F_UART_H
+
+/**@{*/
+
+#include
+#include
+
+/* =============================================================================
+ * Convenience macros
+ * ---------------------------------------------------------------------------*/
+/** @defgroup uart_reg_base UART register base addresses
+ * @{*/
+#define UART0 UART0_BASE
+#define UART1 UART1_BASE
+#define UART2 UART2_BASE
+#define UART3 UART3_BASE
+#define UART4 UART4_BASE
+#define UART5 UART5_BASE
+#define UART6 UART6_BASE
+#define UART7 UART7_BASE
+/** @} */
+
+/* =============================================================================
+ * UART registers
+ * ---------------------------------------------------------------------------*/
+
+/* UART data register */
+#define UART_DR(uart_base) MMIO32(uart_base + 0x00)
+
+/* UART Receive Status/Error Clear register */
+#define UART_RSR(uart_base) MMIO32(uart_base + 0x04)
+#define UART_ECR(uart_base) MMIO32(uart_base + 0x04)
+
+/* UART Flag register */
+#define UART_FR(uart_base) MMIO32(uart_base + 0x18)
+
+/* UART IrDA Low-Power register */
+#define UART_ILPR(uart_base) MMIO32(uart_base + 0x20)
+
+/* UART Integer baudrate divisor */
+#define UART_IBRD(uart_base) MMIO32(uart_base + 0x24)
+
+/* UART Fractional baudrate divisor */
+#define UART_FBRD(uart_base) MMIO32(uart_base + 0x28)
+
+/* UART Line control */
+#define UART_LCRH(uart_base) MMIO32(uart_base + 0x2C)
+
+/* UART Control */
+#define UART_CTL(uart_base) MMIO32(uart_base + 0x30)
+
+/* UART Interrupt FIFO level select */
+#define UART_IFLS(uart_base) MMIO32(uart_base + 0x34)
+
+/* UART Interrupt mask */
+#define UART_IM(uart_base) MMIO32(uart_base + 0x38)
+
+/* UART Raw interrupt status */
+#define UART_RIS(uart_base) MMIO32(uart_base + 0x3C)
+
+/* UART Masked Interrupt status */
+#define UART_MIS(uart_base) MMIO32(uart_base + 0x40)
+
+/* UART Interrupt Clear */
+#define UART_ICR(uart_base) MMIO32(uart_base + 0x44)
+
+/* UART DMA control */
+#define UART_DMACTL(uart_base) MMIO32(uart_base + 0x48)
+
+/* UART LIN control */
+#define UART_LCTL(uart_base) MMIO32(uart_base + 0x90)
+
+/* UART LIN snap shot */
+#define UART_LSS(uart_base) MMIO32(uart_base + 0x94)
+
+/* UART LIN timer */
+#define UART_LTIM(uart_base) MMIO32(uart_base + 0x98)
+
+/* UART 9-Bit self address */
+#define UART_9BITADDR(uart_base) MMIO32(uart_base + 0xA4)
+
+/* UART 9-Bit self address mask */
+#define UART_9BITAMASK(uart_base) MMIO32(uart_base + 0xA8)
+
+/* UART Peripheral properties */
+#define UART_PP(uart_base) MMIO32(uart_base + 0xFC0)
+
+/* UART Clock configuration */
+#define UART_CC(uart_base) MMIO32(uart_base + 0xFC8)
+
+/* UART Peripheral Identification 4 */
+#define UART_PERIPH_ID4(uart_base) MMIO32(uart_base + 0xFD0)
+
+/* UART Peripheral Identification 5 */
+#define UART_PERIPH_ID5(uart_base) MMIO32(uart_base + 0xFD4)
+
+/* UART Peripheral Identification 6 */
+#define UART_PERIPH_ID6(uart_base) MMIO32(uart_base + 0xFD8)
+
+/* UART Peripheral Identification 7 */
+#define UART_PERIPH_ID7(uart_base) MMIO32(uart_base + 0xFDC)
+
+/* UART Peripheral Identification 0 */
+#define UART_PERIPH_ID0(uart_base) MMIO32(uart_base + 0xFE0)
+
+/* UART Peripheral Identification 1 */
+#define UART_PERIPH_ID1(uart_base) MMIO32(uart_base + 0xFE4)
+
+/* UART Peripheral Identification 2 */
+#define UART_PERIPH_ID2(uart_base) MMIO32(uart_base + 0xFE8)
+
+/* UART Peripheral Identification 3 */
+#define UART_PERIPH_ID3(uart_base) MMIO32(uart_base + 0xFEC)
+
+/* UART PrimeCell Identification 0 */
+#define UART_PCELL_ID0(uart_base) MMIO32(uart_base + 0xFF0)
+
+/* UART PrimeCell Identification 1 */
+#define UART_PCELL_ID1(uart_base) MMIO32(uart_base + 0xFF4)
+
+/* UART PrimeCell Identification 2 */
+#define UART_PCELL_ID2(uart_base) MMIO32(uart_base + 0xFF8)
+
+/* UART PrimeCell Identification 3 */
+#define UART_PCELL_ID3(uart_base) MMIO32(uart_base + 0xFFC)
+
+
+/* =============================================================================
+ * UART_DR values
+ * ---------------------------------------------------------------------------*/
+/** Overrun Error */
+#define UART_DR_OE (1 << 11)
+/** Break Error */
+#define UART_DR_BE (1 << 10)
+/** Parity Error */
+#define UART_DR_PE (1 << 9)
+/** Framing Error */
+#define UART_DR_FE (1 << 8)
+/** Data transmitted or received */
+#define UART_DR_DATA_MASK (0xFF << 0)
+
+/* =============================================================================
+ * Readonly UART_RSR values
+ * ---------------------------------------------------------------------------*/
+/** Overrun Error */
+#define UART_RSR_OE (1 << 3)
+/** Break Error */
+#define UART_RSR_BE (1 << 2)
+/** Parity Error */
+#define UART_RSR_PE (1 << 1)
+/** Framing Error */
+#define UART_RSR_FE (1 << 0)
+
+/* =============================================================================
+ * UART_FR values
+ * ---------------------------------------------------------------------------*/
+/** Tx FIFO empty */
+#define UART_FR_TXFE (1 << 7)
+/** Rx FIFO full */
+#define UART_FR_RXFF (1 << 6)
+/** Tx FIFO full */
+#define UART_FR_TXFF (1 << 5)
+/** Rx FIFO empty */
+#define UART_FR_RXFE (1 << 4)
+/** UART Busy */
+#define UART_FR_BUSY (1 << 3)
+/** Clear To Send */
+#define UART_FR_CTS (1 << 0)
+
+/* =============================================================================
+ * UART_LCRH values
+ * ---------------------------------------------------------------------------*/
+/** Stick parity select */
+#define UART_LCRH_SPS (1 << 7)
+/** Word length */
+#define UART_LCRH_WLEN_MASK (3 << 5)
+#define UART_LCRH_WLEN_5 (0 << 5)
+#define UART_LCRH_WLEN_6 (1 << 5)
+#define UART_LCRH_WLEN_7 (2 << 5)
+#define UART_LCRH_WLEN_8 (3 << 5)
+/** Enable FIFOs */
+#define UART_LCRH_FEN (1 << 4)
+/** Two stop bits select */
+#define UART_LCRH_STP2 (1 << 3)
+/** Even parity select */
+#define UART_LCRH_EPS (1 << 2)
+/** Parity enable */
+#define UART_LCRH_PEN (1 << 1)
+/** Send break */
+#define UART_LCRH_BRK (1 << 0)
+
+/* =============================================================================
+ * UART_CTL values
+ * ---------------------------------------------------------------------------*/
+/** Enable Clear To Send */
+#define UART_CTL_CTSEN (1 << 15)
+/** Enable Request To Send */
+#define UART_CTL_RTSEN (1 << 14)
+/** Request To Send */
+#define UART_CTL_RTS (1 << 11)
+/** Data terminal ready */
+#define UART_CTL_DTR (1 << 10)
+/** Rx Enable */
+#define UART_CTL_RXE (1 << 9)
+/** Tx Enable */
+#define UART_CTL_TXE (1 << 8)
+/** Loop back enable */
+#define UART_CTL_LBE (1 << 7)
+/** LIN mode enable */
+#define UART_CTL_LIN (1 << 6)
+/** High speed Enable */
+#define UART_CTL_HSE (1 << 5)
+/** End of transmission */
+#define UART_CTL_EOT (1 << 4)
+/** ISO 7816 Smart Card support */
+#define UART_CTL_SMART (1 << 3)
+/** SIR low-power mode */
+#define UART_CTL_SIRLIP (1 << 2)
+/** SIR enable */
+#define UART_CTL_SIREN (1 << 1)
+/** UART enable */
+#define UART_CTL_UARTEN (1 << 0)
+
+/* =============================================================================
+ * UART_IFLS values
+ * ---------------------------------------------------------------------------*/
+/** UART Rx interrupt FIFO level select */
+#define UART_IFLS_RXIFLSEL_MASK (7 << 3)
+#define UART_IFLS_RXIFLSEL_1_8 (0 << 3)
+#define UART_IFLS_RXIFLSEL_1_4 (1 << 3)
+#define UART_IFLS_RXIFLSEL_1_2 (2 << 3)
+#define UART_IFLS_RXIFLSEL_3_4 (3 << 3)
+#define UART_IFLS_RXIFLSEL_7_8 (4 << 3)
+/** UART Tx interrupt FIFO level select */
+#define UART_IFLS_TXIFLSEL_MASK (7 << 0)
+#define UART_IFLS_TXIFLSEL_7_8 (0 << 0)
+#define UART_IFLS_TXIFLSEL_3_4 (1 << 0)
+#define UART_IFLS_TXIFLSEL_1_2 (2 << 0)
+#define UART_IFLS_TXIFLSEL_1_4 (3 << 0)
+#define UART_IFLS_TXIFLSEL_1_8 (4 << 0)
+
+/* =============================================================================
+ * UART interrupt mask values
+ *
+ * These are interchangeable across UART_IM, UART_RIS, UART_MIS, and UART_ICR
+ * registers.
+ * ---------------------------------------------------------------------------*/
+/** LIN mode edge 5 interrupt mask */
+#define UART_IM_LME5IM (1 << 15)
+/** LIN mode edge 1 interrupt mask */
+#define UART_IM_LME1IM (1 << 14)
+/** LIN mode sync break interrupt mask */
+#define UART_IM_LMSBIM (1 << 13)
+/** 9-bit mode interrupt mask */
+#define UART_IM_9BITIM (1 << 12)
+/** Overrun error interrupt mask */
+#define UART_IM_OEIM (1 << 10)
+/** Break error interrupt mask */
+#define UART_IM_BEIM (1 << 9)
+/** Parity error interrupt mask */
+#define UART_IM_PEIM (1 << 8)
+/** Framing error interrupt mask */
+#define UART_IM_FEIM (1 << 7)
+/** Receive time-out interrupt mask */
+#define UART_IM_RTIM (1 << 6)
+/** Transmit interrupt mask */
+#define UART_IM_TXIM (1 << 5)
+/** Receive interrupt mask */
+#define UART_IM_RXIM (1 << 4)
+/** Data Set Ready modem interrupt mask */
+#define UART_IM_DSRIM (1 << 3)
+/** Data Carrier Detect modem interrupt mask */
+#define UART_IM_DCDIM (1 << 2)
+/** Clear To Send modem interrupt mask */
+#define UART_IM_CTSIM (1 << 1)
+/** Ring Indicator modem interrupt mask */
+#define UART_IM_RIIM (1 << 0)
+
+/* =============================================================================
+ * UART_DMACTL values
+ * ---------------------------------------------------------------------------*/
+/** DMA on error */
+#define UART_DMACTL_DMAERR (1 << 2)
+/** Transmit DMA enable */
+#define UART_DMACTL_TXDMAE (1 << 1)
+/** Recieve DMA enable */
+#define UART_DMACTL_RXDMAE (1 << 0)
+
+/* =============================================================================
+ * UART_LCTL values
+ * ---------------------------------------------------------------------------*/
+/** Sync break length */
+#define UART_LCTL_BLEN_MASK (3 << 4)
+#define UART_LCTL_BLEN_16T (3 << 4)
+#define UART_LCTL_BLEN_15T (2 << 4)
+#define UART_LCTL_BLEN_14T (1 << 4)
+#define UART_LCTL_BLEN_13T (0 << 4)
+/** LIN master enable */
+#define UART_LCTL_MASTER (1 << 0)
+
+/* =============================================================================
+ * UART_9BITADDR values
+ * ---------------------------------------------------------------------------*/
+/** Enable 9-bit mode */
+#define UART_UART_9BITADDR_9BITEN (1 << 15)
+/** Self-address for 9-bit mode */
+#define UART_UART_9BITADDR_ADDR_MASK (0xFF << 0)
+
+/* =============================================================================
+ * UART_PP values
+ * ---------------------------------------------------------------------------*/
+/** 9-bit support */
+#define UART_UART_PP_NB (1 << 1)
+/** Smart Card support */
+#define UART_UART_PP_SC (1 << 0)
+
+/* =============================================================================
+ * UART_CC values
+ * ---------------------------------------------------------------------------*/
+/** UART baud clock source */
+#define UART_CC_CS_MASK (0xF << 0)
+#define UART_CC_CS_SYSCLK (0x0 << 0)
+#define UART_CC_CS_PIOSC (0x5 << 0)
+
+/* =============================================================================
+ * Convenience enums
+ * ---------------------------------------------------------------------------*/
+enum uart_parity {
+ UART_PARITY_NONE,
+ UART_PARITY_ODD,
+ UART_PARITY_EVEN,
+ UART_PARITY_STICK_0,
+ UART_PARITY_STICK_1,
+};
+
+enum uart_flowctl {
+ UART_FLOWCTL_NONE,
+ UART_FLOWCTL_RTS,
+ UART_FLOWCTL_CTS,
+ UART_FLOWCTL_RTS_CTS,
+};
+
+/**
+ * \brief UART interrupt masks
+ *
+ * These masks can be OR'ed together to specify more than one interrupt. For
+ * example, (UART_INT_TXIM | UART_INT_TXIM) specifies both Rx and Tx Interrupt.
+ */
+enum uart_interrupt_flag {
+
+ UART_INT_LME5 = UART_IM_LME5IM,
+ UART_INT_LME1 = UART_IM_LME1IM,
+ UART_INT_LMSB = UART_IM_LMSBIM,
+ UART_INT_9BIT = UART_IM_9BITIM,
+ UART_INT_OE = UART_IM_OEIM,
+ UART_INT_BE = UART_IM_BEIM,
+ UART_INT_PE = UART_IM_PEIM,
+ UART_INT_FE = UART_IM_FEIM,
+ UART_INT_RT = UART_IM_RTIM,
+ UART_INT_TX = UART_IM_TXIM,
+ UART_INT_RX = UART_IM_RXIM,
+ UART_INT_DSR = UART_IM_DSRIM,
+ UART_INT_DCD = UART_IM_DCDIM,
+ UART_INT_CTS = UART_IM_CTSIM,
+ UART_INT_RI = UART_IM_RIIM,
+};
+
+/**
+ * \brief UART RX FIFO interrupt trigger levels
+ *
+ * The levels indicate how full the FIFO should be before an interrupt is
+ * generated. UART_FIFO_RX_TRIG_3_4 means that an interrupt is triggered when
+ * the FIFO is 3/4 full. As the FIFO is 8 elements deep, 1/8 is equal to being
+ * triggered by a single character.
+ */
+enum uart_fifo_rx_trigger_level {
+ UART_FIFO_RX_TRIG_1_8 = UART_IFLS_RXIFLSEL_1_8,
+ UART_FIFO_RX_TRIG_1_4 = UART_IFLS_RXIFLSEL_1_4,
+ UART_FIFO_RX_TRIG_1_2 = UART_IFLS_RXIFLSEL_1_2,
+ UART_FIFO_RX_TRIG_3_4 = UART_IFLS_RXIFLSEL_3_4,
+ UART_FIFO_RX_TRIG_7_8 = UART_IFLS_RXIFLSEL_7_8
+};
+
+/**
+ * \brief UART TX FIFO interrupt trigger levels
+ *
+ * The levels indicate how empty the FIFO should be before an interrupt is
+ * generated. Note that this indicates the emptiness of the FIFO and not the
+ * fullness. This is somewhat confusing, but it follows the wording of the
+ * LM4F120H5QR datasheet.
+ *
+ * UART_FIFO_TX_TRIG_3_4 means that an interrupt is triggered when the FIFO is
+ * 3/4 empty. As the FIFO is 8 elements deep, 7/8 is equal to being triggered
+ * by a single character.
+ */
+enum uart_fifo_tx_trigger_level {
+ UART_FIFO_TX_TRIG_7_8 = UART_IFLS_TXIFLSEL_7_8,
+ UART_FIFO_TX_TRIG_3_4 = UART_IFLS_TXIFLSEL_3_4,
+ UART_FIFO_TX_TRIG_1_2 = UART_IFLS_TXIFLSEL_1_2,
+ UART_FIFO_TX_TRIG_1_4 = UART_IFLS_TXIFLSEL_1_4,
+ UART_FIFO_TX_TRIG_1_8 = UART_IFLS_TXIFLSEL_1_8
+};
+
+/* =============================================================================
+ * Function prototypes
+ * ---------------------------------------------------------------------------*/
+BEGIN_DECLS
+
+void uart_set_baudrate(uint32_t uart, uint32_t baud);
+void uart_set_databits(uint32_t uart, uint8_t databits);
+void uart_set_stopbits(uint32_t uart, uint8_t stopbits);
+void uart_set_parity(uint32_t uart, enum uart_parity parity);
+void uart_set_mode(uint32_t uart, uint32_t mode);
+void uart_set_flow_control(uint32_t uart, enum uart_flowctl flow);
+void uart_enable(uint32_t uart);
+void uart_disable(uint32_t uart);
+void uart_clock_from_piosc(uint32_t uart);
+void uart_clock_from_sysclk(uint32_t uart);
+
+void uart_send(uint32_t uart, uint16_t data);
+uint16_t uart_recv(uint32_t uart);
+void uart_wait_send_ready(uint32_t uart);
+void uart_wait_recv_ready(uint32_t uart);
+void uart_send_blocking(uint32_t uart, uint16_t data);
+uint16_t uart_recv_blocking(uint32_t uart);
+
+void uart_enable_rx_dma(uint32_t uart);
+void uart_disable_rx_dma(uint32_t uart);
+void uart_enable_tx_dma(uint32_t uart);
+void uart_disable_tx_dma(uint32_t uart);
+
+void uart_enable_fifo(uint32_t uart);
+void uart_disable_fifo(uint32_t uart);
+void uart_set_fifo_trigger_levels(uint32_t uart,
+ enum uart_fifo_rx_trigger_level rx_level,
+ enum uart_fifo_tx_trigger_level tx_level);
+
+/* We inline FIFO full/empty checks as they are intended to be called from ISRs
+ * */
+/** @ingroup uart_fifo
+ * @{
+ * \brief Determine if the TX fifo is full
+ *
+ * @param[in] uart UART block register address base @ref uart_reg_base
+ */
+static inline
+bool uart_is_tx_fifo_full(uint32_t uart)
+{
+ return UART_FR(uart) & UART_FR_TXFF;
+}
+
+
+/**
+ * \brief Determine if the TX fifo is empty
+ *
+ * @param[in] uart UART block register address base @ref uart_reg_base
+ */
+static inline
+bool uart_is_tx_fifo_empty(uint32_t uart)
+{
+ return UART_FR(uart) & UART_FR_TXFE;
+}
+
+/**
+ * \brief Determine if the RX fifo is full
+ *
+ * @param[in] uart UART block register address base @ref uart_reg_base
+ */
+static inline
+bool uart_is_rx_fifo_full(uint32_t uart)
+{
+ return UART_FR(uart) & UART_FR_RXFF;
+}
+
+/**
+ * \brief Determine if the RX fifo is empty
+ *
+ * @param[in] uart UART block register address base @ref uart_reg_base
+ */
+static inline
+bool uart_is_rx_fifo_empty(uint32_t uart)
+{
+ return UART_FR(uart) & UART_FR_RXFE;
+}
+/**@}*/
+
+void uart_enable_interrupts(uint32_t uart, enum uart_interrupt_flag ints);
+void uart_disable_interrupts(uint32_t uart, enum uart_interrupt_flag ints);
+void uart_enable_rx_interrupt(uint32_t uart);
+void uart_disable_rx_interrupt(uint32_t uart);
+void uart_enable_tx_interrupt(uint32_t uart);
+void uart_disable_tx_interrupt(uint32_t uart);
+void uart_clear_interrupt_flag(uint32_t uart, enum uart_interrupt_flag ints);
+
+/* Let's keep this one inlined. It's designed to be used in ISRs */
+/** @ingroup uart_irq
+ * @{
+ * \brief Determine if interrupt is generated by the given source
+ *
+ * @param[in] uart UART block register address base @ref uart_reg_base
+ * @param[in] source source to check.
+ */
+static inline
+bool uart_is_interrupt_source(uint32_t uart, enum uart_interrupt_flag source)
+{
+ return UART_MIS(uart) & source;
+}
+/**@}*/
+
+END_DECLS
+
+/**@}*/
+
+#endif /* LIBOPENCM3_LM4F_UART_H */
diff --git a/libopencm3/include/libopencm3/lm4f/usb.h b/libopencm3/include/libopencm3/lm4f/usb.h
new file mode 100644
index 0000000..f22d799
--- /dev/null
+++ b/libopencm3/include/libopencm3/lm4f/usb.h
@@ -0,0 +1,422 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Alexandru Gagniuc
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+/** @defgroup usb_defines USB Controller
+ *
+ * @brief Defined Constants and Types for the LM4F USB Controller
+ *
+ * @ingroup LM4Fxx_defines
+ *
+ * @version 1.0.0
+ *
+ * @author @htmlonly © @endhtmlonly 2013 Alexandru Gagniuc
+ *
+ * @date 15 May 2013
+ *
+ * LGPL License Terms @ref lgpl_license
+ */
+
+
+#ifndef LIBOPENCM3_LM4F_USB_H
+#define LIBOPENCM3_LM4F_USB_H
+
+/**@{*/
+
+#include
+#include
+
+/* ============================================================================
+ * USB registers
+ * --------------------------------------------------------------------------*/
+
+/* USB Device Functional Address */
+#define USB_FADDR MMIO8(USB_BASE + 0x00)
+
+/* USB Power */
+#define USB_POWER MMIO8(USB_BASE + 0x01)
+
+/* USB Transmit Interrupt Status */
+#define USB_TXIS MMIO16(USB_BASE + 0x02)
+
+/* USB Receive Interrupt Status */
+#define USB_RXIS MMIO16(USB_BASE + 0x04)
+
+/* USB Transmit Interrupt Enable */
+#define USB_TXIE MMIO16(USB_BASE + 0x06)
+
+/* USB Receive Interrupt Enable */
+#define USB_RXIE MMIO16(USB_BASE + 0x08)
+
+/* USB General Interrupt Status */
+#define USB_IS MMIO8(USB_BASE + 0x0A)
+
+/* USB Interrupt Enable */
+#define USB_IE MMIO8(USB_BASE + 0x0B)
+
+/* USB Frame Value */
+#define USB_FRAME MMIO16(USB_BASE + 0x0C)
+
+/* USB Endpoint Index */
+#define USB_EPIDX MMIO8(USB_BASE + 0x0E)
+
+/* USB Test Mode */
+#define USB_TEST MMIO8(USB_BASE + 0x0F)
+
+/* USB FIFO Endpoint [0-7] */
+#define USB_FIFO8(n) MMIO8(USB_BASE + 0x20 + n*0x04)
+#define USB_FIFO16(n) MMIO16(USB_BASE + 0x20 + n*0x04)
+#define USB_FIFO32(n) MMIO32(USB_BASE + 0x20 + n*0x04)
+
+/* USB Transmit Dynamic FIFO Sizing */
+#define USB_TXFIFOSZ MMIO8(USB_BASE + 0x62)
+
+/* USB Receive Dynamic FIFO Sizing */
+#define USB_RXFIFOSZ MMIO8(USB_BASE + 0x63)
+
+/* USB Transmit FIFO Start Address */
+#define USB_TXFIFOADD MMIO16(USB_BASE + 0x64)
+
+/* USB Receive FIFO Start Address */
+#define USB_RXFIFOADD MMIO16(USB_BASE + 0x66)
+
+/* USB Connect Timing */
+#define USB_CONTIM MMIO8(USB_BASE + 0x7A)
+
+/* USB Full-Speed Last Transaction to End of Frame Timing */
+#define USB_FSEOF MMIO8(USB_BASE + 0x7D)
+
+/* USB Low-Speed Last Transaction to End of Frame Timing */
+#define USB_LSEOF MMIO8(USB_BASE + 0x7E)
+
+/* USB Control and Status Endpoint 0 Low */
+#define USB_CSRL0 MMIO8(USB_BASE + 0x102)
+
+/* USB Control and Status Endpoint 0 High */
+#define USB_CSRH0 MMIO8(USB_BASE + 0x103)
+
+/* USB Receive Byte Count Endpoint 0 */
+#define USB_COUNT0 MMIO8(USB_BASE + 0x108)
+
+/* USB Maximum Transmit Data Endpoint [1-7] */
+#define USB_TXMAXP(n) MMIO16(USB_BASE + 0x100 + n*0x10)
+
+/* USB Transmit Control and Status Endpoint [1-7] Low */
+#define USB_TXCSRL(n) MMIO8(USB_BASE + 0x102 + n*0x10)
+
+/* USB Transmit Control and Status Endpoint [1-7] High */
+#define USB_TXCSRH(n) MMIO8(USB_BASE + 0x103 + n*0x10)
+
+/* USB Maximum Receive Data Endpoint [1-7] */
+#define USB_RXMAXP(n) MMIO16(USB_BASE + 0x104 + n*0x10)
+
+/* USB Receive Control and Status Endpoint [1-7] Low */
+#define USB_RXCSRL(n) MMIO8(USB_BASE + 0x106 + n*0x10)
+
+/* USB Receive Control and Status Endpoint [1-7] High */
+#define USB_RXCSRH(n) MMIO8(USB_BASE + 0x107 + n*0x10)
+
+/* USB Receive Byte Count Endpoint [1-7] */
+#define USB_RXCOUNT(n) MMIO16(USB_BASE + 0x108 + n*0x10)
+
+/* USB Receive Double Packet Buffer Disable */
+#define USB_RXDPKTBUFDIS MMIO16(USB_BASE + 0x340)
+
+/* USB Transmit Double Packet Buffer Disable */
+#define USB_TXDPKTBUFDIS MMIO16(USB_BASE + 0x342)
+
+/* USB Device RESUME Raw Interrupt Status */
+#define USB_DRRIS MMIO32(USB_BASE + 0x410)
+
+/* USB Device RESUME Interrupt Mask */
+#define USB_DRIM MMIO32(USB_BASE + 0x414)
+
+/* USB Device RESUME Interrupt Status and Clear */
+#define USB_DRISC MMIO32(USB_BASE + 0x418)
+
+/* USB DMA Select */
+#define USB_DMASEL MMIO32(USB_BASE + 0x450)
+
+/* USB Peripheral Properties */
+#define USB_PP MMIO32(USB_BASE + 0xFC0)
+
+
+/* =============================================================================
+ * USB_FADDR values
+ * ---------------------------------------------------------------------------*/
+/** Function Address */
+#define USB_FADDR_FUNCADDR_MASK (0x3f << 0)
+
+/* =============================================================================
+ * USB_POWER values
+ * ---------------------------------------------------------------------------*/
+/** Isochronous Update */
+#define USB_POWER_ISOUP (1 << 7)
+/** Soft Connect/Disconnect */
+#define USB_POWER_SOFTCONN (1 << 6)
+/** RESET signaling */
+#define USB_POWER_RESET (1 << 3)
+/** RESUME signaling */
+#define USB_POWER_RESUME (1 << 2)
+/** SUSPEND mode */
+#define USB_POWER_SUSPEND (1 << 1)
+/** Power down PHY */
+#define USB_POWER_PWRDNPHY (1 << 0)
+
+/* =============================================================================
+ * Endpoint bitmasks for interrupt status and control registers
+ * Applies to USB_TXIS, USB_RXIS, USB_TXIE, USB_RXIE, USB_RXDPKTBUFDIS,
+ * USB_TXDPKTBUFDIS
+ * ---------------------------------------------------------------------------*/
+#define USB_EP7 (1 << 7)
+#define USB_EP6 (1 << 6)
+#define USB_EP5 (1 << 5)
+#define USB_EP4 (1 << 4)
+#define USB_EP3 (1 << 3)
+#define USB_EP2 (1 << 2)
+#define USB_EP1 (1 << 1)
+#define USB_EP0 (1 << 0)
+
+/* =============================================================================
+ * USB interrupt mask values
+ *
+ * These are interchangeable across USB_IS, and USB_IE registers.
+ * ---------------------------------------------------------------------------*/
+/** USB disconnect interrupt */
+#define USB_IM_DISCON (1 << 5)
+/** Start of frame */
+#define USB_IM_SOF (1 << 3)
+/** RESET signaling detected */
+#define USB_IM_RESET (1 << 2)
+/** RESUME signaling detected */
+#define USB_IM_RESUME (1 << 1)
+/** SUSPEND signaling detected */
+#define USB_IM_SUSPEND (1 << 0)
+
+/* =============================================================================
+ * USB_FRAME values
+ * ---------------------------------------------------------------------------*/
+/** Frame number */
+#define USB_FRAME_MASK (0x03FF)
+
+/* =============================================================================
+ * USB_IDX values
+ * ---------------------------------------------------------------------------*/
+/** Endpoint Index */
+#define USB_EPIDX_MASK (0x0F)
+
+/* =============================================================================
+ * USB_TEST values
+ * ---------------------------------------------------------------------------*/
+/** FIFO access */
+#define USB_TEST_FIFOACC (1 << 6)
+/** Force full-speed mode */
+#define USB_TEST_FORCEFS (1 << 5)
+
+/* =============================================================================
+ * USB_TXFIFOSZ and USB_RXFIFOSZ values
+ * ---------------------------------------------------------------------------*/
+/** Double packet buffer support */
+#define USB_FIFOSZ_DPB (1 << 4)
+/* USB Transmit Dynamic FIFO Sizing */
+#define USB_FIFOSZ_SIZE_MASK (0x0F << 0)
+#define USB_FIFOSZ_SIZE_8 (0x00 << 0)
+#define USB_FIFOSZ_SIZE_16 (0x01 << 0)
+#define USB_FIFOSZ_SIZE_32 (0x02 << 0)
+#define USB_FIFOSZ_SIZE_64 (0x03 << 0)
+#define USB_FIFOSZ_SIZE_128 (0x04 << 0)
+#define USB_FIFOSZ_SIZE_256 (0x05 << 0)
+#define USB_FIFOSZ_SIZE_512 (0x06 << 0)
+#define USB_FIFOSZ_SIZE_1024 (0x07 << 0)
+#define USB_FIFOSZ_SIZE_2048 (0x08 << 0)
+
+
+/* =============================================================================
+ * USB_CONTIM values
+ * ---------------------------------------------------------------------------*/
+/** Connect wait */
+#define USB_CONTIM_WTCON_MASK (0x0F << 4)
+/** Wait ID */
+#define USB_CONTIM_WTID_MASK (0x0F << 0)
+
+/* =============================================================================
+ * USB_CSRL0 values
+ * ---------------------------------------------------------------------------*/
+/** Setup End Clear */
+#define USB_CSRL0_SETENDC (1 << 7)
+/** RXRDY Clear */
+#define USB_CSRL0_RXRDYC (1 << 6)
+/** Send Stall */
+#define USB_CSRL0_STALL (1 << 5)
+/** Setup End */
+#define USB_CSRL0_SETEND (1 << 4)
+/** Data End */
+#define USB_CSRL0_DATAEND (1 << 3)
+/** Endpoint Stalled */
+#define USB_CSRL0_STALLED (1 << 2)
+/** Transmit Packet Ready */
+#define USB_CSRL0_TXRDY (1 << 1)
+/** Receive Packet Ready */
+#define USB_CSRL0_RXRDY (1 << 0)
+
+/* =============================================================================
+ * USB_CSRH0 values
+ * ---------------------------------------------------------------------------*/
+/** Flush FIFO */
+#define USB_CSRH0_FLUSH (1 << 0)
+
+/* =============================================================================
+ * USB_TXCSRLx values
+ * ---------------------------------------------------------------------------*/
+/** Clear data toggle */
+#define USB_TXCSRL_CLRDT (1 << 6)
+/** Endpoint Stalled */
+#define USB_TXCSRL_STALLED (1 << 5)
+/** Send Stall */
+#define USB_TXCSRL_STALL (1 << 4)
+/** Flush FIFO */
+#define USB_TXCSRL_FLUSH (1 << 3)
+/** Underrun */
+#define USB_TXCSRL_UNDRN (1 << 2)
+/** FIFO not empty */
+#define USB_TXCSRL_FIFONE (1 << 1)
+/** Transmit Packet Ready */
+#define USB_TXCSRL_TXRDY (1 << 0)
+
+/* =============================================================================
+ * USB_TXCSRHx values
+ * ---------------------------------------------------------------------------*/
+/** Auto set */
+#define USB_TXCSRH_AUTOSET (1 << 7)
+/** Isochronous transfers */
+#define USB_TXCSRH_ISO (1 << 6)
+/** Mode */
+#define USB_TXCSRH_MODE (1 << 5)
+/** DMA request enable */
+#define USB_TXCSRH_DMAEN (1 << 4)
+/** Force data toggle */
+#define USB_TXCSRH_FDT (1 << 3)
+/** DMA request mode */
+#define USB_TXCSRH_DMAMOD (1 << 2)
+
+/* =============================================================================
+ * USB_RXCSRLx values
+ * ---------------------------------------------------------------------------*/
+/** Clear data toggle */
+#define USB_RXCSRL_CLRDT (1 << 7)
+/** Endpoint Stalled */
+#define USB_RXCSRL_STALLED (1 << 6)
+/** Send Stall */
+#define USB_RXCSRL_STALL (1 << 5)
+/** Flush FIFO */
+#define USB_RXCSRL_FLUSH (1 << 4)
+/** Data error */
+#define USB_RXCSRL_DATAERR (1 << 2)
+/** Overrun */
+#define USB_RXCSRL_OVER (1 << 2)
+/** FIFO full */
+#define USB_RXCSRL_FULL (1 << 1)
+/** Receive Packet Ready */
+#define USB_RXCSRL_RXRDY (1 << 0)
+
+/* =============================================================================
+ * USB_RXCSRHx values
+ * ---------------------------------------------------------------------------*/
+/** Auto clear */
+#define USB_RXCSRH_AUTOCL (1 << 7)
+/** Isochronous transfers */
+#define USB_RXCSRH_ISO (1 << 6)
+/** DMA request enable */
+#define USB_RXCSRH_DMAEN (1 << 5)
+/** Disable NYET / PID error */
+#define USB_RXCSRH_PIDERR (1 << 4)
+/** DMA request mode */
+#define USB_RXCSRH_DMAMOD (1 << 3)
+
+/* =============================================================================
+ * USB_DRRIS values
+ * ---------------------------------------------------------------------------*/
+/** RESUME interrupt status */
+#define USB_DRRIS_RESUME (1 << 0)
+
+/* =============================================================================
+ * USB_DRIM values
+ * ---------------------------------------------------------------------------*/
+/** RESUME interrupt mask */
+#define USB_DRIM_RESUME (1 << 0)
+
+/* =============================================================================
+ * USB_DRISC values
+ * ---------------------------------------------------------------------------*/
+/** RESUME interrupt status and clear */
+#define USB_DRISC_RESUME (1 << 0)
+
+/* =============================================================================
+ * USB_PP values
+ * ---------------------------------------------------------------------------*/
+/** Endpoint count */
+#define USB_PP_ECNT_MASK (0xFF << 8)
+/** USB capability */
+#define USB_PP_USB_MASK (0x03 << 6)
+#define USB_PP_USB_NA (0x00 << 6)
+#define USB_PP_USB_DEVICE (0x01 << 6)
+#define USB_PP_USB_HOST (0x02 << 6)
+#define USB_PP_USB_OTG (0x03 << 6)
+/** PHY present */
+#define USB_PP_PHY (1 << 4)
+/** Controller type */
+#define USB_PP_TYPE_MASK (0x0F << 0)
+
+/* =============================================================================
+ * Convenience enums
+ * ---------------------------------------------------------------------------*/
+enum usb_interrupt {
+ USB_INT_DISCON = USB_IM_DISCON,
+ USB_INT_SOF = USB_IM_SOF,
+ USB_INT_RESET = USB_IM_RESET,
+ USB_INT_RESUME = USB_IM_RESUME,
+ USB_INT_SUSPEND = USB_IM_SUSPEND,
+};
+
+enum usb_ep_interrupt {
+ USB_EP0_INT = USB_EP0,
+ USB_EP1_INT = USB_EP1,
+ USB_EP2_INT = USB_EP2,
+ USB_EP3_INT = USB_EP3,
+ USB_EP4_INT = USB_EP4,
+ USB_EP5_INT = USB_EP5,
+ USB_EP6_INT = USB_EP6,
+ USB_EP7_INT = USB_EP7,
+};
+/* =============================================================================
+ * Function prototypes
+ * ---------------------------------------------------------------------------*/
+BEGIN_DECLS
+
+void usb_enable_interrupts(enum usb_interrupt ints,
+ enum usb_ep_interrupt rx_ints,
+ enum usb_ep_interrupt tx_ints);
+void usb_disable_interrupts(enum usb_interrupt ints,
+ enum usb_ep_interrupt rx_ints,
+ enum usb_ep_interrupt tx_ints);
+
+END_DECLS
+
+/**@}*/
+
+#endif /* LIBOPENCM3_LM4F_USB_H */
diff --git a/libopencm3/include/libopencm3/lpc13xx/doc-lpc13xx.h b/libopencm3/include/libopencm3/lpc13xx/doc-lpc13xx.h
new file mode 100644
index 0000000..5ed7cae
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc13xx/doc-lpc13xx.h
@@ -0,0 +1,32 @@
+/** @mainpage libopencm3 LPC13xx
+
+@version 1.0.0
+
+@date 14 September 2012
+
+API documentation for NXP Semiconductors LPC13xx Cortex M3 series.
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup LPC13xx LPC13xx
+Libraries for NXP Semiconductors LPC13xx series.
+
+@version 1.0.0
+
+@date 14 September 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup LPC13xx_defines LPC13xx Defines
+
+@brief Defined Constants and Types for the LPC13xx series
+
+@version 1.0.0
+
+@date 14 September 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
diff --git a/libopencm3/include/libopencm3/lpc13xx/gpio.h b/libopencm3/include/libopencm3/lpc13xx/gpio.h
new file mode 100644
index 0000000..907533a
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc13xx/gpio.h
@@ -0,0 +1,124 @@
+/** @defgroup gpio_defines GPIO Defines
+
+@brief Defined Constants and Types for the LPC13xx General Purpose I/O
+
+@ingroup LPC13xx_defines
+
+@version 1.0.0
+
+@author @htmlonly © @endhtmlonly 2009 Uwe Hermann
+
+@date 10 March 2013
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Uwe Hermann
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+/**@{*/
+
+#ifndef LPC13XX_GPIO_H
+#define LPC13XX_GPIO_H
+
+#include
+#include
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* GPIO port base addresses (for convenience) */
+#define GPIO0 GPIO_PIO0_BASE
+#define GPIO1 GPIO_PIO1_BASE
+#define GPIO2 GPIO_PIO2_BASE
+#define GPIO3 GPIO_PIO3_BASE
+
+/* --- GPIO registers ------------------------------------------------------ */
+
+/* GPIO data register (GPIOn_DATA) */
+#define GPIO_DATA(port) MMIO32(port + 0x3ffc)
+#define GPIO0_DATA GPIO_DATA(GPIO0)
+#define GPIO1_DATA GPIO_DATA(GPIO1)
+#define GPIO2_DATA GPIO_DATA(GPIO2)
+#define GPIO3_DATA GPIO_DATA(GPIO3)
+
+/* GPIO data direction register (GPIOn_DIR) */
+#define GPIO_DIR(port) MMIO32(port + 0x00)
+#define GPIO0_DIR GPIO_DIR(GPIO0)
+#define GPIO1_DIR GPIO_DIR(GPIO1)
+#define GPIO2_DIR GPIO_DIR(GPIO2)
+#define GPIO3_DIR GPIO_DIR(GPIO3)
+
+/* GPIO interrupt sense register (GPIOn_IS) */
+#define GPIO_IS(port) MMIO32(port + 0x04)
+#define GPIO0_IS GPIO_IS(GPIO0)
+#define GPIO1_IS GPIO_IS(GPIO1)
+#define GPIO2_IS GPIO_IS(GPIO2)
+#define GPIO3_IS GPIO_IS(GPIO3)
+
+/* GPIO interrupt both edges sense register (GPIOn_IBE) */
+#define GPIO_IBE(port) MMIO32(port + 0x08)
+#define GPIO0_IBE GPIO_IBE(GPIO0)
+#define GPIO1_IBE GPIO_IBE(GPIO1)
+#define GPIO2_IBE GPIO_IBE(GPIO2)
+#define GPIO3_IBE GPIO_IBE(GPIO3)
+
+/* GPIO interrupt event register (GPIOn_IEV) */
+#define GPIO_IEV(port) MMIO32(port + 0x0c)
+#define GPIO0_IEV GPIO_IEV(GPIO0)
+#define GPIO1_IEV GPIO_IEV(GPIO1)
+#define GPIO2_IEV GPIO_IEV(GPIO2)
+#define GPIO3_IEV GPIO_IEV(GPIO3)
+
+/* GPIO interrupt mask register (GPIOn_IE) */
+#define GPIO_IE(port) MMIO16(port + 0x10)
+#define GPIO0_IE GPIO_IE(GPIO0)
+#define GPIO1_IE GPIO_IE(GPIO1)
+#define GPIO2_IE GPIO_IE(GPIO2)
+#define GPIO3_IE GPIO_IE(GPIO3)
+
+/* FIXME: IRS or RIS? Datasheet is not consistent here. */
+/* GPIO raw interrupt status register (GPIOn_IRS) */
+#define GPIO_IRS(port) MMIO16(port + 0x14)
+#define GPIO0_IRS GPIO_IRS(GPIO0)
+#define GPIO1_IRS GPIO_IRS(GPIO1)
+#define GPIO2_IRS GPIO_IRS(GPIO2)
+#define GPIO3_IRS GPIO_IRS(GPIO3)
+
+/* GPIO masked interrupt status register (GPIOn_MIS) */
+#define GPIO_MIS(port) MMIO16(port + 0x18)
+#define GPIO0_MIS GPIO_MIS(GPIO0)
+#define GPIO1_MIS GPIO_MIS(GPIO1)
+#define GPIO2_MIS GPIO_MIS(GPIO2)
+#define GPIO3_MIS GPIO_MIS(GPIO3)
+
+/* GPIO interrupt clear register (GPIOn_IC) */
+#define GPIO_IC(port) MMIO16(port + 0x1c)
+#define GPIO0_IC GPIO_IC(GPIO0)
+#define GPIO1_IC GPIO_IC(GPIO1)
+#define GPIO2_IC GPIO_IC(GPIO2)
+#define GPIO3_IC GPIO_IC(GPIO3)
+
+BEGIN_DECLS
+
+void gpio_set(uint32_t gpioport, uint16_t gpios);
+
+END_DECLS
+
+/**@}*/
+
+#endif
diff --git a/libopencm3/include/libopencm3/lpc13xx/irq.json b/libopencm3/include/libopencm3/lpc13xx/irq.json
new file mode 100644
index 0000000..d9ac31f
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc13xx/irq.json
@@ -0,0 +1,63 @@
+{
+ "irqs": {
+ "0": "pio0_0",
+ "1": "pio0_1",
+ "2": "pio0_2",
+ "3": "pio0_3",
+ "4": "pio0_4",
+ "5": "pio0_5",
+ "6": "pio0_6",
+ "7": "pio0_7",
+ "8": "pio0_8",
+ "9": "pio0_9",
+ "10": "pio0_10",
+ "11": "pio0_11",
+ "12": "pio1_0",
+ "13": "pio1_1",
+ "14": "pio1_2",
+ "15": "pio1_3",
+ "16": "pio1_4",
+ "17": "pio1_5",
+ "18": "pio1_6",
+ "19": "pio1_7",
+ "20": "pio1_8",
+ "21": "pio1_9",
+ "22": "pio1_10",
+ "23": "pio1_11",
+ "24": "pio2_0",
+ "25": "pio2_1",
+ "26": "pio2_2",
+ "27": "pio2_3",
+ "28": "pio2_4",
+ "29": "pio2_5",
+ "30": "pio2_6",
+ "31": "pio2_7",
+ "32": "pio2_8",
+ "33": "pio2_9",
+ "34": "pio2_10",
+ "35": "pio2_11",
+ "36": "pio3_0",
+ "37": "pio3_1",
+ "38": "pio3_2",
+ "39": "pio3_3",
+ "40": "i2c0",
+ "41": "ct16b0",
+ "42": "ct16b1",
+ "43": "ct32b0",
+ "44": "ct32b1",
+ "45": "ssp0",
+ "46": "uart",
+ "47": "usb",
+ "48": "usb_fiq",
+ "49": "adc",
+ "50": "wdt",
+ "51": "bod",
+ "53": "pio3",
+ "54": "pio2",
+ "55": "pio1",
+ "56": "ssp1"
+ },
+ "partname_humanreadable": "LPC 13xx series",
+ "partname_doxygen": "LPC13xx",
+ "includeguard": "LIBOPENCM3_LPC13xx_NVIC_H"
+}
\ No newline at end of file
diff --git a/libopencm3/include/libopencm3/lpc13xx/memorymap.h b/libopencm3/include/libopencm3/lpc13xx/memorymap.h
new file mode 100644
index 0000000..01b94b2
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc13xx/memorymap.h
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Uwe Hermann
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LPC13XX_MEMORYMAP_H
+#define LPC13XX_MEMORYMAP_H
+
+#include
+
+/* --- LPC13XX specific peripheral definitions ----------------------------- */
+
+/* Memory map for all busses */
+#define PERIPH_BASE_APB (0x40000000U)
+#define PERIPH_BASE_AHB (0x50000000U)
+
+/* Register boundary addresses */
+
+/* APB */
+#define I2C_BASE (PERIPH_BASE_APB + 0x00000)
+#define WDT_BASE (PERIPH_BASE_APB + 0x04000)
+#define UART_BASE (PERIPH_BASE_APB + 0x08000)
+#define TIMER0_16BIT_BASE (PERIPH_BASE_APB + 0x0c000)
+#define TIMER1_16BIT_BASE (PERIPH_BASE_APB + 0x10000)
+#define TIMER0_32BIT_BASE (PERIPH_BASE_APB + 0x14000)
+#define TIMER1_32BIT_BASE (PERIPH_BASE_APB + 0x18000)
+#define ADC_BASE (PERIPH_BASE_APB + 0x1c000)
+#define USB_BASE (PERIPH_BASE_APB + 0x20000)
+/* PERIPH_BASE_APB + 0x28000 (0x4002 8000 - 0x4003 7FFF): Reserved */
+#define PMU_BASE (PERIPH_BASE_APB + 0x38000)
+#define FLASH_BASE (PERIPH_BASE_APB + 0x3c000)
+#define SSP_BASE (PERIPH_BASE_APB + 0x40000)
+#define IOCONFIG_BASE (PERIPH_BASE_APB + 0x44000)
+#define SYSCTRL_BASE (PERIPH_BASE_APB + 0x48000)
+/* PERIPH_BASE_APB + 0x4c000 (0x4004 c000 - 0x4007 FFFF): Reserved */
+
+/* AHB */
+#define GPIO_PIO0_BASE (PERIPH_BASE_AHB + 0x00000)
+#define GPIO_PIO1_BASE (PERIPH_BASE_AHB + 0x10000)
+#define GPIO_PIO2_BASE (PERIPH_BASE_AHB + 0x20000)
+#define GPIO_PIO3_BASE (PERIPH_BASE_AHB + 0x30000)
+/* PERIPH_BASE_AHB + 0x40000 (0x5004 0000 - 0x501F FFFF): Reserved */
+
+#endif
diff --git a/libopencm3/include/libopencm3/lpc17xx/doc-lpc17xx.h b/libopencm3/include/libopencm3/lpc17xx/doc-lpc17xx.h
new file mode 100644
index 0000000..4bc603d
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc17xx/doc-lpc17xx.h
@@ -0,0 +1,32 @@
+/** @mainpage libopencm3 LPC17xx
+
+@version 1.0.0
+
+@date 14 September 2012
+
+API documentation for NXP Semiconductors LPC17xx Cortex M3 series.
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup LPC17xx LPC17xx
+Libraries for NXP Semiconductors LPC17xx series.
+
+@version 1.0.0
+
+@date 14 September 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup LPC17xx_defines LPC17xx Defines
+
+@brief Defined Constants and Types for the LPC17xx series
+
+@version 1.0.0
+
+@date 14 September 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
diff --git a/libopencm3/include/libopencm3/lpc17xx/gpio.h b/libopencm3/include/libopencm3/lpc17xx/gpio.h
new file mode 100644
index 0000000..2aecd6b
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc17xx/gpio.h
@@ -0,0 +1,160 @@
+/** @defgroup gpio_defines GPIO Defines
+
+@brief Defined Constants and Types for the LPC17xx General Purpose I/O
+
+@ingroup LPC17xx_defines
+
+@version 1.0.0
+
+@author @htmlonly © @endhtmlonly 2009 Uwe Hermann
+
+@date 10 March 2013
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Uwe Hermann
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LPC17XX_GPIO_H
+#define LPC17XX_GPIO_H
+
+/**@{*/
+
+#include
+#include
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* GPIO port base addresses (for convenience) */
+#define GPIO0 GPIO_PIO0_BASE
+#define GPIO1 GPIO_PIO1_BASE
+#define GPIO2 GPIO_PIO2_BASE
+#define GPIO3 GPIO_PIO3_BASE
+#define GPIO4 GPIO_PIO4_BASE
+
+/* GPIO number definitions (for convenience) */
+#define GPIOPIN0 (1 << 0)
+#define GPIOPIN1 (1 << 1)
+#define GPIOPIN2 (1 << 2)
+#define GPIOPIN3 (1 << 3)
+#define GPIOPIN4 (1 << 4)
+#define GPIOPIN5 (1 << 5)
+#define GPIOPIN6 (1 << 6)
+#define GPIOPIN7 (1 << 7)
+#define GPIOPIN8 (1 << 8)
+#define GPIOPIN9 (1 << 9)
+#define GPIOPIN10 (1 << 10)
+#define GPIOPIN11 (1 << 11)
+#define GPIOPIN12 (1 << 12)
+#define GPIOPIN13 (1 << 13)
+#define GPIOPIN14 (1 << 14)
+#define GPIOPIN15 (1 << 15)
+#define GPIOPIN16 (1 << 16)
+#define GPIOPIN17 (1 << 17)
+#define GPIOPIN18 (1 << 18)
+#define GPIOPIN19 (1 << 19)
+#define GPIOPIN20 (1 << 20)
+#define GPIOPIN21 (1 << 21)
+#define GPIOPIN22 (1 << 22)
+#define GPIOPIN23 (1 << 23)
+#define GPIOPIN24 (1 << 24)
+#define GPIOPIN25 (1 << 25)
+#define GPIOPIN26 (1 << 26)
+#define GPIOPIN27 (1 << 27)
+#define GPIOPIN28 (1 << 28)
+#define GPIOPIN29 (1 << 29)
+#define GPIOPIN30 (1 << 30)
+#define GPIOPIN31 (1 << 31)
+
+/* --- GPIO registers ------------------------------------------------------ */
+
+/* GPIO data direction register (GPIOn_DIR) */
+#define GPIO_DIR(port) MMIO32(port + 0x00)
+#define GPIO0_DIR GPIO_DIR(GPIO0)
+#define GPIO1_DIR GPIO_DIR(GPIO1)
+#define GPIO2_DIR GPIO_DIR(GPIO2)
+#define GPIO3_DIR GPIO_DIR(GPIO3)
+#define GPIO4_DIR GPIO_DIR(GPIO4)
+
+/* GPIO fast mask register (GPIOn_DIR) */
+#define GPIO_MASK(port) MMIO32(port + 0x10)
+#define GPIO0_MASK GPIO_MASK(GPIO0)
+#define GPIO1_MASK GPIO_MASK(GPIO1)
+#define GPIO2_MASK GPIO_MASK(GPIO2)
+#define GPIO3_MASK GPIO_MASK(GPIO3)
+#define GPIO4_MASK GPIO_MASK(GPIO4)
+
+/* GPIO port pin value register (GPIOn_PIN) */
+#define GPIO_PIN(port) MMIO32(port + 0x14)
+#define GPIO0_PIN GPIO_PIN(GPIO0)
+#define GPIO1_PIN GPIO_PIN(GPIO1)
+#define GPIO2_PIN GPIO_PIN(GPIO2)
+#define GPIO3_PIN GPIO_PIN(GPIO3)
+#define GPIO4_PIN GPIO_PIN(GPIO4)
+
+/* GPIO port output set register (GPIOn_SET) */
+#define GPIO_SET(port) MMIO32(port + 0x18)
+#define GPIO0_SET GPIO_SET(GPIO0)
+#define GPIO1_SET GPIO_SET(GPIO1)
+#define GPIO2_SET GPIO_SET(GPIO2)
+#define GPIO3_SET GPIO_SET(GPIO3)
+#define GPIO4_SET GPIO_SET(GPIO4)
+
+/* GPIO port output clear register (GPIOn_CLR) */
+#define GPIO_CLR(port) MMIO32(port + 0x1C)
+#define GPIO0_CLR GPIO_CLR(GPIO0)
+#define GPIO1_CLR GPIO_CLR(GPIO1)
+#define GPIO2_CLR GPIO_CLR(GPIO2)
+#define GPIO3_CLR GPIO_CLR(GPIO3)
+#define GPIO4_CLR GPIO_CLR(GPIO4)
+
+/* GPIO interrupt register map */
+/* Interrupt enable rising edge */
+#define GPIO0_IER MMIO32(GPIOINTERRUPT_BASE + 0x90)
+#define GPIO2_IER MMIO32(GPIOINTERRUPT_BASE + 0xB0)
+
+/* Interrupt enable falling edge */
+#define GPIO0_IEF MMIO32(GPIOINTERRUPT_BASE + 0x94)
+#define GPIO2_IEF MMIO32(GPIOINTERRUPT_BASE + 0xB4)
+
+/* Interrupt status rising edge */
+#define GPIO0_ISR MMIO32(GPIOINTERRUPT_BASE + 0x84)
+#define GPIO2_ISR MMIO32(GPIOINTERRUPT_BASE + 0xA4)
+
+/* Interrupt status falling edge */
+#define GPIO0_ISF MMIO32(GPIOINTERRUPT_BASE + 0x88)
+#define GPIO2_ISF MMIO32(GPIOINTERRUPT_BASE + 0xA8)
+
+/* Interrupt clear */
+#define GPIO0_IC MMIO32(GPIOINTERRUPT_BASE + 0x8C)
+#define GPIO1_IC MMIO32(GPIOINTERRUPT_BASE + 0xAC)
+
+/* Overall interrupt status */
+#define GPIO_IS MMIO32(GPIOINTERRUPT_BASE + 0x80)
+
+BEGIN_DECLS
+
+void gpio_set(uint32_t gpioport, uint32_t gpios);
+void gpio_clear(uint32_t gpioport, uint32_t gpios);
+
+END_DECLS
+
+/**@}*/
+
+#endif
diff --git a/libopencm3/include/libopencm3/lpc17xx/irq.json b/libopencm3/include/libopencm3/lpc17xx/irq.json
new file mode 100644
index 0000000..94eec07
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc17xx/irq.json
@@ -0,0 +1,42 @@
+{
+ "irqs": {
+ "0": "wdt",
+ "1": "timer0",
+ "2": "timer1",
+ "3": "timer2",
+ "4": "timer3",
+ "5": "uart0",
+ "6": "uart1",
+ "7": "uart2",
+ "8": "uart3",
+ "9": "pwm",
+ "10": "i2c0",
+ "11": "i2c1",
+ "12": "i2c2",
+ "13": "spi",
+ "14": "ssp0",
+ "15": "ssp1",
+ "16": "pll0",
+ "17": "rtc",
+ "18": "eint0",
+ "19": "eint1",
+ "20": "eint2",
+ "21": "eint3",
+ "22": "adc",
+ "23": "bod",
+ "24": "usb",
+ "25": "can",
+ "26": "gpdma",
+ "27": "i2s",
+ "28": "ethernet",
+ "29": "rit",
+ "30": "motor_pwm",
+ "31": "qei",
+ "32": "pll1",
+ "33": "usb_act",
+ "34": "can_act"
+ },
+ "partname_humanreadable": "LPC 17xx series",
+ "partname_doxygen": "LPC17xx",
+ "includeguard": "LIBOPENCM3_LPC17xx_NVIC_H"
+}
\ No newline at end of file
diff --git a/libopencm3/include/libopencm3/lpc17xx/memorymap.h b/libopencm3/include/libopencm3/lpc17xx/memorymap.h
new file mode 100644
index 0000000..b82a51b
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc17xx/memorymap.h
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Uwe Hermann
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LPC17XX_MEMORYMAP_H
+#define LPC17XX_MEMORYMAP_H
+
+#include
+
+/* --- LPC17XX specific peripheral definitions ----------------------------- */
+
+/* Memory map for all busses */
+#define PERIPH_BASE_APB0 (0x40000000U)
+#define PERIPH_BASE_APB1 (0x40080000U)
+#define PERIPH_BASE_AHB (0x20000000U)
+
+/* Register boundary addresses */
+
+/* APB0 */
+#define WDT_BASE (PERIPH_BASE_APB0 + 0x00000)
+#define TIMER0_BASE (PERIPH_BASE_APB0 + 0x04000)
+#define TIMER1_BASE (PERIPH_BASE_APB0 + 0x08000)
+#define UART0_BASE (PERIPH_BASE_APB0 + 0x0c000)
+#define UART1_BASE (PERIPH_BASE_APB0 + 0x10000)
+/* PERIPH_BASE_APB0 + 0X14000 (0x4001 4000 - 0x4001 7FFF): Reserved */
+#define PWM1_BASE (PERIPH_BASE_APB0 + 0x18000)
+#define I2C0_BASE (PERIPH_BASE_APB0 + 0x1c000)
+#define SPI_BASE (PERIPH_BASE_APB0 + 0x20000)
+#define RTC_BASE (PERIPH_BASE_APB0 + 0x24000)
+#define GPIOINTERRUPT_BASE (PERIPH_BASE_APB0 + 0x28000)
+#define PINCONNECT_BASE (PERIPH_BASE_APB0 + 0x2c000)
+#define SSP1_BASE (PERIPH_BASE_APB0 + 0x30000)
+#define ADC_BASE (PERIPH_BASE_APB0 + 0x34000)
+#define CANAFRAM_BASE (PERIPH_BASE_APB0 + 0x38000)
+#define CANAFREG_BASE (PERIPH_BASE_APB0 + 0x3C000)
+#define CANCOMMONREG_BASE (PERIPH_BASE_APB0 + 0x40000)
+#define CAN1_BASE (PERIPH_BASE_APB0 + 0x44000)
+#define CAN2_BASE (PERIPH_BASE_APB0 + 0x48000)
+/* PERIPH_BASE_APB0 + 0X4C000 (0x4004 C000 - 0x4005 BFFF): Reserved */
+#define I2C1_BASE (PERIPH_BASE_APB0 + 0x5C000)
+/* PERIPH_BASE_APB0 + 0X60000 (0x6000 0000 - 0x4007 BFFF): Reserved */
+
+/* AHB */
+#define GPIO_PIO0_BASE (PERIPH_BASE_AHB + 0x9c000)
+#define GPIO_PIO1_BASE (PERIPH_BASE_AHB + 0x9c020)
+#define GPIO_PIO2_BASE (PERIPH_BASE_AHB + 0x9c040)
+#define GPIO_PIO3_BASE (PERIPH_BASE_AHB + 0x9c060)
+#define GPIO_PIO4_BASE (PERIPH_BASE_AHB + 0x9c080)
+
+#endif
diff --git a/libopencm3/include/libopencm3/lpc43xx/adc.h b/libopencm3/include/libopencm3/lpc43xx/adc.h
new file mode 100644
index 0000000..c63c1e4
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc43xx/adc.h
@@ -0,0 +1,113 @@
+/** @defgroup adc_defines ADC Defines
+
+@brief Defined Constants and Types for the LPC43xx A/D Converter
+
+@ingroup LPC43xx_defines
+
+@version 1.0.0
+
+@author @htmlonly © @endhtmlonly 2012 Michael Ossmann
+
+@date 10 March 2013
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Michael Ossmann
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LPC43XX_ADC_H
+#define LPC43XX_ADC_H
+
+/**@{*/
+
+#include
+#include
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* ADC port base addresses (for convenience) */
+#define ADC0 ADC0_BASE
+#define ADC1 ADC1_BASE
+
+
+/* --- ADC registers ------------------------------------------------------- */
+
+/* A/D Control Register */
+#define ADC_CR(port) MMIO32(port + 0x000)
+#define ADC0_CR ADC_CR(ADC0)
+#define ADC1_CR ADC_CR(ADC1)
+
+/* A/D Global Data Register */
+#define ADC_GDR(port) MMIO32(port + 0x004)
+#define ADC0_GDR ADC_GDR(ADC0)
+#define ADC1_GDR ADC_GDR(ADC1)
+
+/* A/D Interrupt Enable Register */
+#define ADC_INTEN(port) MMIO32(port + 0x00C)
+#define ADC0_INTEN ADC_INTEN(ADC0)
+#define ADC1_INTEN ADC_INTEN(ADC1)
+
+/* A/D Channel 0 Data Register */
+#define ADC_DR0(port) MMIO32(port + 0x010)
+#define ADC0_DR0 ADC_DR0(ADC0)
+#define ADC1_DR0 ADC_DR0(ADC1)
+
+/* A/D Channel 1 Data Register */
+#define ADC_DR1(port) MMIO32(port + 0x014)
+#define ADC0_DR1 ADC_DR1(ADC0)
+#define ADC1_DR1 ADC_DR1(ADC1)
+
+/* A/D Channel 2 Data Register */
+#define ADC_DR2(port) MMIO32(port + 0x018)
+#define ADC0_DR2 ADC_DR2(ADC0)
+#define ADC1_DR2 ADC_DR2(ADC1)
+
+/* A/D Channel 3 Data Register */
+#define ADC_DR3(port) MMIO32(port + 0x01C)
+#define ADC0_DR3 ADC_DR3(ADC0)
+#define ADC1_DR3 ADC_DR3(ADC1)
+
+/* A/D Channel 4 Data Register */
+#define ADC_DR4(port) MMIO32(port + 0x020)
+#define ADC0_DR4 ADC_DR4(ADC0)
+#define ADC1_DR4 ADC_DR4(ADC1)
+
+/* A/D Channel 5 Data Register */
+#define ADC_DR5(port) MMIO32(port + 0x024)
+#define ADC0_DR5 ADC_DR5(ADC0)
+#define ADC1_DR5 ADC_DR5(ADC1)
+
+/* A/D Channel 6 Data Register */
+#define ADC_DR6(port) MMIO32(port + 0x028)
+#define ADC0_DR6 ADC_DR6(ADC0)
+#define ADC1_DR6 ADC_DR6(ADC1)
+
+/* A/D Channel 7 Data Register */
+#define ADC_DR7(port) MMIO32(port + 0x02C)
+#define ADC0_DR7 ADC_DR7(ADC0)
+#define ADC1_DR7 ADC_DR7(ADC1)
+
+/* A/D Status Register */
+#define ADC_STAT(port) MMIO32(port + 0x030)
+#define ADC0_STAT ADC_STAT(ADC0)
+#define ADC1_STAT ADC_STAT(ADC1)
+
+/**@}*/
+
+#endif
diff --git a/libopencm3/include/libopencm3/lpc43xx/atimer.h b/libopencm3/include/libopencm3/lpc43xx/atimer.h
new file mode 100644
index 0000000..cbb70d7
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc43xx/atimer.h
@@ -0,0 +1,70 @@
+/** @defgroup atimer_defines Alarm Timer Defines
+
+@brief Defined Constants and Types for the LPC43xx Alarm Timer
+
+@ingroup LPC43xx_defines
+
+@version 1.0.0
+
+@author @htmlonly © @endhtmlonly 2012 Michael Ossmann
+
+@date 10 March 2013
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Michael Ossmann
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LPC43XX_ATIMER_H
+#define LPC43XX_ATIMER_H
+
+/**@{*/
+
+#include
+#include
+
+/* --- Alarm Timer registers ----------------------------------------------- */
+
+/* Downcounter register */
+#define ATIMER_DOWNCOUNTER MMIO32(ATIMER_BASE + 0x000)
+
+/* Preset value register */
+#define ATIMER_PRESET MMIO32(ATIMER_BASE + 0x004)
+
+/* Interrupt clear enable register */
+#define ATIMER_CLR_EN MMIO32(ATIMER_BASE + 0xFD8)
+
+/* Interrupt set enable register */
+#define ATIMER_SET_EN MMIO32(ATIMER_BASE + 0xFDC)
+
+/* Status register */
+#define ATIMER_STATUS MMIO32(ATIMER_BASE + 0xFE0)
+
+/* Enable register */
+#define ATIMER_ENABLE MMIO32(ATIMER_BASE + 0xFE4)
+
+/* Clear register */
+#define ATIMER_CLR_STAT MMIO32(ATIMER_BASE + 0xFE8)
+
+/* Set register */
+#define ATIMER_SET_STAT MMIO32(ATIMER_BASE + 0xFEC)
+
+/**@}*/
+
+#endif
diff --git a/libopencm3/include/libopencm3/lpc43xx/ccu.h b/libopencm3/include/libopencm3/lpc43xx/ccu.h
new file mode 100644
index 0000000..d3b1d50
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc43xx/ccu.h
@@ -0,0 +1,402 @@
+/** @defgroup ccu_defines Clock Control Unit Defines
+
+@brief Defined Constants and Types for the LPC43xx Clock Control Unit
+
+@ingroup LPC43xx_defines
+
+@version 1.0.0
+
+@author @htmlonly © @endhtmlonly 2012 Michael Ossmann
+
+@date 10 March 2013
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Michael Ossmann
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LPC43XX_CCU_H
+#define LPC43XX_CCU_H
+
+/**@{*/
+
+#include
+#include
+
+/* --- CCU1 registers ------------------------------------------------------ */
+
+/* CCU1 power mode register */
+#define CCU1_PM MMIO32(CCU1_BASE + 0x000)
+
+/* CCU1 base clock status register */
+#define CCU1_BASE_STAT MMIO32(CCU1_BASE + 0x004)
+
+/* CLK_APB3_BUS clock configuration register */
+#define CCU1_CLK_APB3_BUS_CFG MMIO32(CCU1_BASE + 0x100)
+
+/* CLK_APB3_BUS clock status register */
+#define CCU1_CLK_APB3_BUS_STAT MMIO32(CCU1_BASE + 0x104)
+
+/* CLK_APB3_I2C1 configuration register */
+#define CCU1_CLK_APB3_I2C1_CFG MMIO32(CCU1_BASE + 0x108)
+
+/* CLK_APB3_I2C1 status register */
+#define CCU1_CLK_APB3_I2C1_STAT MMIO32(CCU1_BASE + 0x10C)
+
+/* CLK_APB3_DAC configuration register */
+#define CCU1_CLK_APB3_DAC_CFG MMIO32(CCU1_BASE + 0x110)
+
+/* CLK_APB3_DAC status register */
+#define CCU1_CLK_APB3_DAC_STAT MMIO32(CCU1_BASE + 0x114)
+
+/* CLK_APB3_ADC0 configuration register */
+#define CCU1_CLK_APB3_ADC0_CFG MMIO32(CCU1_BASE + 0x118)
+
+/* CLK_APB3_ADC0 status register */
+#define CCU1_CLK_APB3_ADC0_STAT MMIO32(CCU1_BASE + 0x11C)
+
+/* CLK_APB3_ADC1 configuration register */
+#define CCU1_CLK_APB3_ADC1_CFG MMIO32(CCU1_BASE + 0x120)
+
+/* CLK_APB3_ADC1 status register */
+#define CCU1_CLK_APB3_ADC1_STAT MMIO32(CCU1_BASE + 0x124)
+
+/* CLK_APB3_CAN0 configuration register */
+#define CCU1_CLK_APB3_CAN0_CFG MMIO32(CCU1_BASE + 0x128)
+
+/* CLK_APB3_CAN0 status register */
+#define CCU1_CLK_APB3_CAN0_STAT MMIO32(CCU1_BASE + 0x12C)
+
+/* CLK_APB1_BUS configuration register */
+#define CCU1_CLK_APB1_BUS_CFG MMIO32(CCU1_BASE + 0x200)
+
+/* CLK_APB1_BUS status register */
+#define CCU1_CLK_APB1_BUS_STAT MMIO32(CCU1_BASE + 0x204)
+
+/* CLK_APB1_MOTOCON configuration register */
+#define CCU1_CLK_APB1_MOTOCONPWM_CFG MMIO32(CCU1_BASE + 0x208)
+
+/* CLK_APB1_MOTOCON status register */
+#define CCU1_CLK_APB1_MOTOCONPWM_STAT MMIO32(CCU1_BASE + 0x20C)
+
+/* CLK_APB1_I2C0 configuration register */
+#define CCU1_CLK_APB1_I2C0_CFG MMIO32(CCU1_BASE + 0x210)
+
+/* CLK_APB1_I2C0 status register */
+#define CCU1_CLK_APB1_I2C0_STAT MMIO32(CCU1_BASE + 0x214)
+
+/* CLK_APB1_I2S configuration register */
+#define CCU1_CLK_APB1_I2S_CFG MMIO32(CCU1_BASE + 0x218)
+
+/* CLK_APB1_I2S status register */
+#define CCU1_CLK_APB1_I2S_STAT MMIO32(CCU1_BASE + 0x21C)
+
+/* CLK_APB3_CAN1 configuration register */
+#define CCU1_CLK_APB1_CAN1_CFG MMIO32(CCU1_BASE + 0x220)
+
+/* CLK_APB3_CAN1 status register */
+#define CCU1_CLK_APB1_CAN1_STAT MMIO32(CCU1_BASE + 0x224)
+
+/* CLK_SPIFI configuration register */
+#define CCU1_CLK_SPIFI_CFG MMIO32(CCU1_BASE + 0x300)
+
+/* CLK_SPIFI status register */
+#define CCU1_CLK_SPIFI_STAT MMIO32(CCU1_BASE + 0x304)
+
+/* CLK_M4_BUS configuration register */
+#define CCU1_CLK_M4_BUS_CFG MMIO32(CCU1_BASE + 0x400)
+
+/* CLK_M4_BUS status register */
+#define CCU1_CLK_M4_BUS_STAT MMIO32(CCU1_BASE + 0x404)
+
+/* CLK_M4_SPIFI configuration register */
+#define CCU1_CLK_M4_SPIFI_CFG MMIO32(CCU1_BASE + 0x408)
+
+/* CLK_M4_SPIFI status register */
+#define CCU1_CLK_M4_SPIFI_STAT MMIO32(CCU1_BASE + 0x40C)
+
+/* CLK_M4_GPIO configuration register */
+#define CCU1_CLK_M4_GPIO_CFG MMIO32(CCU1_BASE + 0x410)
+
+/* CLK_M4_GPIO status register */
+#define CCU1_CLK_M4_GPIO_STAT MMIO32(CCU1_BASE + 0x414)
+
+/* CLK_M4_LCD configuration register */
+#define CCU1_CLK_M4_LCD_CFG MMIO32(CCU1_BASE + 0x418)
+
+/* CLK_M4_LCD status register */
+#define CCU1_CLK_M4_LCD_STAT MMIO32(CCU1_BASE + 0x41C)
+
+/* CLK_M4_ETHERNET configuration register */
+#define CCU1_CLK_M4_ETHERNET_CFG MMIO32(CCU1_BASE + 0x420)
+
+/* CLK_M4_ETHERNET status register */
+#define CCU1_CLK_M4_ETHERNET_STAT MMIO32(CCU1_BASE + 0x424)
+
+/* CLK_M4_USB0 configuration register */
+#define CCU1_CLK_M4_USB0_CFG MMIO32(CCU1_BASE + 0x428)
+
+/* CLK_M4_USB0 status register */
+#define CCU1_CLK_M4_USB0_STAT MMIO32(CCU1_BASE + 0x42C)
+
+/* CLK_M4_EMC configuration register */
+#define CCU1_CLK_M4_EMC_CFG MMIO32(CCU1_BASE + 0x430)
+
+/* CLK_M4_EMC status register */
+#define CCU1_CLK_M4_EMC_STAT MMIO32(CCU1_BASE + 0x434)
+
+/* CLK_M4_SDIO configuration register */
+#define CCU1_CLK_M4_SDIO_CFG MMIO32(CCU1_BASE + 0x438)
+
+/* CLK_M4_SDIO status register */
+#define CCU1_CLK_M4_SDIO_STAT MMIO32(CCU1_BASE + 0x43C)
+
+/* CLK_M4_DMA configuration register */
+#define CCU1_CLK_M4_DMA_CFG MMIO32(CCU1_BASE + 0x440)
+
+/* CLK_M4_DMA status register */
+#define CCU1_CLK_M4_DMA_STAT MMIO32(CCU1_BASE + 0x444)
+
+/* CLK_M4_M4CORE configuration register */
+#define CCU1_CLK_M4_M4CORE_CFG MMIO32(CCU1_BASE + 0x448)
+
+/* CLK_M4_M4CORE status register */
+#define CCU1_CLK_M4_M4CORE_STAT MMIO32(CCU1_BASE + 0x44C)
+
+/* CLK_M4_SCT configuration register */
+#define CCU1_CLK_M4_SCT_CFG MMIO32(CCU1_BASE + 0x468)
+
+/* CLK_M4_SCT status register */
+#define CCU1_CLK_M4_SCT_STAT MMIO32(CCU1_BASE + 0x46C)
+
+/* CLK_M4_USB1 configuration register */
+#define CCU1_CLK_M4_USB1_CFG MMIO32(CCU1_BASE + 0x470)
+
+/* CLK_M4_USB1 status register */
+#define CCU1_CLK_M4_USB1_STAT MMIO32(CCU1_BASE + 0x474)
+
+/* CLK_M4_EMCDIV configuration register */
+#define CCU1_CLK_M4_EMCDIV_CFG MMIO32(CCU1_BASE + 0x478)
+
+/* CLK_M4_EMCDIV status register */
+#define CCU1_CLK_M4_EMCDIV_STAT MMIO32(CCU1_BASE + 0x47C)
+
+/* CLK_M4_M0_CFG configuration register */
+#define CCU1_CLK_M4_M0APP_CFG MMIO32(CCU1_BASE + 0x490)
+
+/* CLK_M4_M0_STAT status register */
+#define CCU1_CLK_M4_M0APP_STAT MMIO32(CCU1_BASE + 0x494)
+
+/* CLK_M4_VADC_CFG configuration register */
+#define CCU1_CLK_M4_VADC_CFG MMIO32(CCU1_BASE + 0x498)
+
+/* CLK_M4_VADC_STAT configuration register */
+#define CCU1_CLK_M4_VADC_STAT MMIO32(CCU1_BASE + 0x49C)
+
+/* CLK_M4_WWDT configuration register */
+#define CCU1_CLK_M4_WWDT_CFG MMIO32(CCU1_BASE + 0x500)
+
+/* CLK_M4_WWDT status register */
+#define CCU1_CLK_M4_WWDT_STAT MMIO32(CCU1_BASE + 0x504)
+
+/* CLK_M4_UART0 configuration register */
+#define CCU1_CLK_M4_USART0_CFG MMIO32(CCU1_BASE + 0x508)
+
+/* CLK_M4_UART0 status register */
+#define CCU1_CLK_M4_USART0_STAT MMIO32(CCU1_BASE + 0x50C)
+
+/* CLK_M4_UART1 configuration register */
+#define CCU1_CLK_M4_UART1_CFG MMIO32(CCU1_BASE + 0x510)
+
+/* CLK_M4_UART1 status register */
+#define CCU1_CLK_M4_UART1_STAT MMIO32(CCU1_BASE + 0x514)
+
+/* CLK_M4_SSP0 configuration register */
+#define CCU1_CLK_M4_SSP0_CFG MMIO32(CCU1_BASE + 0x518)
+
+/* CLK_M4_SSP0 status register */
+#define CCU1_CLK_M4_SSP0_STAT MMIO32(CCU1_BASE + 0x51C)
+
+/* CLK_M4_TIMER0 configuration register */
+#define CCU1_CLK_M4_TIMER0_CFG MMIO32(CCU1_BASE + 0x520)
+
+/* CLK_M4_TIMER0 status register */
+#define CCU1_CLK_M4_TIMER0_STAT MMIO32(CCU1_BASE + 0x524)
+
+/* CLK_M4_TIMER1 configuration register */
+#define CCU1_CLK_M4_TIMER1_CFG MMIO32(CCU1_BASE + 0x528)
+
+/* CLK_M4_TIMER1 status register */
+#define CCU1_CLK_M4_TIMER1_STAT MMIO32(CCU1_BASE + 0x52C)
+
+/* CLK_M4_SCU configuration register */
+#define CCU1_CLK_M4_SCU_CFG MMIO32(CCU1_BASE + 0x530)
+
+/* CLK_M4_SCU status register */
+#define CCU1_CLK_M4_SCU_STAT MMIO32(CCU1_BASE + 0x534)
+
+/* CLK_M4_CREG configuration register */
+#define CCU1_CLK_M4_CREG_CFG MMIO32(CCU1_BASE + 0x538)
+
+/* CLK_M4_CREG status register */
+#define CCU1_CLK_M4_CREG_STAT MMIO32(CCU1_BASE + 0x53C)
+
+/* CLK_M4_RITIMER configuration register */
+#define CCU1_CLK_M4_RITIMER_CFG MMIO32(CCU1_BASE + 0x600)
+
+/* CLK_M4_RITIMER status register */
+#define CCU1_CLK_M4_RITIMER_STAT MMIO32(CCU1_BASE + 0x604)
+
+/* CLK_M4_UART2 configuration register */
+#define CCU1_CLK_M4_USART2_CFG MMIO32(CCU1_BASE + 0x608)
+
+/* CLK_M4_UART2 status register */
+#define CCU1_CLK_M4_USART2_STAT MMIO32(CCU1_BASE + 0x60C)
+
+/* CLK_M4_UART3 configuration register */
+#define CCU1_CLK_M4_USART3_CFG MMIO32(CCU1_BASE + 0x610)
+
+/* CLK_M4_UART3 status register */
+#define CCU1_CLK_M4_USART3_STAT MMIO32(CCU1_BASE + 0x614)
+
+/* CLK_M4_TIMER2 configuration register */
+#define CCU1_CLK_M4_TIMER2_CFG MMIO32(CCU1_BASE + 0x618)
+
+/* CLK_M4_TIMER2 status register */
+#define CCU1_CLK_M4_TIMER2_STAT MMIO32(CCU1_BASE + 0x61C)
+
+/* CLK_M4_TIMER3 configuration register */
+#define CCU1_CLK_M4_TIMER3_CFG MMIO32(CCU1_BASE + 0x620)
+
+/* CLK_M4_TIMER3 status register */
+#define CCU1_CLK_M4_TIMER3_STAT MMIO32(CCU1_BASE + 0x624)
+
+/* CLK_M4_SSP1 configuration register */
+#define CCU1_CLK_M4_SSP1_CFG MMIO32(CCU1_BASE + 0x628)
+
+/* CLK_M4_SSP1 status register */
+#define CCU1_CLK_M4_SSP1_STAT MMIO32(CCU1_BASE + 0x62C)
+
+/* CLK_M4_QEI configuration register */
+#define CCU1_CLK_M4_QEI_CFG MMIO32(CCU1_BASE + 0x630)
+
+/* CLK_M4_QEI status register */
+#define CCU1_CLK_M4_QEI_STAT MMIO32(CCU1_BASE + 0x634)
+
+/* CLK_PERIPH_BUS configuration register */
+#define CCU1_CLK_PERIPH_BUS_CFG MMIO32(CCU1_BASE + 0x700)
+
+/* CLK_PERIPH_BUS status register */
+#define CCU1_CLK_PERIPH_BUS_STAT MMIO32(CCU1_BASE + 0x704)
+
+/* CLK_PERIPH_CORE configuration register */
+#define CCU1_CLK_PERIPH_CORE_CFG MMIO32(CCU1_BASE + 0x710)
+
+/* CLK_PERIPH_CORE status register */
+#define CCU1_CLK_PERIPH_CORE_STAT MMIO32(CCU1_BASE + 0x714)
+
+/* CLK_PERIPH_SGPIO configuration register */
+#define CCU1_CLK_PERIPH_SGPIO_CFG MMIO32(CCU1_BASE + 0x718)
+
+/* CLK_PERIPH_SGPIO status register */
+#define CCU1_CLK_PERIPH_SGPIO_STAT MMIO32(CCU1_BASE + 0x71C)
+
+/* CLK_USB0 configuration register */
+#define CCU1_CLK_USB0_CFG MMIO32(CCU1_BASE + 0x800)
+
+/* CLK_USB0 status register */
+#define CCU1_CLK_USB0_STAT MMIO32(CCU1_BASE + 0x804)
+
+/* CLK_USB1 configuration register */
+#define CCU1_CLK_USB1_CFG MMIO32(CCU1_BASE + 0x900)
+
+/* CLK_USB1 status register */
+#define CCU1_CLK_USB1_STAT MMIO32(CCU1_BASE + 0x904)
+
+/* CLK_SPI configuration register */
+#define CCU1_CLK_SPI_CFG MMIO32(CCU1_BASE + 0xA00)
+
+/* CLK_SPI status register */
+#define CCU1_CLK_SPI_STAT MMIO32(CCU1_BASE + 0xA04)
+
+/* CLK_VADC configuration register */
+#define CCU1_CLK_VADC_CFG MMIO32(CCU1_BASE + 0xB00)
+
+/* CLK_VADC status register */
+#define CCU1_CLK_VADC_STAT MMIO32(CCU1_BASE + 0xB04)
+
+/* --- CCU2 registers ------------------------------------------------------ */
+
+/* CCU2 power mode register */
+#define CCU2_PM MMIO32(CCU2_BASE + 0x000)
+
+/* CCU2 base clocks status register */
+#define CCU2_BASE_STAT MMIO32(CCU2_BASE + 0x004)
+
+/* CLK_APLL configuration register */
+#define CCU2_CLK_APLL_CFG MMIO32(CCU2_BASE + 0x100)
+
+/* CLK_APLL status register */
+#define CCU2_CLK_APLL_STAT MMIO32(CCU2_BASE + 0x104)
+
+/* CLK_APB2_UART3 configuration register */
+#define CCU2_CLK_APB2_USART3_CFG MMIO32(CCU2_BASE + 0x200)
+
+/* CLK_APB2_UART3 status register */
+#define CCU2_CLK_APB2_USART3_STAT MMIO32(CCU2_BASE + 0x204)
+
+/* CLK_APB2_UART2 configuration register */
+#define CCU2_CLK_APB2_USART2_CFG MMIO32(CCU2_BASE + 0x300)
+
+/* CLK_APB2_UART2 status register */
+#define CCU2_CLK_APB2_USART2_STAT MMIO32(CCU2_BASE + 0x304)
+
+/* CLK_APB0_UART1 configuration register */
+#define CCU2_CLK_APB0_UART1_CFG MMIO32(CCU2_BASE + 0x400)
+
+/* CLK_APB0_UART1 status register */
+#define CCU2_CLK_APB0_UART1_STAT MMIO32(CCU2_BASE + 0x404)
+
+/* CLK_APB0_UART0 configuration register */
+#define CCU2_CLK_APB0_USART0_CFG MMIO32(CCU2_BASE + 0x500)
+
+/* CLK_APB0_UART0 status register */
+#define CCU2_CLK_APB0_USART0_STAT MMIO32(CCU2_BASE + 0x504)
+
+/* CLK_APB2_SSP1 configuration register */
+#define CCU2_CLK_APB2_SSP1_CFG MMIO32(CCU2_BASE + 0x600)
+
+/* CLK_APB2_SSP1 status register */
+#define CCU2_CLK_APB2_SSP1_STAT MMIO32(CCU2_BASE + 0x604)
+
+/* CLK_APB0_SSP0 configuration register */
+#define CCU2_CLK_APB0_SSP0_CFG MMIO32(CCU2_BASE + 0x700)
+
+/* CLK_APB0_SSP0 status register */
+#define CCU2_CLK_APB0_SSP0_STAT MMIO32(CCU2_BASE + 0x704)
+
+/* CLK_SDIO configuration register (for SD/MMC) */
+#define CCU2_CLK_SDIO_CFG MMIO32(CCU2_BASE + 0x800)
+
+/* CLK_SDIO status register (for SD/MMC) */
+#define CCU2_CLK_SDIO_STAT MMIO32(CCU2_BASE + 0x804)
+
+/**@}*/
+
+#endif
diff --git a/libopencm3/include/libopencm3/lpc43xx/cgu.h b/libopencm3/include/libopencm3/lpc43xx/cgu.h
new file mode 100644
index 0000000..0a169fd
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc43xx/cgu.h
@@ -0,0 +1,964 @@
+/** @defgroup cgu_defines Clock Generation Unit Defines
+ *
+ * @brief Defined Constants and Types for the LPC43xx Clock Generation
+ * Unit
+ *
+ * @ingroup LPC43xx_defines
+ *
+ * @version 1.0.0
+ *
+ * @author @htmlonly © @endhtmlonly 2012 Michael Ossmann
+ *
+ *
+ * @date 10 March 2013
+ *
+ * LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Michael Ossmann
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LPC43XX_CGU_H
+#define CGU_LPC43XX_CGU_H
+
+/**@{*/
+
+#include
+#include
+
+/* --- CGU registers ------------------------------------------------------- */
+
+/* Frequency monitor register */
+#define CGU_FREQ_MON MMIO32(CGU_BASE + 0x014)
+
+/* Crystal oscillator control register */
+#define CGU_XTAL_OSC_CTRL MMIO32(CGU_BASE + 0x018)
+
+/* PLL0USB status register */
+#define CGU_PLL0USB_STAT MMIO32(CGU_BASE + 0x01C)
+
+/* PLL0USB control register */
+#define CGU_PLL0USB_CTRL MMIO32(CGU_BASE + 0x020)
+
+/* PLL0USB M-divider register */
+#define CGU_PLL0USB_MDIV MMIO32(CGU_BASE + 0x024)
+
+/* PLL0USB N/P-divider register */
+#define CGU_PLL0USB_NP_DIV MMIO32(CGU_BASE + 0x028)
+
+/* PLL0AUDIO status register */
+#define CGU_PLL0AUDIO_STAT MMIO32(CGU_BASE + 0x02C)
+
+/* PLL0AUDIO control register */
+#define CGU_PLL0AUDIO_CTRL MMIO32(CGU_BASE + 0x030)
+
+/* PLL0AUDIO M-divider register */
+#define CGU_PLL0AUDIO_MDIV MMIO32(CGU_BASE + 0x034)
+
+/* PLL0AUDIO N/P-divider register */
+#define CGU_PLL0AUDIO_NP_DIV MMIO32(CGU_BASE + 0x038)
+
+/* PLL0AUDIO fractional divider register */
+#define CGU_PLLAUDIO_FRAC MMIO32(CGU_BASE + 0x03C)
+
+/* PLL1 status register */
+#define CGU_PLL1_STAT MMIO32(CGU_BASE + 0x040)
+
+/* PLL1 control register */
+#define CGU_PLL1_CTRL MMIO32(CGU_BASE + 0x044)
+
+/* Integer divider A control register */
+#define CGU_IDIVA_CTRL MMIO32(CGU_BASE + 0x048)
+
+/* Integer divider B control register */
+#define CGU_IDIVB_CTRL MMIO32(CGU_BASE + 0x04C)
+
+/* Integer divider C control register */
+#define CGU_IDIVC_CTRL MMIO32(CGU_BASE + 0x050)
+
+/* Integer divider D control register */
+#define CGU_IDIVD_CTRL MMIO32(CGU_BASE + 0x054)
+
+/* Integer divider E control register */
+#define CGU_IDIVE_CTRL MMIO32(CGU_BASE + 0x058)
+
+/* Output stage 0 control register */
+#define CGU_BASE_SAFE_CLK MMIO32(CGU_BASE + 0x05C)
+
+/* Output stage 1 control register for base clock */
+#define CGU_BASE_USB0_CLK MMIO32(CGU_BASE + 0x060)
+
+/* Output stage 2 control register for base clock */
+#define CGU_BASE_PERIPH_CLK MMIO32(CGU_BASE + 0x064)
+
+/* Output stage 3 control register for base clock */
+#define CGU_BASE_USB1_CLK MMIO32(CGU_BASE + 0x068)
+
+/* Output stage 4 control register for base clock */
+#define CGU_BASE_M4_CLK MMIO32(CGU_BASE + 0x06C)
+
+/* Output stage 5 control register for base clock */
+#define CGU_BASE_SPIFI_CLK MMIO32(CGU_BASE + 0x070)
+
+/* Output stage 6 control register for base clock */
+#define CGU_BASE_SPI_CLK MMIO32(CGU_BASE + 0x074)
+
+/* Output stage 7 control register for base clock */
+#define CGU_BASE_PHY_RX_CLK MMIO32(CGU_BASE + 0x078)
+
+/* Output stage 8 control register for base clock */
+#define CGU_BASE_PHY_TX_CLK MMIO32(CGU_BASE + 0x07C)
+
+/* Output stage 9 control register for base clock */
+#define CGU_BASE_APB1_CLK MMIO32(CGU_BASE + 0x080)
+
+/* Output stage 10 control register for base clock */
+#define CGU_BASE_APB3_CLK MMIO32(CGU_BASE + 0x084)
+
+/* Output stage 11 control register for base clock */
+#define CGU_BASE_LCD_CLK MMIO32(CGU_BASE + 0x088)
+
+/* Output stage 12 control register for base clock */
+#define CGU_BASE_VADC_CLK MMIO32(CGU_BASE + 0x08C)
+
+/* Output stage 13 control register for base clock */
+#define CGU_BASE_SDIO_CLK MMIO32(CGU_BASE + 0x090)
+
+/* Output stage 14 control register for base clock */
+#define CGU_BASE_SSP0_CLK MMIO32(CGU_BASE + 0x094)
+
+/* Output stage 15 control register for base clock */
+#define CGU_BASE_SSP1_CLK MMIO32(CGU_BASE + 0x098)
+
+/* Output stage 16 control register for base clock */
+#define CGU_BASE_UART0_CLK MMIO32(CGU_BASE + 0x09C)
+
+/* Output stage 17 control register for base clock */
+#define CGU_BASE_UART1_CLK MMIO32(CGU_BASE + 0x0A0)
+
+/* Output stage 18 control register for base clock */
+#define CGU_BASE_UART2_CLK MMIO32(CGU_BASE + 0x0A4)
+
+/* Output stage 19 control register for base clock */
+#define CGU_BASE_UART3_CLK MMIO32(CGU_BASE + 0x0A8)
+
+/* Output stage 20 control register for base clock */
+#define CGU_BASE_OUT_CLK MMIO32(CGU_BASE + 0x0AC)
+
+/* Reserved output stage */
+#define CGU_OUTCLK_21_CTRL MMIO32(CGU_BASE + 0x0B0)
+
+/* Reserved output stage */
+#define CGU_OUTCLK_22_CTRL MMIO32(CGU_BASE + 0x0B4)
+
+/* Reserved output stage */
+#define CGU_OUTCLK_23_CTRL MMIO32(CGU_BASE + 0x0B8)
+
+/* Reserved output stage */
+#define CGU_OUTCLK_24_CTRL MMIO32(CGU_BASE + 0x0BC)
+
+/* Output stage 25 control register for base clock */
+#define CGU_BASE_APLL_CLK MMIO32(CGU_BASE + 0x0C0)
+
+/* Output stage 26 control CLK register for base clock */
+#define CGU_BASE_CGU_OUT0_CLK MMIO32(CGU_BASE + 0x0C4)
+
+/* Output stage 27 control CLK register for base clock */
+#define CGU_BASE_CGU_OUT1_CLK MMIO32(CGU_BASE + 0x0C8)
+
+/* --- CGU_FREQ_MON values -------------------------------------- */
+
+/* RCNT: 9-bit reference clock-counter value */
+#define CGU_FREQ_MON_RCNT_SHIFT (0)
+#define CGU_FREQ_MON_RCNT_MASK (0x1ff << CGU_FREQ_MON_RCNT_SHIFT)
+#define CGU_FREQ_MON_RCNT(x) ((x) << CGU_FREQ_MON_RCNT_SHIFT)
+
+/* FCNT: 14-bit selected clock-counter value */
+#define CGU_FREQ_MON_FCNT_SHIFT (9)
+#define CGU_FREQ_MON_FCNT_MASK (0x3fff << CGU_FREQ_MON_FCNT_SHIFT)
+#define CGU_FREQ_MON_FCNT(x) ((x) << CGU_FREQ_MON_FCNT_SHIFT)
+
+/* MEAS: Measure frequency */
+#define CGU_FREQ_MON_MEAS_SHIFT (23)
+#define CGU_FREQ_MON_MEAS (1 << CGU_FREQ_MON_MEAS_SHIFT)
+
+/* CLK_SEL: Clock-source selection for the clock to be measured */
+#define CGU_FREQ_MON_CLK_SEL_SHIFT (24)
+#define CGU_FREQ_MON_CLK_SEL_MASK (0x1f << CGU_FREQ_MON_CLK_SEL_SHIFT)
+#define CGU_FREQ_MON_CLK_SEL(x) ((x) << CGU_FREQ_MON_CLK_SEL_SHIFT)
+
+/* --- CGU_XTAL_OSC_CTRL values --------------------------------- */
+
+/* ENABLE: Oscillator-pad enable */
+#define CGU_XTAL_OSC_CTRL_ENABLE_SHIFT (0)
+#define CGU_XTAL_OSC_CTRL_ENABLE (1 << CGU_XTAL_OSC_CTRL_ENABLE_SHIFT)
+
+/* BYPASS: Configure crystal operation or external-clock input pin XTAL1 */
+#define CGU_XTAL_OSC_CTRL_BYPASS_SHIFT (1)
+#define CGU_XTAL_OSC_CTRL_BYPASS (1 << CGU_XTAL_OSC_CTRL_BYPASS_SHIFT)
+
+/* HF: Select frequency range */
+#define CGU_XTAL_OSC_CTRL_HF_SHIFT (2)
+#define CGU_XTAL_OSC_CTRL_HF (1 << CGU_XTAL_OSC_CTRL_HF_SHIFT)
+
+/* --- CGU_PLL0USB_STAT values ---------------------------------- */
+
+/* LOCK: PLL0 lock indicator */
+#define CGU_PLL0USB_STAT_LOCK_SHIFT (0)
+#define CGU_PLL0USB_STAT_LOCK (1 << CGU_PLL0USB_STAT_LOCK_SHIFT)
+
+/* FR: PLL0 free running indicator */
+#define CGU_PLL0USB_STAT_FR_SHIFT (1)
+#define CGU_PLL0USB_STAT_FR (1 << CGU_PLL0USB_STAT_FR_SHIFT)
+
+/* --- CGU_PLL0USB_CTRL values ---------------------------------- */
+
+/* PD: PLL0 power down */
+#define CGU_PLL0USB_CTRL_PD_SHIFT (0)
+#define CGU_PLL0USB_CTRL_PD (1 << CGU_PLL0USB_CTRL_PD_SHIFT)
+
+/* BYPASS: Input clock bypass control */
+#define CGU_PLL0USB_CTRL_BYPASS_SHIFT (1)
+#define CGU_PLL0USB_CTRL_BYPASS (1 << CGU_PLL0USB_CTRL_BYPASS_SHIFT)
+
+/* DIRECTI: PLL0 direct input */
+#define CGU_PLL0USB_CTRL_DIRECTI_SHIFT (2)
+#define CGU_PLL0USB_CTRL_DIRECTI (1 << CGU_PLL0USB_CTRL_DIRECTI_SHIFT)
+
+/* DIRECTO: PLL0 direct output */
+#define CGU_PLL0USB_CTRL_DIRECTO_SHIFT (3)
+#define CGU_PLL0USB_CTRL_DIRECTO (1 << CGU_PLL0USB_CTRL_DIRECTO_SHIFT)
+
+/* CLKEN: PLL0 clock enable */
+#define CGU_PLL0USB_CTRL_CLKEN_SHIFT (4)
+#define CGU_PLL0USB_CTRL_CLKEN (1 << CGU_PLL0USB_CTRL_CLKEN_SHIFT)
+
+/* FRM: Free running mode */
+#define CGU_PLL0USB_CTRL_FRM_SHIFT (6)
+#define CGU_PLL0USB_CTRL_FRM (1 << CGU_PLL0USB_CTRL_FRM_SHIFT)
+
+/* AUTOBLOCK: Block clock automatically during frequency change */
+#define CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT (11)
+#define CGU_PLL0USB_CTRL_AUTOBLOCK (1 << CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT)
+
+/* CLK_SEL: Clock source selection */
+#define CGU_PLL0USB_CTRL_CLK_SEL_SHIFT (24)
+#define CGU_PLL0USB_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT)
+#define CGU_PLL0USB_CTRL_CLK_SEL(x) ((x) << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT)
+
+/* --- CGU_PLL0USB_MDIV values ---------------------------------- */
+
+/* MDEC: Decoded M-divider coefficient value */
+#define CGU_PLL0USB_MDIV_MDEC_SHIFT (0)
+#define CGU_PLL0USB_MDIV_MDEC_MASK (0x1ffff << CGU_PLL0USB_MDIV_MDEC_SHIFT)
+#define CGU_PLL0USB_MDIV_MDEC(x) ((x) << CGU_PLL0USB_MDIV_MDEC_SHIFT)
+
+/* SELP: Bandwidth select P value */
+#define CGU_PLL0USB_MDIV_SELP_SHIFT (17)
+#define CGU_PLL0USB_MDIV_SELP_MASK (0x1f << CGU_PLL0USB_MDIV_SELP_SHIFT)
+#define CGU_PLL0USB_MDIV_SELP(x) ((x) << CGU_PLL0USB_MDIV_SELP_SHIFT)
+
+/* SELI: Bandwidth select I value */
+#define CGU_PLL0USB_MDIV_SELI_SHIFT (22)
+#define CGU_PLL0USB_MDIV_SELI_MASK (0x3f << CGU_PLL0USB_MDIV_SELI_SHIFT)
+#define CGU_PLL0USB_MDIV_SELI(x) ((x) << CGU_PLL0USB_MDIV_SELI_SHIFT)
+
+/* SELR: Bandwidth select R value */
+#define CGU_PLL0USB_MDIV_SELR_SHIFT (28)
+#define CGU_PLL0USB_MDIV_SELR_MASK (0xf << CGU_PLL0USB_MDIV_SELR_SHIFT)
+#define CGU_PLL0USB_MDIV_SELR(x) ((x) << CGU_PLL0USB_MDIV_SELR_SHIFT)
+
+/* --- CGU_PLL0USB_NP_DIV values -------------------------------- */
+
+/* PDEC: Decoded P-divider coefficient value */
+#define CGU_PLL0USB_NP_DIV_PDEC_SHIFT (0)
+#define CGU_PLL0USB_NP_DIV_PDEC_MASK (0x7f << CGU_PLL0USB_NP_DIV_PDEC_SHIFT)
+#define CGU_PLL0USB_NP_DIV_PDEC(x) ((x) << CGU_PLL0USB_NP_DIV_PDEC_SHIFT)
+
+/* NDEC: Decoded N-divider coefficient value */
+#define CGU_PLL0USB_NP_DIV_NDEC_SHIFT (12)
+#define CGU_PLL0USB_NP_DIV_NDEC_MASK (0x3ff << CGU_PLL0USB_NP_DIV_NDEC_SHIFT)
+#define CGU_PLL0USB_NP_DIV_NDEC(x) ((x) << CGU_PLL0USB_NP_DIV_NDEC_SHIFT)
+
+/* --- CGU_PLL0AUDIO_STAT values -------------------------------- */
+
+/* LOCK: PLL0 lock indicator */
+#define CGU_PLL0AUDIO_STAT_LOCK_SHIFT (0)
+#define CGU_PLL0AUDIO_STAT_LOCK (1 << CGU_PLL0AUDIO_STAT_LOCK_SHIFT)
+
+/* FR: PLL0 free running indicator */
+#define CGU_PLL0AUDIO_STAT_FR_SHIFT (1)
+#define CGU_PLL0AUDIO_STAT_FR (1 << CGU_PLL0AUDIO_STAT_FR_SHIFT)
+
+/* --- CGU_PLL0AUDIO_CTRL values -------------------------------- */
+
+/* PD: PLL0 power down */
+#define CGU_PLL0AUDIO_CTRL_PD_SHIFT (0)
+#define CGU_PLL0AUDIO_CTRL_PD (1 << CGU_PLL0AUDIO_CTRL_PD_SHIFT)
+
+/* BYPASS: Input clock bypass control */
+#define CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT (1)
+#define CGU_PLL0AUDIO_CTRL_BYPASS (1 << CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT)
+
+/* DIRECTI: PLL0 direct input */
+#define CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT (2)
+#define CGU_PLL0AUDIO_CTRL_DIRECTI (1 << CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT)
+
+/* DIRECTO: PLL0 direct output */
+#define CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT (3)
+#define CGU_PLL0AUDIO_CTRL_DIRECTO (1 << CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT)
+
+/* CLKEN: PLL0 clock enable */
+#define CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT (4)
+#define CGU_PLL0AUDIO_CTRL_CLKEN (1 << CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT)
+
+/* FRM: Free running mode */
+#define CGU_PLL0AUDIO_CTRL_FRM_SHIFT (6)
+#define CGU_PLL0AUDIO_CTRL_FRM (1 << CGU_PLL0AUDIO_CTRL_FRM_SHIFT)
+
+/* AUTOBLOCK: Block clock automatically during frequency change */
+#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT (11)
+#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK \
+ (1 << CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT)
+
+/* PLLFRACT_REQ: Fractional PLL word write request */
+#define CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT (12)
+#define CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ \
+ (1 << CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT)
+
+/* SEL_EXT: Select fractional divider */
+#define CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT (13)
+#define CGU_PLL0AUDIO_CTRL_SEL_EXT (1 << CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT)
+
+/* MOD_PD: Sigma-Delta modulator power-down */
+#define CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT (14)
+#define CGU_PLL0AUDIO_CTRL_MOD_PD (1 << CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT)
+
+/* CLK_SEL: Clock source selection */
+#define CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT (24)
+#define CGU_PLL0AUDIO_CTRL_CLK_SEL_MASK \
+ (0x1f << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT)
+#define CGU_PLL0AUDIO_CTRL_CLK_SEL(x) \
+ ((x) << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT)
+
+/* --- CGU_PLL0AUDIO_MDIV values -------------------------------- */
+
+/* MDEC: Decoded M-divider coefficient value */
+#define CGU_PLL0AUDIO_MDIV_MDEC_SHIFT (0)
+#define CGU_PLL0AUDIO_MDIV_MDEC_MASK \
+ (0x1ffff << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT)
+#define CGU_PLL0AUDIO_MDIV_MDEC(x) \
+ ((x) << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT)
+
+/* --- CGU_PLL0AUDIO_NP_DIV values ------------------------------ */
+
+/* PDEC: Decoded P-divider coefficient value */
+#define CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT (0)
+#define CGU_PLL0AUDIO_NP_DIV_PDEC_MASK \
+ (0x7f << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT)
+#define CGU_PLL0AUDIO_NP_DIV_PDEC(x) \
+ ((x) << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT)
+
+/* NDEC: Decoded N-divider coefficient value */
+#define CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT (12)
+#define CGU_PLL0AUDIO_NP_DIV_NDEC_MASK \
+ (0x3ff << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT)
+#define CGU_PLL0AUDIO_NP_DIV_NDEC(x) \
+ ((x) << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT)
+
+/* --- CGU_PLLAUDIO_FRAC values --------------------------------- */
+
+/* PLLFRACT_CTRL: PLL fractional divider control word */
+#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT (0)
+#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_MASK \
+ (0x3fffff << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT)
+#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL(x) \
+ ((x) << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT)
+
+/* --- CGU_PLL1_STAT values ------------------------------------- */
+
+/* LOCK: PLL1 lock indicator */
+#define CGU_PLL1_STAT_LOCK_SHIFT (0)
+#define CGU_PLL1_STAT_LOCK (1 << CGU_PLL1_STAT_LOCK_SHIFT)
+
+/* --- CGU_PLL1_CTRL values ------------------------------------- */
+
+/* PD: PLL1 power down */
+#define CGU_PLL1_CTRL_PD_SHIFT (0)
+#define CGU_PLL1_CTRL_PD (1 << CGU_PLL1_CTRL_PD_SHIFT)
+
+/* BYPASS: Input clock bypass control */
+#define CGU_PLL1_CTRL_BYPASS_SHIFT (1)
+#define CGU_PLL1_CTRL_BYPASS (1 << CGU_PLL1_CTRL_BYPASS_SHIFT)
+
+/* FBSEL: PLL feedback select */
+#define CGU_PLL1_CTRL_FBSEL_SHIFT (6)
+#define CGU_PLL1_CTRL_FBSEL (1 << CGU_PLL1_CTRL_FBSEL_SHIFT)
+
+/* DIRECT: PLL direct CCO output */
+#define CGU_PLL1_CTRL_DIRECT_SHIFT (7)
+#define CGU_PLL1_CTRL_DIRECT (1 << CGU_PLL1_CTRL_DIRECT_SHIFT)
+
+/* PSEL: Post-divider division ratio P */
+#define CGU_PLL1_CTRL_PSEL_SHIFT (8)
+#define CGU_PLL1_CTRL_PSEL_MASK (0x3 << CGU_PLL1_CTRL_PSEL_SHIFT)
+#define CGU_PLL1_CTRL_PSEL(x) ((x) << CGU_PLL1_CTRL_PSEL_SHIFT)
+
+/* AUTOBLOCK: Block clock automatically during frequency change */
+#define CGU_PLL1_CTRL_AUTOBLOCK_SHIFT (11)
+#define CGU_PLL1_CTRL_AUTOBLOCK (1 << CGU_PLL1_CTRL_AUTOBLOCK_SHIFT)
+
+/* NSEL: Pre-divider division ratio N */
+#define CGU_PLL1_CTRL_NSEL_SHIFT (12)
+#define CGU_PLL1_CTRL_NSEL_MASK (0x3 << CGU_PLL1_CTRL_NSEL_SHIFT)
+#define CGU_PLL1_CTRL_NSEL(x) ((x) << CGU_PLL1_CTRL_NSEL_SHIFT)
+
+/* MSEL: Feedback-divider division ratio (M) */
+#define CGU_PLL1_CTRL_MSEL_SHIFT (16)
+#define CGU_PLL1_CTRL_MSEL_MASK (0xff << CGU_PLL1_CTRL_MSEL_SHIFT)
+#define CGU_PLL1_CTRL_MSEL(x) ((x) << CGU_PLL1_CTRL_MSEL_SHIFT)
+
+/* CLK_SEL: Clock-source selection */
+#define CGU_PLL1_CTRL_CLK_SEL_SHIFT (24)
+#define CGU_PLL1_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL1_CTRL_CLK_SEL_SHIFT)
+#define CGU_PLL1_CTRL_CLK_SEL(x) ((x) << CGU_PLL1_CTRL_CLK_SEL_SHIFT)
+
+/* --- CGU_IDIVA_CTRL values ------------------------------------ */
+
+/* PD: Integer divider power down */
+#define CGU_IDIVA_CTRL_PD_SHIFT (0)
+#define CGU_IDIVA_CTRL_PD (1 << CGU_IDIVA_CTRL_PD_SHIFT)
+
+/* IDIV: Integer divider A divider value (1/(IDIV + 1)) */
+#define CGU_IDIVA_CTRL_IDIV_SHIFT (2)
+#define CGU_IDIVA_CTRL_IDIV_MASK (0x3 << CGU_IDIVA_CTRL_IDIV_SHIFT)
+#define CGU_IDIVA_CTRL_IDIV(x) ((x) << CGU_IDIVA_CTRL_IDIV_SHIFT)
+
+/* AUTOBLOCK: Block clock automatically during frequency change */
+#define CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT (11)
+#define CGU_IDIVA_CTRL_AUTOBLOCK (1 << CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT)
+
+/* CLK_SEL: Clock source selection */
+#define CGU_IDIVA_CTRL_CLK_SEL_SHIFT (24)
+#define CGU_IDIVA_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVA_CTRL_CLK_SEL_SHIFT)
+#define CGU_IDIVA_CTRL_CLK_SEL(x) ((x) << CGU_IDIVA_CTRL_CLK_SEL_SHIFT)
+
+/* --- CGU_IDIVB_CTRL values ------------------------------------ */
+
+/* PD: Integer divider power down */
+#define CGU_IDIVB_CTRL_PD_SHIFT (0)
+#define CGU_IDIVB_CTRL_PD (1 << CGU_IDIVB_CTRL_PD_SHIFT)
+
+/* IDIV: Integer divider B divider value (1/(IDIV + 1)) */
+#define CGU_IDIVB_CTRL_IDIV_SHIFT (2)
+#define CGU_IDIVB_CTRL_IDIV_MASK (0xf << CGU_IDIVB_CTRL_IDIV_SHIFT)
+#define CGU_IDIVB_CTRL_IDIV(x) ((x) << CGU_IDIVB_CTRL_IDIV_SHIFT)
+
+/* AUTOBLOCK: Block clock automatically during frequency change */
+#define CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT (11)
+#define CGU_IDIVB_CTRL_AUTOBLOCK (1 << CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT)
+
+/* CLK_SEL: Clock source selection */
+#define CGU_IDIVB_CTRL_CLK_SEL_SHIFT (24)
+#define CGU_IDIVB_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVB_CTRL_CLK_SEL_SHIFT)
+#define CGU_IDIVB_CTRL_CLK_SEL(x) ((x) << CGU_IDIVB_CTRL_CLK_SEL_SHIFT)
+
+/* --- CGU_IDIVC_CTRL values ------------------------------------ */
+
+/* PD: Integer divider power down */
+#define CGU_IDIVC_CTRL_PD_SHIFT (0)
+#define CGU_IDIVC_CTRL_PD (1 << CGU_IDIVC_CTRL_PD_SHIFT)
+
+/* IDIV: Integer divider C divider value (1/(IDIV + 1)) */
+#define CGU_IDIVC_CTRL_IDIV_SHIFT (2)
+#define CGU_IDIVC_CTRL_IDIV_MASK (0xf << CGU_IDIVC_CTRL_IDIV_SHIFT)
+#define CGU_IDIVC_CTRL_IDIV(x) ((x) << CGU_IDIVC_CTRL_IDIV_SHIFT)
+
+/* AUTOBLOCK: Block clock automatically during frequency change */
+#define CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT (11)
+#define CGU_IDIVC_CTRL_AUTOBLOCK (1 << CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT)
+
+/* CLK_SEL: Clock source selection */
+#define CGU_IDIVC_CTRL_CLK_SEL_SHIFT (24)
+#define CGU_IDIVC_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVC_CTRL_CLK_SEL_SHIFT)
+#define CGU_IDIVC_CTRL_CLK_SEL(x) ((x) << CGU_IDIVC_CTRL_CLK_SEL_SHIFT)
+
+/* --- CGU_IDIVD_CTRL values ------------------------------------ */
+
+/* PD: Integer divider power down */
+#define CGU_IDIVD_CTRL_PD_SHIFT (0)
+#define CGU_IDIVD_CTRL_PD (1 << CGU_IDIVD_CTRL_PD_SHIFT)
+
+/* IDIV: Integer divider D divider value (1/(IDIV + 1)) */
+#define CGU_IDIVD_CTRL_IDIV_SHIFT (2)
+#define CGU_IDIVD_CTRL_IDIV_MASK (0xf << CGU_IDIVD_CTRL_IDIV_SHIFT)
+#define CGU_IDIVD_CTRL_IDIV(x) ((x) << CGU_IDIVD_CTRL_IDIV_SHIFT)
+
+/* AUTOBLOCK: Block clock automatically during frequency change */
+#define CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT (11)
+#define CGU_IDIVD_CTRL_AUTOBLOCK (1 << CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT)
+
+/* CLK_SEL: Clock source selection */
+#define CGU_IDIVD_CTRL_CLK_SEL_SHIFT (24)
+#define CGU_IDIVD_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVD_CTRL_CLK_SEL_SHIFT)
+#define CGU_IDIVD_CTRL_CLK_SEL(x) ((x) << CGU_IDIVD_CTRL_CLK_SEL_SHIFT)
+
+/* --- CGU_IDIVE_CTRL values ------------------------------------ */
+
+/* PD: Integer divider power down */
+#define CGU_IDIVE_CTRL_PD_SHIFT (0)
+#define CGU_IDIVE_CTRL_PD (1 << CGU_IDIVE_CTRL_PD_SHIFT)
+
+/* IDIV: Integer divider E divider value (1/(IDIV + 1)) */
+#define CGU_IDIVE_CTRL_IDIV_SHIFT (2)
+#define CGU_IDIVE_CTRL_IDIV_MASK (0xff << CGU_IDIVE_CTRL_IDIV_SHIFT)
+#define CGU_IDIVE_CTRL_IDIV(x) ((x) << CGU_IDIVE_CTRL_IDIV_SHIFT)
+
+/* AUTOBLOCK: Block clock automatically during frequency change */
+#define CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT (11)
+#define CGU_IDIVE_CTRL_AUTOBLOCK (1 << CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT)
+
+/* CLK_SEL: Clock source selection */
+#define CGU_IDIVE_CTRL_CLK_SEL_SHIFT (24)
+#define CGU_IDIVE_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVE_CTRL_CLK_SEL_SHIFT)
+#define CGU_IDIVE_CTRL_CLK_SEL(x) ((x) << CGU_IDIVE_CTRL_CLK_SEL_SHIFT)
+
+/* --- CGU_BASE_SAFE_CLK values --------------------------------- */
+
+/* PD: Output stage power down */
+#define CGU_BASE_SAFE_CLK_PD_SHIFT (0)
+#define CGU_BASE_SAFE_CLK_PD (1 << CGU_BASE_SAFE_CLK_PD_SHIFT)
+
+/* AUTOBLOCK: Block clock automatically during frequency change */
+#define CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT (11)
+#define CGU_BASE_SAFE_CLK_AUTOBLOCK (1 << CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT)
+
+/* CLK_SEL: Clock source selection */
+#define CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT (24)
+#define CGU_BASE_SAFE_CLK_CLK_SEL_MASK \
+ (0x1f << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT)
+#define CGU_BASE_SAFE_CLK_CLK_SEL(x) \
+ ((x) << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT)
+
+/* --- CGU_BASE_USB0_CLK values --------------------------------- */
+
+/* PD: Output stage power down */
+#define CGU_BASE_USB0_CLK_PD_SHIFT (0)
+#define CGU_BASE_USB0_CLK_PD (1 << CGU_BASE_USB0_CLK_PD_SHIFT)
+
+/* AUTOBLOCK: Block clock automatically during frequency change */
+#define CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT (11)
+#define CGU_BASE_USB0_CLK_AUTOBLOCK (1 << CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT)
+
+/* CLK_SEL: Clock source selection */
+#define CGU_BASE_USB0_CLK_CLK_SEL_SHIFT (24)
+#define CGU_BASE_USB0_CLK_CLK_SEL_MASK \
+ (0x1f << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT)
+#define CGU_BASE_USB0_CLK_CLK_SEL(x) \
+ ((x) << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT)
+
+/* --- CGU_BASE_PERIPH_CLK values ------------------------------- */
+
+/* PD: Output stage power down */
+#define CGU_BASE_PERIPH_CLK_PD_SHIFT (0)
+#define CGU_BASE_PERIPH_CLK_PD (1 << CGU_BASE_PERIPH_CLK_PD_SHIFT)
+
+/* AUTOBLOCK: Block clock automatically during frequency change */
+#define CGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT (11)
+#define CGU_BASE_PERIPH_CLK_AUTOBLOCK \
+ (1 << CGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT)
+
+/* CLK_SEL: Clock source selection */
+#define CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT (24)
+#define CGU_BASE_PERIPH_CLK_CLK_SEL_MASK \
+ (0x1f << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT)
+#define CGU_BASE_PERIPH_CLK_CLK_SEL(x) \
+ ((x) << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT)
+
+/* --- CGU_BASE_USB1_CLK values --------------------------------- */
+
+/* PD: Output stage power down */
+#define CGU_BASE_USB1_CLK_PD_SHIFT (0)
+#define CGU_BASE_USB1_CLK_PD (1 << CGU_BASE_USB1_CLK_PD_SHIFT)
+
+/* AUTOBLOCK: Block clock automatically during frequency change */
+#define CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT (11)
+#define CGU_BASE_USB1_CLK_AUTOBLOCK (1 << CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT)
+
+/* CLK_SEL: Clock source selection */
+#define CGU_BASE_USB1_CLK_CLK_SEL_SHIFT (24)
+#define CGU_BASE_USB1_CLK_CLK_SEL_MASK \
+ (0x1f << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT)
+#define CGU_BASE_USB1_CLK_CLK_SEL(x) \
+ ((x) << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT)
+
+/* --- CGU_BASE_M4_CLK values ----------------------------------- */
+
+/* PD: Output stage power down */
+#define CGU_BASE_M4_CLK_PD_SHIFT (0)
+#define CGU_BASE_M4_CLK_PD (1 << CGU_BASE_M4_CLK_PD_SHIFT)
+
+/* AUTOBLOCK: Block clock automatically during frequency change */
+#define CGU_BASE_M4_CLK_AUTOBLOCK_SHIFT (11)
+#define CGU_BASE_M4_CLK_AUTOBLOCK (1 << CGU_BASE_M4_CLK_AUTOBLOCK_SHIFT)
+
+/* CLK_SEL: Clock source selection */
+#define CGU_BASE_M4_CLK_CLK_SEL_SHIFT (24)
+#define CGU_BASE_M4_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_M4_CLK_CLK_SEL_SHIFT)
+#define CGU_BASE_M4_CLK_CLK_SEL(x) ((x) << CGU_BASE_M4_CLK_CLK_SEL_SHIFT)
+
+/* --- CGU_BASE_SPIFI_CLK values -------------------------------- */
+
+/* PD: Output stage power down */
+#define CGU_BASE_SPIFI_CLK_PD_SHIFT (0)
+#define CGU_BASE_SPIFI_CLK_PD (1 << CGU_BASE_SPIFI_CLK_PD_SHIFT)
+
+/* AUTOBLOCK: Block clock automatically during frequency change */
+#define CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT (11)
+#define CGU_BASE_SPIFI_CLK_AUTOBLOCK \
+ (1 << CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT)
+
+/* CLK_SEL: Clock source selection */
+#define CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT (24)
+#define CGU_BASE_SPIFI_CLK_CLK_SEL_MASK \
+ (0x1f << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT)
+#define CGU_BASE_SPIFI_CLK_CLK_SEL(x) \
+ ((x) << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT)
+
+/* --- CGU_BASE_SPI_CLK values ---------------------------------- */
+
+/* PD: Output stage power down */
+#define CGU_BASE_SPI_CLK_PD_SHIFT (0)
+#define CGU_BASE_SPI_CLK_PD (1 << CGU_BASE_SPI_CLK_PD_SHIFT)
+
+/* AUTOBLOCK: Block clock automatically during frequency change */
+#define CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT (11)
+#define CGU_BASE_SPI_CLK_AUTOBLOCK (1 << CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT)
+
+/* CLK_SEL: Clock source selection */
+#define CGU_BASE_SPI_CLK_CLK_SEL_SHIFT (24)
+#define CGU_BASE_SPI_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT)
+#define CGU_BASE_SPI_CLK_CLK_SEL(x) ((x) << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT)
+
+/* --- CGU_BASE_PHY_RX_CLK values ------------------------------- */
+
+/* PD: Output stage power down */
+#define CGU_BASE_PHY_RX_CLK_PD_SHIFT (0)
+#define CGU_BASE_PHY_RX_CLK_PD (1 << CGU_BASE_PHY_RX_CLK_PD_SHIFT)
+
+/* AUTOBLOCK: Block clock automatically during frequency change */
+#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT (11)
+#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK \
+ (1 << CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT)
+
+/* CLK_SEL: Clock source selection */
+#define CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT (24)
+#define CGU_BASE_PHY_RX_CLK_CLK_SEL_MASK \
+ (0x1f << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT)
+#define CGU_BASE_PHY_RX_CLK_CLK_SEL(x) \
+ ((x) << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT)
+
+/* --- CGU_BASE_PHY_TX_CLK values ------------------------------- */
+
+/* PD: Output stage power down */
+#define CGU_BASE_PHY_TX_CLK_PD_SHIFT (0)
+#define CGU_BASE_PHY_TX_CLK_PD (1 << CGU_BASE_PHY_TX_CLK_PD_SHIFT)
+
+/* AUTOBLOCK: Block clock automatically during frequency change */
+#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT (11)
+#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK \
+ (1 << CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT)
+
+/* CLK_SEL: Clock source selection */
+#define CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT (24)
+#define CGU_BASE_PHY_TX_CLK_CLK_SEL_MASK \
+ (0x1f << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT)
+#define CGU_BASE_PHY_TX_CLK_CLK_SEL(x) \
+ ((x) << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT)
+
+/* --- CGU_BASE_APB1_CLK values --------------------------------- */
+
+/* PD: Output stage power down */
+#define CGU_BASE_APB1_CLK_PD_SHIFT (0)
+#define CGU_BASE_APB1_CLK_PD (1 << CGU_BASE_APB1_CLK_PD_SHIFT)
+
+/* AUTOBLOCK: Block clock automatically during frequency change */
+#define CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT (11)
+#define CGU_BASE_APB1_CLK_AUTOBLOCK (1 << CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT)
+
+/* CLK_SEL: Clock source selection */
+#define CGU_BASE_APB1_CLK_CLK_SEL_SHIFT (24)
+#define CGU_BASE_APB1_CLK_CLK_SEL_MASK \
+ (0x1f << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT)
+#define CGU_BASE_APB1_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT)
+
+/* --- CGU_BASE_APB3_CLK values --------------------------------- */
+
+/* PD: Output stage power down */
+#define CGU_BASE_APB3_CLK_PD_SHIFT (0)
+#define CGU_BASE_APB3_CLK_PD (1 << CGU_BASE_APB3_CLK_PD_SHIFT)
+
+/* AUTOBLOCK: Block clock automatically during frequency change */
+#define CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT (11)
+#define CGU_BASE_APB3_CLK_AUTOBLOCK (1 << CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT)
+
+/* CLK_SEL: Clock source selection */
+#define CGU_BASE_APB3_CLK_CLK_SEL_SHIFT (24)
+#define CGU_BASE_APB3_CLK_CLK_SEL_MASK \
+ (0x1f << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT)
+#define CGU_BASE_APB3_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT)
+
+/* --- CGU_BASE_LCD_CLK values ---------------------------------- */
+
+/* PD: Output stage power down */
+#define CGU_BASE_LCD_CLK_PD_SHIFT (0)
+#define CGU_BASE_LCD_CLK_PD (1 << CGU_BASE_LCD_CLK_PD_SHIFT)
+
+/* AUTOBLOCK: Block clock automatically during frequency change */
+#define CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT (11)
+#define CGU_BASE_LCD_CLK_AUTOBLOCK (1 << CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT)
+
+/* CLK_SEL: Clock source selection */
+#define CGU_BASE_LCD_CLK_CLK_SEL_SHIFT (24)
+#define CGU_BASE_LCD_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT)
+#define CGU_BASE_LCD_CLK_CLK_SEL(x) ((x) << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT)
+
+/* --- CGU_BASE_VADC_CLK values --------------------------------- */
+
+/* PD: Output stage power down */
+#define CGU_BASE_VADC_CLK_PD_SHIFT (0)
+#define CGU_BASE_VADC_CLK_PD (1 << CGU_BASE_VADC_CLK_PD_SHIFT)
+
+/* AUTOBLOCK: Block clock automatically during frequency change */
+#define CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT (11)
+#define CGU_BASE_VADC_CLK_AUTOBLOCK (1 << CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT)
+
+/* CLK_SEL: Clock source selection */
+#define CGU_BASE_VADC_CLK_CLK_SEL_SHIFT (24)
+#define CGU_BASE_VADC_CLK_CLK_SEL_MASK \
+ (0x1f << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT)
+#define CGU_BASE_VADC_CLK_CLK_SEL(x) ((x) << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT)
+
+/* --- CGU_BASE_SDIO_CLK values --------------------------------- */
+
+/* PD: Output stage power down */
+#define CGU_BASE_SDIO_CLK_PD_SHIFT (0)
+#define CGU_BASE_SDIO_CLK_PD (1 << CGU_BASE_SDIO_CLK_PD_SHIFT)
+
+/* AUTOBLOCK: Block clock automatically during frequency change */
+#define CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT (11)
+#define CGU_BASE_SDIO_CLK_AUTOBLOCK (1 << CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT)
+
+/* CLK_SEL: Clock source selection */
+#define CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT (24)
+#define CGU_BASE_SDIO_CLK_CLK_SEL_MASK \
+ (0x1f << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT)
+#define CGU_BASE_SDIO_CLK_CLK_SEL(x) ((x) << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT)
+
+/* --- CGU_BASE_SSP0_CLK values --------------------------------- */
+
+/* PD: Output stage power down */
+#define CGU_BASE_SSP0_CLK_PD_SHIFT (0)
+#define CGU_BASE_SSP0_CLK_PD (1 << CGU_BASE_SSP0_CLK_PD_SHIFT)
+
+/* AUTOBLOCK: Block clock automatically during frequency change */
+#define CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT (11)
+#define CGU_BASE_SSP0_CLK_AUTOBLOCK (1 << CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT)
+
+/* CLK_SEL: Clock source selection */
+#define CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT (24)
+#define CGU_BASE_SSP0_CLK_CLK_SEL_MASK \
+ (0x1f << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT)
+#define CGU_BASE_SSP0_CLK_CLK_SEL(x) ((x) << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT)
+
+/* --- CGU_BASE_SSP1_CLK values --------------------------------- */
+
+/* PD: Output stage power down */
+#define CGU_BASE_SSP1_CLK_PD_SHIFT (0)
+#define CGU_BASE_SSP1_CLK_PD (1 << CGU_BASE_SSP1_CLK_PD_SHIFT)
+
+/* AUTOBLOCK: Block clock automatically during frequency change */
+#define CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT (11)
+#define CGU_BASE_SSP1_CLK_AUTOBLOCK (1 << CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT)
+
+/* CLK_SEL: Clock source selection */
+#define CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT (24)
+#define CGU_BASE_SSP1_CLK_CLK_SEL_MASK \
+ (0x1f << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT)
+#define CGU_BASE_SSP1_CLK_CLK_SEL(x) \
+ ((x) << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT)
+
+/* --- CGU_BASE_UART0_CLK values -------------------------------- */
+
+/* PD: Output stage power down */
+#define CGU_BASE_UART0_CLK_PD_SHIFT (0)
+#define CGU_BASE_UART0_CLK_PD (1 << CGU_BASE_UART0_CLK_PD_SHIFT)
+
+/* AUTOBLOCK: Block clock automatically during frequency change */
+#define CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT (11)
+#define CGU_BASE_UART0_CLK_AUTOBLOCK \
+ (1 << CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT)
+
+/* CLK_SEL: Clock source selection */
+#define CGU_BASE_UART0_CLK_CLK_SEL_SHIFT (24)
+#define CGU_BASE_UART0_CLK_CLK_SEL_MASK \
+ (0x1f << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT)
+#define CGU_BASE_UART0_CLK_CLK_SEL(x) \
+ ((x) << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT)
+
+/* --- CGU_BASE_UART1_CLK values -------------------------------- */
+
+/* PD: Output stage power down */
+#define CGU_BASE_UART1_CLK_PD_SHIFT (0)
+#define CGU_BASE_UART1_CLK_PD (1 << CGU_BASE_UART1_CLK_PD_SHIFT)
+
+/* AUTOBLOCK: Block clock automatically during frequency change */
+#define CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT (11)
+#define CGU_BASE_UART1_CLK_AUTOBLOCK \
+ (1 << CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT)
+
+/* CLK_SEL: Clock source selection */
+#define CGU_BASE_UART1_CLK_CLK_SEL_SHIFT (24)
+#define CGU_BASE_UART1_CLK_CLK_SEL_MASK \
+ (0x1f << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT)
+#define CGU_BASE_UART1_CLK_CLK_SEL(x) \
+ ((x) << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT)
+
+/* --- CGU_BASE_UART2_CLK values -------------------------------- */
+
+/* PD: Output stage power down */
+#define CGU_BASE_UART2_CLK_PD_SHIFT (0)
+#define CGU_BASE_UART2_CLK_PD (1 << CGU_BASE_UART2_CLK_PD_SHIFT)
+
+/* AUTOBLOCK: Block clock automatically during frequency change */
+#define CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT (11)
+#define CGU_BASE_UART2_CLK_AUTOBLOCK \
+ (1 << CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT)
+
+/* CLK_SEL: Clock source selection */
+#define CGU_BASE_UART2_CLK_CLK_SEL_SHIFT (24)
+#define CGU_BASE_UART2_CLK_CLK_SEL_MASK \
+ (0x1f << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT)
+#define CGU_BASE_UART2_CLK_CLK_SEL(x) \
+ ((x) << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT)
+
+/* --- CGU_BASE_UART3_CLK values -------------------------------- */
+
+/* PD: Output stage power down */
+#define CGU_BASE_UART3_CLK_PD_SHIFT (0)
+#define CGU_BASE_UART3_CLK_PD (1 << CGU_BASE_UART3_CLK_PD_SHIFT)
+
+/* AUTOBLOCK: Block clock automatically during frequency change */
+#define CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT (11)
+#define CGU_BASE_UART3_CLK_AUTOBLOCK \
+ (1 << CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT)
+
+/* CLK_SEL: Clock source selection */
+#define CGU_BASE_UART3_CLK_CLK_SEL_SHIFT (24)
+#define CGU_BASE_UART3_CLK_CLK_SEL_MASK \
+ (0x1f << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT)
+#define CGU_BASE_UART3_CLK_CLK_SEL(x) \
+ ((x) << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT)
+
+/* --- CGU_BASE_OUT_CLK values ---------------------------------- */
+
+/* PD: Output stage power down */
+#define CGU_BASE_OUT_CLK_PD_SHIFT (0)
+#define CGU_BASE_OUT_CLK_PD (1 << CGU_BASE_OUT_CLK_PD_SHIFT)
+
+/* AUTOBLOCK: Block clock automatically during frequency change */
+#define CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT (11)
+#define CGU_BASE_OUT_CLK_AUTOBLOCK (1 << CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT)
+
+/* CLK_SEL: Clock source selection */
+#define CGU_BASE_OUT_CLK_CLK_SEL_SHIFT (24)
+#define CGU_BASE_OUT_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT)
+#define CGU_BASE_OUT_CLK_CLK_SEL(x) ((x) << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT)
+
+/* --- CGU_BASE_APLL_CLK values --------------------------------- */
+
+/* PD: Output stage power down */
+#define CGU_BASE_APLL_CLK_PD_SHIFT (0)
+#define CGU_BASE_APLL_CLK_PD (1 << CGU_BASE_APLL_CLK_PD_SHIFT)
+
+/* AUTOBLOCK: Block clock automatically during frequency change */
+#define CGU_BASE_APLL_CLK_AUTOBLOCK_SHIFT (11)
+#define CGU_BASE_APLL_CLK_AUTOBLOCK (1 << CGU_BASE_APLL_CLK_AUTOBLOCK_SHIFT)
+
+/* CLK_SEL: Clock source selection */
+#define CGU_BASE_APLL_CLK_CLK_SEL_SHIFT (24)
+#define CGU_BASE_APLL_CLK_CLK_SEL_MASK \
+ (0x1f << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT)
+#define CGU_BASE_APLL_CLK_CLK_SEL(x) ((x) << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT)
+
+/* --- CGU_BASE_CGU_OUT0_CLK values ----------------------------- */
+
+/* PD: Output stage power down */
+#define CGU_BASE_CGU_OUT0_CLK_PD_SHIFT (0)
+#define CGU_BASE_CGU_OUT0_CLK_PD (1 << CGU_BASE_CGU_OUT0_CLK_PD_SHIFT)
+
+/* AUTOBLOCK: Block clock automatically during frequency change */
+#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT (11)
+#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK \
+ (1 << CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT)
+
+/* CLK_SEL: Clock source selection */
+#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT (24)
+#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_MASK \
+ (0x1f << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT)
+#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL(x) \
+ ((x) << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT)
+
+/* --- CGU_BASE_CGU_OUT1_CLK values ----------------------------- */
+
+/* PD: Output stage power down */
+#define CGU_BASE_CGU_OUT1_CLK_PD_SHIFT (0)
+#define CGU_BASE_CGU_OUT1_CLK_PD (1 << CGU_BASE_CGU_OUT1_CLK_PD_SHIFT)
+
+/* AUTOBLOCK: Block clock automatically during frequency change */
+#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT (11)
+#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK \
+ (1 << CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT)
+
+/* CLK_SEL: Clock source selection */
+#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT (24)
+#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_MASK \
+ (0x1f << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT)
+#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL(x) \
+ ((x) << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT)
+
+/* --- CGU_BASE_x_CLK clock sources --------------------------------------- */
+
+#define CGU_SRC_32K 0x00
+#define CGU_SRC_IRC 0x01
+#define CGU_SRC_ENET_RX 0x02
+#define CGU_SRC_ENET_TX 0x03
+#define CGU_SRC_GP_CLKIN 0x04
+#define CGU_SRC_XTAL 0x06
+#define CGU_SRC_PLL0USB 0x07
+#define CGU_SRC_PLL0AUDIO 0x08
+#define CGU_SRC_PLL1 0x09
+#define CGU_SRC_IDIVA 0x0C
+#define CGU_SRC_IDIVB 0x0D
+#define CGU_SRC_IDIVC 0x0E
+#define CGU_SRC_IDIVD 0x0F
+#define CGU_SRC_IDIVE 0x10
+
+/**@}*/
+
+#endif
diff --git a/libopencm3/include/libopencm3/lpc43xx/creg.h b/libopencm3/include/libopencm3/lpc43xx/creg.h
new file mode 100644
index 0000000..2c69551
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc43xx/creg.h
@@ -0,0 +1,354 @@
+/** @defgroup creg_defines Configuration Registers Defines
+
+@brief Defined Constants and Types for the LPC43xx Configuration
+Registers
+
+@ingroup LPC43xx_defines
+
+@version 1.0.0
+
+@author @htmlonly © @endhtmlonly 2012 Michael Ossmann
+
+@date 10 March 2013
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Michael Ossmann
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LPC43XX_CREG_H
+#define LPC43XX_CREG_H
+
+/**@{*/
+
+#include
+#include
+
+/* --- CREG registers ----------------------------------------------------- */
+
+/*
+ * Chip configuration register 32 kHz oscillator output and BOD control
+ * register
+ */
+#define CREG_CREG0 MMIO32(CREG_BASE + 0x004)
+
+/* ARM Cortex-M4 memory mapping */
+#define CREG_M4MEMMAP MMIO32(CREG_BASE + 0x100)
+
+/* Chip configuration register 1 */
+#define CREG_CREG1 MMIO32(CREG_BASE + 0x108)
+
+/* Chip configuration register 2 */
+#define CREG_CREG2 MMIO32(CREG_BASE + 0x10C)
+
+/* Chip configuration register 3 */
+#define CREG_CREG3 MMIO32(CREG_BASE + 0x110)
+
+/* Chip configuration register 4 */
+#define CREG_CREG4 MMIO32(CREG_BASE + 0x114)
+
+/* Chip configuration register 5 */
+#define CREG_CREG5 MMIO32(CREG_BASE + 0x118)
+
+/* DMA muxing control */
+#define CREG_DMAMUX MMIO32(CREG_BASE + 0x11C)
+
+/* Flash accelerator configuration register for flash bank A */
+#define CREG_FLASHCFGA MMIO32(CREG_BASE + 0x120)
+
+/* Flash accelerator configuration register for flash bank B */
+#define CREG_FLASHCFGB MMIO32(CREG_BASE + 0x124)
+
+/* ETB RAM configuration */
+#define CREG_ETBCFG MMIO32(CREG_BASE + 0x128)
+
+/*
+ * Chip configuration register 6. Controls multiple functions: Ethernet
+ * interface, SCT output, I2S0/1 inputs, EMC clock.
+ */
+#define CREG_CREG6 MMIO32(CREG_BASE + 0x12C)
+
+/* Cortex-M4 TXEV event clear */
+#define CREG_M4TXEVENT MMIO32(CREG_BASE + 0x130)
+
+/* Part ID (Boundary scan ID code, read-only) */
+#define CREG_CHIPID MMIO32(CREG_BASE + 0x200)
+
+/* Cortex-M0 TXEV event clear */
+#define CREG_M0TXEVENT MMIO32(CREG_BASE + 0x400)
+
+/* ARM Cortex-M0 memory mapping */
+#define CREG_M0APPMEMMAP MMIO32(CREG_BASE + 0x404)
+
+/* USB0 frame length adjust register */
+#define CREG_USB0FLADJ MMIO32(CREG_BASE + 0x500)
+
+/* USB1 frame length adjust register */
+#define CREG_USB1FLADJ MMIO32(CREG_BASE + 0x600)
+
+/* --- CREG_CREG0 values ---------------------------------------- */
+
+/* EN1KHZ: Enable 1 kHz output */
+#define CREG_CREG0_EN1KHZ_SHIFT (0)
+#define CREG_CREG0_EN1KHZ (1 << CREG_CREG0_EN1KHZ_SHIFT)
+
+/* EN32KHZ: Enable 32 kHz output */
+#define CREG_CREG0_EN32KHZ_SHIFT (1)
+#define CREG_CREG0_EN32KHZ (1 << CREG_CREG0_EN32KHZ_SHIFT)
+
+/* RESET32KHZ: 32 kHz oscillator reset */
+#define CREG_CREG0_RESET32KHZ_SHIFT (2)
+#define CREG_CREG0_RESET32KHZ (1 << CREG_CREG0_RESET32KHZ_SHIFT)
+
+/* PD32KHZ: 32 kHz power control */
+#define CREG_CREG0_PD32KHZ_SHIFT (3)
+#define CREG_CREG0_PD32KHZ (1 << CREG_CREG0_PD32KHZ_SHIFT)
+
+/* USB0PHY: USB0 PHY power control */
+#define CREG_CREG0_USB0PHY_SHIFT (5)
+#define CREG_CREG0_USB0PHY (1 << CREG_CREG0_USB0PHY_SHIFT)
+
+/* ALARMCTRL: RTC_ALARM pin output control */
+#define CREG_CREG0_ALARMCTRL_SHIFT (6)
+#define CREG_CREG0_ALARMCTRL_MASK (0x3 << CREG_CREG0_ALARMCTRL_SHIFT)
+#define CREG_CREG0_ALARMCTRL(x) ((x) << CREG_CREG0_ALARMCTRL_SHIFT)
+
+/* BODLVL1: BOD trip level to generate an interrupt */
+#define CREG_CREG0_BODLVL1_SHIFT (8)
+#define CREG_CREG0_BODLVL1_MASK (0x3 << CREG_CREG0_BODLVL1_SHIFT)
+#define CREG_CREG0_BODLVL1(x) ((x) << CREG_CREG0_BODLVL1_SHIFT)
+
+/* BODLVL2: BOD trip level to generate a reset */
+#define CREG_CREG0_BODLVL2_SHIFT (10)
+#define CREG_CREG0_BODLVL2_MASK (0x3 << CREG_CREG0_BODLVL2_SHIFT)
+#define CREG_CREG0_BODLVL2(x) ((x) << CREG_CREG0_BODLVL2_SHIFT)
+
+/* SAMPLECTRL: SAMPLE pin input/output control */
+#define CREG_CREG0_SAMPLECTRL_SHIFT (12)
+#define CREG_CREG0_SAMPLECTRL_MASK (0x3 << CREG_CREG0_SAMPLECTRL_SHIFT)
+#define CREG_CREG0_SAMPLECTRL(x) ((x) << CREG_CREG0_SAMPLECTRL_SHIFT)
+
+/* WAKEUP0CTRL: WAKEUP0 pin input/output control */
+#define CREG_CREG0_WAKEUP0CTRL_SHIFT (14)
+#define CREG_CREG0_WAKEUP0CTRL_MASK (0x3 << CREG_CREG0_WAKEUP0CTRL_SHIFT)
+#define CREG_CREG0_WAKEUP0CTRL(x) ((x) << CREG_CREG0_WAKEUP0CTRL_SHIFT)
+
+/* WAKEUP1CTRL: WAKEUP1 pin input/output control */
+#define CREG_CREG0_WAKEUP1CTRL_SHIFT (16)
+#define CREG_CREG0_WAKEUP1CTRL_MASK (0x3 << CREG_CREG0_WAKEUP1CTRL_SHIFT)
+#define CREG_CREG0_WAKEUP1CTRL(x) ((x) << CREG_CREG0_WAKEUP1CTRL_SHIFT)
+
+/* --- CREG_M4MEMMAP values ------------------------------------- */
+
+/* M4MAP: Shadow address when accessing memory at address 0x00000000 */
+#define CREG_M4MEMMAP_M4MAP_SHIFT (12)
+#define CREG_M4MEMMAP_M4MAP_MASK (0xfffff << CREG_M4MEMMAP_M4MAP_SHIFT)
+#define CREG_M4MEMMAP_M4MAP(x) ((x) << CREG_M4MEMMAP_M4MAP_SHIFT)
+
+/* --- CREG_CREG5 values ---------------------------------------- */
+
+/* M4TAPSEL: JTAG debug select for M4 core */
+#define CREG_CREG5_M4TAPSEL_SHIFT (6)
+#define CREG_CREG5_M4TAPSEL (1 << CREG_CREG5_M4TAPSEL_SHIFT)
+
+/* M0APPTAPSEL: JTAG debug select for M0 co-processor */
+#define CREG_CREG5_M0APPTAPSEL_SHIFT (9)
+#define CREG_CREG5_M0APPTAPSEL (1 << CREG_CREG5_M0APPTAPSEL_SHIFT)
+
+/* --- CREG_DMAMUX values --------------------------------------- */
+
+/* DMAMUXPER0: Select DMA to peripheral connection for DMA peripheral 0 */
+#define CREG_DMAMUX_DMAMUXPER0_SHIFT (0)
+#define CREG_DMAMUX_DMAMUXPER0_MASK (0x3 << CREG_DMAMUX_DMAMUXPER0_SHIFT)
+#define CREG_DMAMUX_DMAMUXPER0(x) ((x) << CREG_DMAMUX_DMAMUXPER0_SHIFT)
+
+/* DMAMUXPER1: Select DMA to peripheral connection for DMA peripheral 1 */
+#define CREG_DMAMUX_DMAMUXPER1_SHIFT (2)
+#define CREG_DMAMUX_DMAMUXPER1_MASK (0x3 << CREG_DMAMUX_DMAMUXPER1_SHIFT)
+#define CREG_DMAMUX_DMAMUXPER1(x) ((x) << CREG_DMAMUX_DMAMUXPER1_SHIFT)
+
+/* DMAMUXPER2: Select DMA to peripheral connection for DMA peripheral 2 */
+#define CREG_DMAMUX_DMAMUXPER2_SHIFT (4)
+#define CREG_DMAMUX_DMAMUXPER2_MASK (0x3 << CREG_DMAMUX_DMAMUXPER2_SHIFT)
+#define CREG_DMAMUX_DMAMUXPER2(x) ((x) << CREG_DMAMUX_DMAMUXPER2_SHIFT)
+
+/* DMAMUXPER3: Select DMA to peripheral connection for DMA peripheral 3 */
+#define CREG_DMAMUX_DMAMUXPER3_SHIFT (6)
+#define CREG_DMAMUX_DMAMUXPER3_MASK (0x3 << CREG_DMAMUX_DMAMUXPER3_SHIFT)
+#define CREG_DMAMUX_DMAMUXPER3(x) ((x) << CREG_DMAMUX_DMAMUXPER3_SHIFT)
+
+/* DMAMUXPER4: Select DMA to peripheral connection for DMA peripheral 4 */
+#define CREG_DMAMUX_DMAMUXPER4_SHIFT (8)
+#define CREG_DMAMUX_DMAMUXPER4_MASK (0x3 << CREG_DMAMUX_DMAMUXPER4_SHIFT)
+#define CREG_DMAMUX_DMAMUXPER4(x) ((x) << CREG_DMAMUX_DMAMUXPER4_SHIFT)
+
+/* DMAMUXPER5: Select DMA to peripheral connection for DMA peripheral 5 */
+#define CREG_DMAMUX_DMAMUXPER5_SHIFT (10)
+#define CREG_DMAMUX_DMAMUXPER5_MASK (0x3 << CREG_DMAMUX_DMAMUXPER5_SHIFT)
+#define CREG_DMAMUX_DMAMUXPER5(x) ((x) << CREG_DMAMUX_DMAMUXPER5_SHIFT)
+
+/* DMAMUXPER6: Select DMA to peripheral connection for DMA peripheral 6 */
+#define CREG_DMAMUX_DMAMUXPER6_SHIFT (12)
+#define CREG_DMAMUX_DMAMUXPER6_MASK (0x3 << CREG_DMAMUX_DMAMUXPER6_SHIFT)
+#define CREG_DMAMUX_DMAMUXPER6(x) ((x) << CREG_DMAMUX_DMAMUXPER6_SHIFT)
+
+/* DMAMUXPER7: Select DMA to peripheral connection for DMA peripheral 7 */
+#define CREG_DMAMUX_DMAMUXPER7_SHIFT (14)
+#define CREG_DMAMUX_DMAMUXPER7_MASK (0x3 << CREG_DMAMUX_DMAMUXPER7_SHIFT)
+#define CREG_DMAMUX_DMAMUXPER7(x) ((x) << CREG_DMAMUX_DMAMUXPER7_SHIFT)
+
+/* DMAMUXPER8: Select DMA to peripheral connection for DMA peripheral 8 */
+#define CREG_DMAMUX_DMAMUXPER8_SHIFT (16)
+#define CREG_DMAMUX_DMAMUXPER8_MASK (0x3 << CREG_DMAMUX_DMAMUXPER8_SHIFT)
+#define CREG_DMAMUX_DMAMUXPER8(x) ((x) << CREG_DMAMUX_DMAMUXPER8_SHIFT)
+
+/* DMAMUXPER9: Select DMA to peripheral connection for DMA peripheral 9 */
+#define CREG_DMAMUX_DMAMUXPER9_SHIFT (18)
+#define CREG_DMAMUX_DMAMUXPER9_MASK (0x3 << CREG_DMAMUX_DMAMUXPER9_SHIFT)
+#define CREG_DMAMUX_DMAMUXPER9(x) ((x) << CREG_DMAMUX_DMAMUXPER9_SHIFT)
+
+/* DMAMUXPER10: Select DMA to peripheral connection for DMA peripheral 10 */
+#define CREG_DMAMUX_DMAMUXPER10_SHIFT (20)
+#define CREG_DMAMUX_DMAMUXPER10_MASK (0x3 << CREG_DMAMUX_DMAMUXPER10_SHIFT)
+#define CREG_DMAMUX_DMAMUXPER10(x) ((x) << CREG_DMAMUX_DMAMUXPER10_SHIFT)
+
+/* DMAMUXPER11: Select DMA to peripheral connection for DMA peripheral 11 */
+#define CREG_DMAMUX_DMAMUXPER11_SHIFT (22)
+#define CREG_DMAMUX_DMAMUXPER11_MASK (0x3 << CREG_DMAMUX_DMAMUXPER11_SHIFT)
+#define CREG_DMAMUX_DMAMUXPER11(x) ((x) << CREG_DMAMUX_DMAMUXPER11_SHIFT)
+
+/* DMAMUXPER12: Select DMA to peripheral connection for DMA peripheral 12 */
+#define CREG_DMAMUX_DMAMUXPER12_SHIFT (24)
+#define CREG_DMAMUX_DMAMUXPER12_MASK (0x3 << CREG_DMAMUX_DMAMUXPER12_SHIFT)
+#define CREG_DMAMUX_DMAMUXPER12(x) ((x) << CREG_DMAMUX_DMAMUXPER12_SHIFT)
+
+/* DMAMUXPER13: Select DMA to peripheral connection for DMA peripheral 13 */
+#define CREG_DMAMUX_DMAMUXPER13_SHIFT (26)
+#define CREG_DMAMUX_DMAMUXPER13_MASK (0x3 << CREG_DMAMUX_DMAMUXPER13_SHIFT)
+#define CREG_DMAMUX_DMAMUXPER13(x) ((x) << CREG_DMAMUX_DMAMUXPER13_SHIFT)
+
+/* DMAMUXPER14: Select DMA to peripheral connection for DMA peripheral 14 */
+#define CREG_DMAMUX_DMAMUXPER14_SHIFT (28)
+#define CREG_DMAMUX_DMAMUXPER14_MASK (0x3 << CREG_DMAMUX_DMAMUXPER14_SHIFT)
+#define CREG_DMAMUX_DMAMUXPER14(x) ((x) << CREG_DMAMUX_DMAMUXPER14_SHIFT)
+
+/* DMAMUXPER15: Select DMA to peripheral connection for DMA peripheral 15 */
+#define CREG_DMAMUX_DMAMUXPER15_SHIFT (30)
+#define CREG_DMAMUX_DMAMUXPER15_MASK (0x3 << CREG_DMAMUX_DMAMUXPER15_SHIFT)
+#define CREG_DMAMUX_DMAMUXPER15(x) ((x) << CREG_DMAMUX_DMAMUXPER15_SHIFT)
+
+/* --- CREG_FLASHCFGA values ------------------------------------ */
+
+/* FLASHTIM: Flash access time. The value of this field plus 1 gives the number
+ * of BASE_M4_CLK clocks used for a flash access */
+#define CREG_FLASHCFGA_FLASHTIM_SHIFT (12)
+#define CREG_FLASHCFGA_FLASHTIM_MASK (0xf << CREG_FLASHCFGA_FLASHTIM_SHIFT)
+#define CREG_FLASHCFGA_FLASHTIM(x) ((x) << CREG_FLASHCFGA_FLASHTIM_SHIFT)
+
+/* POW: Flash bank A power control */
+#define CREG_FLASHCFGA_POW_SHIFT (31)
+#define CREG_FLASHCFGA_POW (1 << CREG_FLASHCFGA_POW_SHIFT)
+
+/* --- CREG_FLASHCFGB values ------------------------------------ */
+
+/* FLASHTIM: Flash access time. The value of this field plus 1 gives the number
+ * of BASE_M4_CLK clocks used for a flash access */
+#define CREG_FLASHCFGB_FLASHTIM_SHIFT (12)
+#define CREG_FLASHCFGB_FLASHTIM_MASK (0xf << CREG_FLASHCFGB_FLASHTIM_SHIFT)
+#define CREG_FLASHCFGB_FLASHTIM(x) ((x) << CREG_FLASHCFGB_FLASHTIM_SHIFT)
+
+/* POW: Flash bank B power control */
+#define CREG_FLASHCFGB_POW_SHIFT (31)
+#define CREG_FLASHCFGB_POW (1 << CREG_FLASHCFGB_POW_SHIFT)
+
+/* --- CREG_ETBCFG values --------------------------------------- */
+
+/* ETB: Select SRAM interface */
+#define CREG_ETBCFG_ETB_SHIFT (0)
+#define CREG_ETBCFG_ETB (1 << CREG_ETBCFG_ETB_SHIFT)
+
+/* --- CREG_CREG6 values ---------------------------------------- */
+
+/* ETHMODE: Selects the Ethernet mode. Reset the ethernet after changing the
+ * PHY interface */
+#define CREG_CREG6_ETHMODE_SHIFT (0)
+#define CREG_CREG6_ETHMODE_MASK (0x7 << CREG_CREG6_ETHMODE_SHIFT)
+#define CREG_CREG6_ETHMODE(x) ((x) << CREG_CREG6_ETHMODE_SHIFT)
+
+/* CTOUTCTRL: Selects the functionality of the SCT outputs */
+#define CREG_CREG6_CTOUTCTRL_SHIFT (4)
+#define CREG_CREG6_CTOUTCTRL (1 << CREG_CREG6_CTOUTCTRL_SHIFT)
+
+/* I2S0_TX_SCK_IN_SEL: I2S0_TX_SCK input select */
+#define CREG_CREG6_I2S0_TX_SCK_IN_SEL_SHIFT (12)
+#define CREG_CREG6_I2S0_TX_SCK_IN_SEL (1 << CREG_CREG6_I2S0_TX_SCK_IN_SEL_SHIFT)
+
+/* I2S0_RX_SCK_IN_SEL: I2S0_RX_SCK input select */
+#define CREG_CREG6_I2S0_RX_SCK_IN_SEL_SHIFT (13)
+#define CREG_CREG6_I2S0_RX_SCK_IN_SEL (1 << CREG_CREG6_I2S0_RX_SCK_IN_SEL_SHIFT)
+
+/* I2S1_TX_SCK_IN_SEL: I2S1_TX_SCK input select */
+#define CREG_CREG6_I2S1_TX_SCK_IN_SEL_SHIFT (14)
+#define CREG_CREG6_I2S1_TX_SCK_IN_SEL (1 << CREG_CREG6_I2S1_TX_SCK_IN_SEL_SHIFT)
+
+/* I2S1_RX_SCK_IN_SEL: I2S1_RX_SCK input select */
+#define CREG_CREG6_I2S1_RX_SCK_IN_SEL_SHIFT (15)
+#define CREG_CREG6_I2S1_RX_SCK_IN_SEL (1 << CREG_CREG6_I2S1_RX_SCK_IN_SEL_SHIFT)
+
+/* EMC_CLK_SEL: EMC_CLK divided clock select */
+#define CREG_CREG6_EMC_CLK_SEL_SHIFT (16)
+#define CREG_CREG6_EMC_CLK_SEL (1 << CREG_CREG6_EMC_CLK_SEL_SHIFT)
+
+/* --- CREG_M4TXEVENT values ------------------------------------ */
+
+/* TXEVCLR: Cortex-M4 TXEV event */
+#define CREG_M4TXEVENT_TXEVCLR_SHIFT (0)
+#define CREG_M4TXEVENT_TXEVCLR (1 << CREG_M4TXEVENT_TXEVCLR_SHIFT)
+
+/* --- CREG_M0TXEVENT values ------------------------------------ */
+
+/* TXEVCLR: Cortex-M0 TXEV event */
+#define CREG_M0TXEVENT_TXEVCLR_SHIFT (0)
+#define CREG_M0TXEVENT_TXEVCLR (1 << CREG_M0TXEVENT_TXEVCLR_SHIFT)
+
+/* --- CREG_M0APPMEMMAP values ---------------------------------- */
+
+/* M0APPMAP: Shadow address when accessing memory at address 0x00000000 */
+#define CREG_M0APPMEMMAP_M0APPMAP_SHIFT (12)
+#define CREG_M0APPMEMMAP_M0APPMAP_MASK \
+ (0xfffff << CREG_M0APPMEMMAP_M0APPMAP_SHIFT)
+#define CREG_M0APPMEMMAP_M0APPMAP(x) ((x) << CREG_M0APPMEMMAP_M0APPMAP_SHIFT)
+
+/* --- CREG_USB0FLADJ values ------------------------------------ */
+
+/* FLTV: Frame length timing value */
+#define CREG_USB0FLADJ_FLTV_SHIFT (0)
+#define CREG_USB0FLADJ_FLTV_MASK (0x3f << CREG_USB0FLADJ_FLTV_SHIFT)
+#define CREG_USB0FLADJ_FLTV(x) ((x) << CREG_USB0FLADJ_FLTV_SHIFT)
+
+/* --- CREG_USB1FLADJ values ------------------------------------ */
+
+/* FLTV: Frame length timing value */
+#define CREG_USB1FLADJ_FLTV_SHIFT (0)
+#define CREG_USB1FLADJ_FLTV_MASK (0x3f << CREG_USB1FLADJ_FLTV_SHIFT)
+#define CREG_USB1FLADJ_FLTV(x) ((x) << CREG_USB1FLADJ_FLTV_SHIFT)
+
+/**@}*/
+
+#endif
diff --git a/libopencm3/include/libopencm3/lpc43xx/doc-lpc43xx.h b/libopencm3/include/libopencm3/lpc43xx/doc-lpc43xx.h
new file mode 100644
index 0000000..3c21aae
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc43xx/doc-lpc43xx.h
@@ -0,0 +1,32 @@
+/** @mainpage libopencm3 LPC43xx
+
+@version 1.0.0
+
+@date 14 September 2012
+
+API documentation for NXP Semiconductors LPC43xx Cortex M3 series.
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup LPC43xx LPC43xx
+Libraries for NXP Semiconductors LPC43xx series.
+
+@version 1.0.0
+
+@date 14 September 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup LPC43xx_defines LPC43xx Defines
+
+@brief Defined Constants and Types for the LPC43xx series
+
+@version 1.0.0
+
+@date 14 September 2012
+
+LGPL License Terms @ref lgpl_license
+*/
+
diff --git a/libopencm3/include/libopencm3/lpc43xx/eventrouter.h b/libopencm3/include/libopencm3/lpc43xx/eventrouter.h
new file mode 100644
index 0000000..d27c67c
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc43xx/eventrouter.h
@@ -0,0 +1,70 @@
+/** @defgroup eventrouter_defines Event Router Defines
+
+@brief Defined Constants and Types for the LPC43xx Event Router
+
+@ingroup LPC43xx_defines
+
+@version 1.0.0
+
+@author @htmlonly © @endhtmlonly 2012 Michael Ossmann
+
+@date 10 March 2013
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Michael Ossmann
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LPC43XX_EVENTROUTER_H
+#define LPC43XX_EVENTROUTER_H
+
+/**@{*/
+
+#include
+#include
+
+/* --- Event Router registers ---------------------------------------------- */
+
+/* Level configuration register */
+#define EVENTROUTER_HILO MMIO32(EVENTROUTER_BASE + 0x000)
+
+/* Edge configuration */
+#define EVENTROUTER_EDGE MMIO32(EVENTROUTER_BASE + 0x004)
+
+/* Clear event enable register */
+#define EVENTROUTER_CLR_EN MMIO32(EVENTROUTER_BASE + 0xFD8)
+
+/* Set event enable register */
+#define EVENTROUTER_SET_EN MMIO32(EVENTROUTER_BASE + 0xFDC)
+
+/* Event Status register */
+#define EVENTROUTER_STATUS MMIO32(EVENTROUTER_BASE + 0xFE0)
+
+/* Event Enable register */
+#define EVENTROUTER_ENABLE MMIO32(EVENTROUTER_BASE + 0xFE4)
+
+/* Clear event status register */
+#define EVENTROUTER_CLR_STAT MMIO32(EVENTROUTER_BASE + 0xFE8)
+
+/* Set event status register */
+#define EVENTROUTER_SET_STAT MMIO32(EVENTROUTER_BASE + 0xFEC)
+
+/**@}*/
+
+#endif
diff --git a/libopencm3/include/libopencm3/lpc43xx/gima.h b/libopencm3/include/libopencm3/lpc43xx/gima.h
new file mode 100644
index 0000000..6a36c76
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc43xx/gima.h
@@ -0,0 +1,137 @@
+/** @defgroup gima_defines Global Input Multiplexer Array Defines
+
+@brief Defined Constants and Types for the LPC43xx Global Input Multiplexer
+Array
+
+@ingroup LPC43xx_defines
+
+@version 1.0.0
+
+@author @htmlonly © @endhtmlonly 2012 Michael Ossmann
+
+@date 10 March 2013
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Michael Ossmann
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LPC43XX_GIMA_H
+#define LPC43XX_GIMA_H
+
+/**@{*/
+
+#include
+#include
+
+/* --- GIMA registers ----------------------------------------------------- */
+
+/* Timer 0 CAP0_0 capture input multiplexer (GIMA output 0) */
+#define GIMA_CAP0_0_IN MMIO32(GIMA_BASE + 0x000)
+
+/* Timer 0 CAP0_1 capture input multiplexer (GIMA output 1) */
+#define GIMA_CAP0_1_IN MMIO32(GIMA_BASE + 0x004)
+
+/* Timer 0 CAP0_2 capture input multiplexer (GIMA output 2) */
+#define GIMA_CAP0_2_IN MMIO32(GIMA_BASE + 0x008)
+
+/* Timer 0 CAP0_3 capture input multiplexer (GIMA output 3) */
+#define GIMA_CAP0_3_IN MMIO32(GIMA_BASE + 0x00C)
+
+/* Timer 1 CAP1_0 capture input multiplexer (GIMA output 4) */
+#define GIMA_CAP1_0_IN MMIO32(GIMA_BASE + 0x010)
+
+/* Timer 1 CAP1_1 capture input multiplexer (GIMA output 5) */
+#define GIMA_CAP1_1_IN MMIO32(GIMA_BASE + 0x014)
+
+/* Timer 1 CAP1_2 capture input multiplexer (GIMA output 6) */
+#define GIMA_CAP1_2_IN MMIO32(GIMA_BASE + 0x018)
+
+/* Timer 1 CAP1_3 capture input multiplexer (GIMA output 7) */
+#define GIMA_CAP1_3_IN MMIO32(GIMA_BASE + 0x01C)
+
+/* Timer 2 CAP2_0 capture input multiplexer (GIMA output 8) */
+#define GIMA_CAP2_0_IN MMIO32(GIMA_BASE + 0x020)
+
+/* Timer 2 CAP2_1 capture input multiplexer (GIMA output 9) */
+#define GIMA_CAP2_1_IN MMIO32(GIMA_BASE + 0x024)
+
+/* Timer 2 CAP2_2 capture input multiplexer (GIMA output 10) */
+#define GIMA_CAP2_2_IN MMIO32(GIMA_BASE + 0x028)
+
+/* Timer 2 CAP2_3 capture input multiplexer (GIMA output 11) */
+#define GIMA_CAP2_3_IN MMIO32(GIMA_BASE + 0x02C)
+
+/* Timer 3 CAP3_0 capture input multiplexer (GIMA output 12) */
+#define GIMA_CAP3_0_IN MMIO32(GIMA_BASE + 0x030)
+
+/* Timer 3 CAP3_1 capture input multiplexer (GIMA output 13) */
+#define GIMA_CAP3_1_IN MMIO32(GIMA_BASE + 0x034)
+
+/* Timer 3 CAP3_2 capture input multiplexer (GIMA output 14) */
+#define GIMA_CAP3_2_IN MMIO32(GIMA_BASE + 0x038)
+
+/* Timer 3 CAP3_3 capture input multiplexer (GIMA output 15) */
+#define GIMA_CAP3_3_IN MMIO32(GIMA_BASE + 0x03C)
+
+/* SCT CTIN_0 capture input multiplexer (GIMA output 16) */
+#define GIMA_CTIN_0_IN MMIO32(GIMA_BASE + 0x040)
+
+/* SCT CTIN_1 capture input multiplexer (GIMA output 17) */
+#define GIMA_CTIN_1_IN MMIO32(GIMA_BASE + 0x044)
+
+/* SCT CTIN_2 capture input multiplexer (GIMA output 18) */
+#define GIMA_CTIN_2_IN MMIO32(GIMA_BASE + 0x048)
+
+/* SCT CTIN_3 capture input multiplexer (GIMA output 19) */
+#define GIMA_CTIN_3_IN MMIO32(GIMA_BASE + 0x04C)
+
+/* SCT CTIN_4 capture input multiplexer (GIMA output 20) */
+#define GIMA_CTIN_4_IN MMIO32(GIMA_BASE + 0x050)
+
+/* SCT CTIN_5 capture input multiplexer (GIMA output 21) */
+#define GIMA_CTIN_5_IN MMIO32(GIMA_BASE + 0x054)
+
+/* SCT CTIN_6 capture input multiplexer (GIMA output 22) */
+#define GIMA_CTIN_6_IN MMIO32(GIMA_BASE + 0x058)
+
+/* SCT CTIN_7 capture input multiplexer (GIMA output 23) */
+#define GIMA_CTIN_7_IN MMIO32(GIMA_BASE + 0x05C)
+
+/* VADC trigger input multiplexer (GIMA output 24) */
+#define GIMA_VADC_TRIGGER_IN MMIO32(GIMA_BASE + 0x060)
+
+/* Event router input 13 multiplexer (GIMA output 25) */
+#define GIMA_EVENTROUTER_13_IN MMIO32(GIMA_BASE + 0x064)
+
+/* Event router input 14 multiplexer (GIMA output 26) */
+#define GIMA_EVENTROUTER_14_IN MMIO32(GIMA_BASE + 0x068)
+
+/* Event router input 16 multiplexer (GIMA output 27) */
+#define GIMA_EVENTROUTER_16_IN MMIO32(GIMA_BASE + 0x06C)
+
+/* ADC start0 input multiplexer (GIMA output 28) */
+#define GIMA_ADCSTART0_IN MMIO32(GIMA_BASE + 0x070)
+
+/* ADC start1 input multiplexer (GIMA output 29) */
+#define GIMA_ADCSTART1_IN MMIO32(GIMA_BASE + 0x074)
+
+/**@}*/
+
+#endif
diff --git a/libopencm3/include/libopencm3/lpc43xx/gpdma.h b/libopencm3/include/libopencm3/lpc43xx/gpdma.h
new file mode 100644
index 0000000..9df6698
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc43xx/gpdma.h
@@ -0,0 +1,552 @@
+/** @defgroup gpdma_defines General Purpose DMA Defines
+ *
+ * @brief Defined Constants and Types for the LPC43xx General Purpose DMA
+ *
+ * @ingroup LPC43xx_defines
+ *
+ * @version 1.0.0
+ *
+ * @author @htmlonly © @endhtmlonly 2012 Michael Ossmann
+ *
+ * @date 10 March 2013
+ *
+ * LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Michael Ossmann
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LPC43XX_GPDMA_H
+#define LPC43XX_GPDMA_H
+
+/**@{*/
+
+#include
+#include
+
+/* --- GPDMA registers ----------------------------------------------------- */
+
+/* General registers */
+
+/* DMA Interrupt Status Register */
+#define GPDMA_INTSTAT MMIO32(GPDMA_BASE + 0x000)
+
+/* DMA Interrupt Terminal Count Request Status Register */
+#define GPDMA_INTTCSTAT MMIO32(GPDMA_BASE + 0x004)
+
+/* DMA Interrupt Terminal Count Request Clear Register */
+#define GPDMA_INTTCCLEAR MMIO32(GPDMA_BASE + 0x008)
+
+/* DMA Interrupt Error Status Register */
+#define GPDMA_INTERRSTAT MMIO32(GPDMA_BASE + 0x00C)
+
+/* DMA Interrupt Error Clear Register */
+#define GPDMA_INTERRCLR MMIO32(GPDMA_BASE + 0x010)
+
+/* DMA Raw Interrupt Terminal Count Status Register */
+#define GPDMA_RAWINTTCSTAT MMIO32(GPDMA_BASE + 0x014)
+
+/* DMA Raw Error Interrupt Status Register */
+#define GPDMA_RAWINTERRSTAT MMIO32(GPDMA_BASE + 0x018)
+
+/* DMA Enabled Channel Register */
+#define GPDMA_ENBLDCHNS MMIO32(GPDMA_BASE + 0x01C)
+
+/* DMA Software Burst Request Register */
+#define GPDMA_SOFTBREQ MMIO32(GPDMA_BASE + 0x020)
+
+/* DMA Software Single Request Register */
+#define GPDMA_SOFTSREQ MMIO32(GPDMA_BASE + 0x024)
+
+/* DMA Software Last Burst Request Register */
+#define GPDMA_SOFTLBREQ MMIO32(GPDMA_BASE + 0x028)
+
+/* DMA Software Last Single Request Register */
+#define GPDMA_SOFTLSREQ MMIO32(GPDMA_BASE + 0x02C)
+
+/* DMA Configuration Register */
+#define GPDMA_CONFIG MMIO32(GPDMA_BASE + 0x030)
+
+/* DMA Synchronization Register */
+#define GPDMA_SYNC MMIO32(GPDMA_BASE + 0x034)
+
+
+/* Channel registers */
+
+/* Source Address Register */
+#define GPDMA_CSRCADDR(channel) MMIO32(GPDMA_BASE + 0x100 + \
+ (channel * 0x20))
+#define GPDMA_C0SRCADDR GPDMA_CSRCADDR(0)
+#define GPDMA_C1SRCADDR GPDMA_CSRCADDR(1)
+#define GPDMA_C2SRCADDR GPDMA_CSRCADDR(2)
+#define GPDMA_C3SRCADDR GPDMA_CSRCADDR(3)
+#define GPDMA_C4SRCADDR GPDMA_CSRCADDR(4)
+#define GPDMA_C5SRCADDR GPDMA_CSRCADDR(5)
+#define GPDMA_C6SRCADDR GPDMA_CSRCADDR(6)
+#define GPDMA_C7SRCADDR GPDMA_CSRCADDR(7)
+
+/* Destination Address Register */
+#define GPDMA_CDESTADDR(channel) MMIO32(GPDMA_BASE + 0x104 + \
+ (channel * 0x20))
+#define GPDMA_C0DESTADDR GPDMA_CDESTADDR(0)
+#define GPDMA_C1DESTADDR GPDMA_CDESTADDR(1)
+#define GPDMA_C2DESTADDR GPDMA_CDESTADDR(2)
+#define GPDMA_C3DESTADDR GPDMA_CDESTADDR(3)
+#define GPDMA_C4DESTADDR GPDMA_CDESTADDR(4)
+#define GPDMA_C5DESTADDR GPDMA_CDESTADDR(5)
+#define GPDMA_C6DESTADDR GPDMA_CDESTADDR(6)
+#define GPDMA_C7DESTADDR GPDMA_CDESTADDR(7)
+
+/* Linked List Item Register */
+#define GPDMA_CLLI(channel) MMIO32(GPDMA_BASE + 0x108 + \
+ (channel * 0x20))
+#define GPDMA_C0LLI GPDMA_CLLI(0)
+#define GPDMA_C1LLI GPDMA_CLLI(1)
+#define GPDMA_C2LLI GPDMA_CLLI(2)
+#define GPDMA_C3LLI GPDMA_CLLI(3)
+#define GPDMA_C4LLI GPDMA_CLLI(4)
+#define GPDMA_C5LLI GPDMA_CLLI(5)
+#define GPDMA_C6LLI GPDMA_CLLI(6)
+#define GPDMA_C7LLI GPDMA_CLLI(7)
+
+/* Control Register */
+#define GPDMA_CCONTROL(channel) MMIO32(GPDMA_BASE + 0x10C + \
+ (channel * 0x20))
+#define GPDMA_C0CONTROL GPDMA_CCONTROL(0)
+#define GPDMA_C1CONTROL GPDMA_CCONTROL(1)
+#define GPDMA_C2CONTROL GPDMA_CCONTROL(2)
+#define GPDMA_C3CONTROL GPDMA_CCONTROL(3)
+#define GPDMA_C4CONTROL GPDMA_CCONTROL(4)
+#define GPDMA_C5CONTROL GPDMA_CCONTROL(5)
+#define GPDMA_C6CONTROL GPDMA_CCONTROL(6)
+#define GPDMA_C7CONTROL GPDMA_CCONTROL(7)
+
+/* Configuration Register */
+#define GPDMA_CCONFIG(channel) MMIO32(GPDMA_BASE + 0x110 + \
+ (channel * 0x20))
+#define GPDMA_C0CONFIG GPDMA_CCONFIG(0)
+#define GPDMA_C1CONFIG GPDMA_CCONFIG(1)
+#define GPDMA_C2CONFIG GPDMA_CCONFIG(2)
+#define GPDMA_C3CONFIG GPDMA_CCONFIG(3)
+#define GPDMA_C4CONFIG GPDMA_CCONFIG(4)
+#define GPDMA_C5CONFIG GPDMA_CCONFIG(5)
+#define GPDMA_C6CONFIG GPDMA_CCONFIG(6)
+#define GPDMA_C7CONFIG GPDMA_CCONFIG(7)
+
+/* --- Common fields -------------------------------------------- */
+
+#define GPDMA_CSRCADDR_SRCADDR_SHIFT (0)
+#define GPDMA_CSRCADDR_SRCADDR_MASK (0xffffffff << GPDMA_CSRCADDR_SRCADDR_SHIFT)
+#define GPDMA_CSRCADDR_SRCADDR(x) ((x) << GPDMA_CSRCADDR_SRCADDR_SHIFT)
+
+#define GPDMA_CDESTADDR_DESTADDR_SHIFT (0)
+#define GPDMA_CDESTADDR_DESTADDR_MASK \
+ (0xffffffff << GPDMA_CDESTADDR_DESTADDR_SHIFT)
+#define GPDMA_CDESTADDR_DESTADDR(x) ((x) << GPDMA_CDESTADDR_DESTADDR_SHIFT)
+
+#define GPDMA_CLLI_LM_SHIFT (0)
+#define GPDMA_CLLI_LM_MASK (0x1 << GPDMA_CLLI_LM_SHIFT)
+#define GPDMA_CLLI_LM(x) ((x) << GPDMA_CLLI_LM_SHIFT)
+
+#define GPDMA_CLLI_LLI_SHIFT (2)
+#define GPDMA_CLLI_LLI_MASK (0x3fffffff << GPDMA_CLLI_LLI_SHIFT)
+#define GPDMA_CLLI_LLI(x) ((x) << GPDMA_CLLI_LLI_SHIFT)
+
+#define GPDMA_CCONTROL_TRANSFERSIZE_SHIFT (0)
+#define GPDMA_CCONTROL_TRANSFERSIZE_MASK \
+ (0xfff << GPDMA_CCONTROL_TRANSFERSIZE_SHIFT)
+#define GPDMA_CCONTROL_TRANSFERSIZE(x) \
+ ((x) << GPDMA_CCONTROL_TRANSFERSIZE_SHIFT)
+
+#define GPDMA_CCONTROL_SBSIZE_SHIFT (12)
+#define GPDMA_CCONTROL_SBSIZE_MASK (0x7 << GPDMA_CCONTROL_SBSIZE_SHIFT)
+#define GPDMA_CCONTROL_SBSIZE(x) ((x) << GPDMA_CCONTROL_SBSIZE_SHIFT)
+
+#define GPDMA_CCONTROL_DBSIZE_SHIFT (15)
+#define GPDMA_CCONTROL_DBSIZE_MASK (0x7 << GPDMA_CCONTROL_DBSIZE_SHIFT)
+#define GPDMA_CCONTROL_DBSIZE(x) ((x) << GPDMA_CCONTROL_DBSIZE_SHIFT)
+
+#define GPDMA_CCONTROL_SWIDTH_SHIFT (18)
+#define GPDMA_CCONTROL_SWIDTH_MASK (0x7 << GPDMA_CCONTROL_SWIDTH_SHIFT)
+#define GPDMA_CCONTROL_SWIDTH(x) ((x) << GPDMA_CCONTROL_SWIDTH_SHIFT)
+
+#define GPDMA_CCONTROL_DWIDTH_SHIFT (21)
+#define GPDMA_CCONTROL_DWIDTH_MASK (0x7 << GPDMA_CCONTROL_DWIDTH_SHIFT)
+#define GPDMA_CCONTROL_DWIDTH(x) ((x) << GPDMA_CCONTROL_DWIDTH_SHIFT)
+
+#define GPDMA_CCONTROL_S_SHIFT (24)
+#define GPDMA_CCONTROL_S_MASK (0x1 << GPDMA_CCONTROL_S_SHIFT)
+#define GPDMA_CCONTROL_S(x) ((x) << GPDMA_CCONTROL_S_SHIFT)
+
+#define GPDMA_CCONTROL_D_SHIFT (25)
+#define GPDMA_CCONTROL_D_MASK (0x1 << GPDMA_CCONTROL_D_SHIFT)
+#define GPDMA_CCONTROL_D(x) ((x) << GPDMA_CCONTROL_D_SHIFT)
+
+#define GPDMA_CCONTROL_SI_SHIFT (26)
+#define GPDMA_CCONTROL_SI_MASK (0x1 << GPDMA_CCONTROL_SI_SHIFT)
+#define GPDMA_CCONTROL_SI(x) ((x) << GPDMA_CCONTROL_SI_SHIFT)
+
+#define GPDMA_CCONTROL_DI_SHIFT (27)
+#define GPDMA_CCONTROL_DI_MASK (0x1 << GPDMA_CCONTROL_DI_SHIFT)
+#define GPDMA_CCONTROL_DI(x) ((x) << GPDMA_CCONTROL_DI_SHIFT)
+
+#define GPDMA_CCONTROL_PROT1_SHIFT (28)
+#define GPDMA_CCONTROL_PROT1_MASK (0x1 << GPDMA_CCONTROL_PROT1_SHIFT)
+#define GPDMA_CCONTROL_PROT1(x) ((x) << GPDMA_CCONTROL_PROT1_SHIFT)
+
+#define GPDMA_CCONTROL_PROT2_SHIFT (29)
+#define GPDMA_CCONTROL_PROT2_MASK (0x1 << GPDMA_CCONTROL_PROT2_SHIFT)
+#define GPDMA_CCONTROL_PROT2(x) ((x) << GPDMA_CCONTROL_PROT2_SHIFT)
+
+#define GPDMA_CCONTROL_PROT3_SHIFT (30)
+#define GPDMA_CCONTROL_PROT3_MASK (0x1 << GPDMA_CCONTROL_PROT3_SHIFT)
+#define GPDMA_CCONTROL_PROT3(x) ((x) << GPDMA_CCONTROL_PROT3_SHIFT)
+
+#define GPDMA_CCONTROL_I_SHIFT (31)
+#define GPDMA_CCONTROL_I_MASK (0x1 << GPDMA_CCONTROL_I_SHIFT)
+#define GPDMA_CCONTROL_I(x) ((x) << GPDMA_CCONTROL_I_SHIFT)
+
+#define GPDMA_CCONFIG_E_SHIFT (0)
+#define GPDMA_CCONFIG_E_MASK (0x1 << GPDMA_CCONFIG_E_SHIFT)
+#define GPDMA_CCONFIG_E(x) ((x) << GPDMA_CCONFIG_E_SHIFT)
+
+#define GPDMA_CCONFIG_SRCPERIPHERAL_SHIFT (1)
+#define GPDMA_CCONFIG_SRCPERIPHERAL_MASK \
+ (0x1f << GPDMA_CCONFIG_SRCPERIPHERAL_SHIFT)
+#define GPDMA_CCONFIG_SRCPERIPHERAL(x) \
+ ((x) << GPDMA_CCONFIG_SRCPERIPHERAL_SHIFT)
+
+#define GPDMA_CCONFIG_DESTPERIPHERAL_SHIFT (6)
+#define GPDMA_CCONFIG_DESTPERIPHERAL_MASK \
+ (0x1f << GPDMA_CCONFIG_DESTPERIPHERAL_SHIFT)
+#define GPDMA_CCONFIG_DESTPERIPHERAL(x) \
+ ((x) << GPDMA_CCONFIG_DESTPERIPHERAL_SHIFT)
+
+#define GPDMA_CCONFIG_FLOWCNTRL_SHIFT (11)
+#define GPDMA_CCONFIG_FLOWCNTRL_MASK (0x7 << GPDMA_CCONFIG_FLOWCNTRL_SHIFT)
+#define GPDMA_CCONFIG_FLOWCNTRL(x) ((x) << GPDMA_CCONFIG_FLOWCNTRL_SHIFT)
+
+#define GPDMA_CCONFIG_IE_SHIFT (14)
+#define GPDMA_CCONFIG_IE_MASK (0x1 << GPDMA_CCONFIG_IE_SHIFT)
+#define GPDMA_CCONFIG_IE(x) ((x) << GPDMA_CCONFIG_IE_SHIFT)
+
+#define GPDMA_CCONFIG_ITC_SHIFT (15)
+#define GPDMA_CCONFIG_ITC_MASK (0x1 << GPDMA_CCONFIG_ITC_SHIFT)
+#define GPDMA_CCONFIG_ITC(x) ((x) << GPDMA_CCONFIG_ITC_SHIFT)
+
+#define GPDMA_CCONFIG_L_SHIFT (16)
+#define GPDMA_CCONFIG_L_MASK (0x1 << GPDMA_CCONFIG_L_SHIFT)
+#define GPDMA_CCONFIG_L(x) ((x) << GPDMA_CCONFIG_L_SHIFT)
+
+#define GPDMA_CCONFIG_A_SHIFT (17)
+#define GPDMA_CCONFIG_A_MASK (0x1 << GPDMA_CCONFIG_A_SHIFT)
+#define GPDMA_CCONFIG_A(x) ((x) << GPDMA_CCONFIG_A_SHIFT)
+
+#define GPDMA_CCONFIG_H_SHIFT (18)
+#define GPDMA_CCONFIG_H_MASK (0x1 << GPDMA_CCONFIG_H_SHIFT)
+#define GPDMA_CCONFIG_H(x) ((x) << GPDMA_CCONFIG_H_SHIFT)
+
+/* --- AUTO-GENERATED STUFF FOLLOWS ----------------------------- */
+
+/* --- GPDMA_NTSTAT values -------------------------------------- */
+
+/* INTSTAT: Status of DMA channel interrupts after masking */
+#define GPDMA_NTSTAT_INTSTAT_SHIFT (0)
+#define GPDMA_NTSTAT_INTSTAT_MASK (0xff << GPDMA_NTSTAT_INTSTAT_SHIFT)
+#define GPDMA_NTSTAT_INTSTAT(x) ((x) << GPDMA_NTSTAT_INTSTAT_SHIFT)
+
+/* --- GPDMA_INTTCSTAT values ----------------------------------- */
+
+/* INTTCSTAT: Terminal count interrupt request status for DMA channels */
+#define GPDMA_INTTCSTAT_INTTCSTAT_SHIFT (0)
+#define GPDMA_INTTCSTAT_INTTCSTAT_MASK (0xff << GPDMA_INTTCSTAT_INTTCSTAT_SHIFT)
+#define GPDMA_INTTCSTAT_INTTCSTAT(x) ((x) << GPDMA_INTTCSTAT_INTTCSTAT_SHIFT)
+
+/* --- GPDMA_INTTCCLEAR values ---------------------------------- */
+
+/* INTTCCLEAR: Allows clearing the Terminal count interrupt request (IntTCStat)
+ for DMA channels */
+#define GPDMA_INTTCCLEAR_INTTCCLEAR_SHIFT (0)
+#define GPDMA_INTTCCLEAR_INTTCCLEAR_MASK \
+ (0xff << GPDMA_INTTCCLEAR_INTTCCLEAR_SHIFT)
+#define GPDMA_INTTCCLEAR_INTTCCLEAR(x) \
+ ((x) << GPDMA_INTTCCLEAR_INTTCCLEAR_SHIFT)
+
+/* --- GPDMA_INTERRSTAT values ---------------------------------- */
+
+/* INTERRSTAT: Interrupt error status for DMA channels */
+#define GPDMA_INTERRSTAT_INTERRSTAT_SHIFT (0)
+#define GPDMA_INTERRSTAT_INTERRSTAT_MASK \
+ (0xff << GPDMA_INTERRSTAT_INTERRSTAT_SHIFT)
+#define GPDMA_INTERRSTAT_INTERRSTAT(x) \
+ ((x) << GPDMA_INTERRSTAT_INTERRSTAT_SHIFT)
+
+/* --- GPDMA_INTERRCLR values ----------------------------------- */
+
+/* INTERRCLR: Writing a 1 clears the error interrupt request (IntErrStat)
+ for DMA channels */
+#define GPDMA_INTERRCLR_INTERRCLR_SHIFT (0)
+#define GPDMA_INTERRCLR_INTERRCLR_MASK \
+ (0xff << GPDMA_INTERRCLR_INTERRCLR_SHIFT)
+#define GPDMA_INTERRCLR_INTERRCLR(x) \
+ ((x) << GPDMA_INTERRCLR_INTERRCLR_SHIFT)
+
+/* --- GPDMA_RAWINTTCSTAT values -------------------------------- */
+
+/* RAWINTTCSTAT: Status of the terminal count interrupt for DMA channels
+ prior to masking */
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT_SHIFT (0)
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT_MASK \
+ (0xff << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT_SHIFT)
+#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT(x) \
+ ((x) << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT_SHIFT)
+
+/* --- GPDMA_RAWINTERRSTAT values ------------------------------- */
+
+/* RAWINTERRSTAT: Status of the error interrupt for DMA channels prior to
+ masking */
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT_SHIFT (0)
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT_MASK \
+ (0xff << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT_SHIFT)
+#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT(x) \
+ ((x) << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT_SHIFT)
+
+/* --- GPDMA_ENBLDCHNS values ----------------------------------- */
+
+/* ENABLEDCHANNELS: Enable status for DMA channels */
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS_SHIFT (0)
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS_MASK \
+ (0xff << GPDMA_ENBLDCHNS_ENABLEDCHANNELS_SHIFT)
+#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS(x) \
+ ((x) << GPDMA_ENBLDCHNS_ENABLEDCHANNELS_SHIFT)
+
+/* --- GPDMA_SOFTBREQ values ------------------------------------ */
+
+/* SOFTBREQ: Software burst request flags for each of 16 possible sources */
+#define GPDMA_SOFTBREQ_SOFTBREQ_SHIFT (0)
+#define GPDMA_SOFTBREQ_SOFTBREQ_MASK (0xffff << GPDMA_SOFTBREQ_SOFTBREQ_SHIFT)
+#define GPDMA_SOFTBREQ_SOFTBREQ(x) ((x) << GPDMA_SOFTBREQ_SOFTBREQ_SHIFT)
+
+/* --- GPDMA_SOFTSREQ values ------------------------------------ */
+
+/* SOFTSREQ: Software single transfer request flags for each of 16 possible
+ sources */
+#define GPDMA_SOFTSREQ_SOFTSREQ_SHIFT (0)
+#define GPDMA_SOFTSREQ_SOFTSREQ_MASK (0xffff << GPDMA_SOFTSREQ_SOFTSREQ_SHIFT)
+#define GPDMA_SOFTSREQ_SOFTSREQ(x) ((x) << GPDMA_SOFTSREQ_SOFTSREQ_SHIFT)
+
+/* --- GPDMA_SOFTLBREQ values ----------------------------------- */
+
+/* SOFTLBREQ: Software last burst request flags for each of 16 possible
+ sources */
+#define GPDMA_SOFTLBREQ_SOFTLBREQ_SHIFT (0)
+#define GPDMA_SOFTLBREQ_SOFTLBREQ_MASK \
+ (0xffff << GPDMA_SOFTLBREQ_SOFTLBREQ_SHIFT)
+#define GPDMA_SOFTLBREQ_SOFTLBREQ(x) \
+ ((x) << GPDMA_SOFTLBREQ_SOFTLBREQ_SHIFT)
+
+/* --- GPDMA_SOFTLSREQ values ----------------------------------- */
+
+/* SOFTLSREQ: Software last single transfer request flags for each of 16
+ possible sources */
+#define GPDMA_SOFTLSREQ_SOFTLSREQ_SHIFT (0)
+#define GPDMA_SOFTLSREQ_SOFTLSREQ_MASK \
+ (0xffff << GPDMA_SOFTLSREQ_SOFTLSREQ_SHIFT)
+#define GPDMA_SOFTLSREQ_SOFTLSREQ(x) \
+ ((x) << GPDMA_SOFTLSREQ_SOFTLSREQ_SHIFT)
+
+/* --- GPDMA_CONFIG values -------------------------------------- */
+
+/* E: DMA Controller enable */
+#define GPDMA_CONFIG_E_SHIFT (0)
+#define GPDMA_CONFIG_E_MASK (0x1 << GPDMA_CONFIG_E_SHIFT)
+#define GPDMA_CONFIG_E(x) ((x) << GPDMA_CONFIG_E_SHIFT)
+
+/* M0: AHB Master 0 endianness configuration */
+#define GPDMA_CONFIG_M0_SHIFT (1)
+#define GPDMA_CONFIG_M0_MASK (0x1 << GPDMA_CONFIG_M0_SHIFT)
+#define GPDMA_CONFIG_M0(x) ((x) << GPDMA_CONFIG_M0_SHIFT)
+
+/* M1: AHB Master 1 endianness configuration */
+#define GPDMA_CONFIG_M1_SHIFT (2)
+#define GPDMA_CONFIG_M1_MASK (0x1 << GPDMA_CONFIG_M1_SHIFT)
+#define GPDMA_CONFIG_M1(x) ((x) << GPDMA_CONFIG_M1_SHIFT)
+
+/* --- GPDMA_SYNC values ---------------------------------------- */
+
+/* DMACSYNC: Controls the synchronization logic for DMA request signals */
+#define GPDMA_SYNC_DMACSYNC_SHIFT (0)
+#define GPDMA_SYNC_DMACSYNC_MASK (0xffff << GPDMA_SYNC_DMACSYNC_SHIFT)
+#define GPDMA_SYNC_DMACSYNC(x) ((x) << GPDMA_SYNC_DMACSYNC_SHIFT)
+
+/* --- GPDMA_C[0..7]SRCADDR values ----------------------------------- */
+
+/* SRCADDR: DMA source address */
+#define GPDMA_CxSRCADDR_SRCADDR_SHIFT (0)
+#define GPDMA_CxSRCADDR_SRCADDR_MASK \
+ (0xffffffff << GPDMA_CxSRCADDR_SRCADDR_SHIFT)
+#define GPDMA_CxSRCADDR_SRCADDR(x) ((x) << GPDMA_CxSRCADDR_SRCADDR_SHIFT)
+
+/* --- GPDMA_C[0..7]DESTADDR values ---------------------------------- */
+
+/* DESTADDR: DMA source address */
+#define GPDMA_CxDESTADDR_DESTADDR_SHIFT (0)
+#define GPDMA_CxDESTADDR_DESTADDR_MASK \
+ (0xffffffff << GPDMA_CxDESTADDR_DESTADDR_SHIFT)
+#define GPDMA_CxDESTADDR_DESTADDR(x) ((x) << GPDMA_CxDESTADDR_DESTADDR_SHIFT)
+
+/* --- GPDMA_C[0..7]LLI values --------------------------------------- */
+
+/* LM: AHB master select for loading the next LLI */
+#define GPDMA_CxLLI_LM_SHIFT (0)
+#define GPDMA_CxLLI_LM_MASK (0x1 << GPDMA_CxLLI_LM_SHIFT)
+#define GPDMA_CxLLI_LM(x) ((x) << GPDMA_CxLLI_LM_SHIFT)
+
+/* LLI: Linked list item */
+#define GPDMA_CxLLI_LLI_SHIFT (2)
+#define GPDMA_CxLLI_LLI_MASK (0x3fffffff << GPDMA_CxLLI_LLI_SHIFT)
+#define GPDMA_CxLLI_LLI(x) ((x) << GPDMA_CxLLI_LLI_SHIFT)
+
+/* --- GPDMA_C[0..7]CONTROL values ----------------------------------- */
+
+/* TRANSFERSIZE: Transfer size in number of transfers */
+#define GPDMA_CxCONTROL_TRANSFERSIZE_SHIFT (0)
+#define GPDMA_CxCONTROL_TRANSFERSIZE_MASK \
+ (0xfff << GPDMA_CxCONTROL_TRANSFERSIZE_SHIFT)
+#define GPDMA_CxCONTROL_TRANSFERSIZE(x) \
+ ((x) << GPDMA_CxCONTROL_TRANSFERSIZE_SHIFT)
+
+/* SBSIZE: Source burst size */
+#define GPDMA_CxCONTROL_SBSIZE_SHIFT (12)
+#define GPDMA_CxCONTROL_SBSIZE_MASK (0x7 << GPDMA_CxCONTROL_SBSIZE_SHIFT)
+#define GPDMA_CxCONTROL_SBSIZE(x) ((x) << GPDMA_CxCONTROL_SBSIZE_SHIFT)
+
+/* DBSIZE: Destination burst size */
+#define GPDMA_CxCONTROL_DBSIZE_SHIFT (15)
+#define GPDMA_CxCONTROL_DBSIZE_MASK (0x7 << GPDMA_CxCONTROL_DBSIZE_SHIFT)
+#define GPDMA_CxCONTROL_DBSIZE(x) ((x) << GPDMA_CxCONTROL_DBSIZE_SHIFT)
+
+/* SWIDTH: Source transfer width */
+#define GPDMA_CxCONTROL_SWIDTH_SHIFT (18)
+#define GPDMA_CxCONTROL_SWIDTH_MASK (0x7 << GPDMA_CxCONTROL_SWIDTH_SHIFT)
+#define GPDMA_CxCONTROL_SWIDTH(x) ((x) << GPDMA_CxCONTROL_SWIDTH_SHIFT)
+
+/* DWIDTH: Destination transfer width */
+#define GPDMA_CxCONTROL_DWIDTH_SHIFT (21)
+#define GPDMA_CxCONTROL_DWIDTH_MASK (0x7 << GPDMA_CxCONTROL_DWIDTH_SHIFT)
+#define GPDMA_CxCONTROL_DWIDTH(x) ((x) << GPDMA_CxCONTROL_DWIDTH_SHIFT)
+
+/* S: Source AHB master select */
+#define GPDMA_CxCONTROL_S_SHIFT (24)
+#define GPDMA_CxCONTROL_S_MASK (0x1 << GPDMA_CxCONTROL_S_SHIFT)
+#define GPDMA_CxCONTROL_S(x) ((x) << GPDMA_CxCONTROL_S_SHIFT)
+
+/* D: Destination AHB master select */
+#define GPDMA_CxCONTROL_D_SHIFT (25)
+#define GPDMA_CxCONTROL_D_MASK (0x1 << GPDMA_CxCONTROL_D_SHIFT)
+#define GPDMA_CxCONTROL_D(x) ((x) << GPDMA_CxCONTROL_D_SHIFT)
+
+/* SI: Source increment */
+#define GPDMA_CxCONTROL_SI_SHIFT (26)
+#define GPDMA_CxCONTROL_SI_MASK (0x1 << GPDMA_CxCONTROL_SI_SHIFT)
+#define GPDMA_Cx0CONTROL_SI(x) ((x) << GPDMA_CxCONTROL_SI_SHIFT)
+
+/* DI: Destination increment */
+#define GPDMA_CxCONTROL_DI_SHIFT (27)
+#define GPDMA_CxCONTROL_DI_MASK (0x1 << GPDMA_CxCONTROL_DI_SHIFT)
+#define GPDMA_CxCONTROL_DI(x) ((x) << GPDMA_CxCONTROL_DI_SHIFT)
+
+/* PROT1: This information is provided to the peripheral during a DMA bus
+ access and indicates that the access is in user mode or privileged mode */
+#define GPDMA_CxCONTROL_PROT1_SHIFT (28)
+#define GPDMA_CxCONTROL_PROT1_MASK (0x1 << GPDMA_CxCONTROL_PROT1_SHIFT)
+#define GPDMA_CxCONTROL_PROT1(x) ((x) << GPDMA_CxCONTROL_PROT1_SHIFT)
+
+/* PROT2: This information is provided to the peripheral during a DMA bus
+ access and indicates to the peripheral that the access is bufferable or not
+ bufferable */
+#define GPDMA_CxCONTROL_PROT2_SHIFT (29)
+#define GPDMA_CxCONTROL_PROT2_MASK (0x1 << GPDMA_CxCONTROL_PROT2_SHIFT)
+#define GPDMA_CxCONTROL_PROT2(x) ((x) << GPDMA_CxCONTROL_PROT2_SHIFT)
+
+/* PROT3: This information is provided to the peripheral during a DMA bus
+ access and indicates to the peripheral that the access is cacheable or not
+ cacheable */
+#define GPDMA_CxCONTROL_PROT3_SHIFT (30)
+#define GPDMA_CxCONTROL_PROT3_MASK (0x1 << GPDMA_CxCONTROL_PROT3_SHIFT)
+#define GPDMA_CxCONTROL_PROT3(x) ((x) << GPDMA_CxCONTROL_PROT3_SHIFT)
+
+/* I: Terminal count interrupt enable bit */
+#define GPDMA_CxCONTROL_I_SHIFT (31)
+#define GPDMA_CxCONTROL_I_MASK (0x1 << GPDMA_CxCONTROL_I_SHIFT)
+#define GPDMA_CxCONTROL_I(x) ((x) << GPDMA_CxCONTROL_I_SHIFT)
+
+/* --- GPDMA_C[0..7]CONFIG values ------------------------------------ */
+
+/* E: Channel enable */
+#define GPDMA_CxCONFIG_E_SHIFT (0)
+#define GPDMA_CxCONFIG_E_MASK (0x1 << GPDMA_CxCONFIG_E_SHIFT)
+#define GPDMA_CxCONFIG_E(x) ((x) << GPDMA_CxCONFIG_E_SHIFT)
+
+/* SRCPERIPHERAL: Source peripheral */
+#define GPDMA_CxCONFIG_SRCPERIPHERAL_SHIFT (1)
+#define GPDMA_CxCONFIG_SRCPERIPHERAL_MASK \
+ (0x1f << GPDMA_CxCONFIG_SRCPERIPHERAL_SHIFT)
+#define GPDMA_CxCONFIG_SRCPERIPHERAL(x) \
+ ((x) << GPDMA_CxCONFIG_SRCPERIPHERAL_SHIFT)
+
+/* DESTPERIPHERAL: Destination peripheral */
+#define GPDMA_CxCONFIG_DESTPERIPHERAL_SHIFT (6)
+#define GPDMA_CxCONFIG_DESTPERIPHERAL_MASK \
+ (0x1f << GPDMA_CxCONFIG_DESTPERIPHERAL_SHIFT)
+#define GPDMA_CxCONFIG_DESTPERIPHERAL(x) \
+ ((x) << GPDMA_CxCONFIG_DESTPERIPHERAL_SHIFT)
+
+/* FLOWCNTRL: Flow control and transfer type */
+#define GPDMA_CxCONFIG_FLOWCNTRL_SHIFT (11)
+#define GPDMA_CxCONFIG_FLOWCNTRL_MASK (0x7 << GPDMA_CxCONFIG_FLOWCNTRL_SHIFT)
+#define GPDMA_CxCONFIG_FLOWCNTRL(x) ((x) << GPDMA_CxCONFIG_FLOWCNTRL_SHIFT)
+
+/* IE: Interrupt error mask */
+#define GPDMA_CxCONFIG_IE_SHIFT (14)
+#define GPDMA_CxCONFIG_IE_MASK (0x1 << GPDMA_CxCONFIG_IE_SHIFT)
+#define GPDMA_CxCONFIG_IE(x) ((x) << GPDMA_CxCONFIG_IE_SHIFT)
+
+/* ITC: Terminal count interrupt mask */
+#define GPDMA_CxCONFIG_ITC_SHIFT (15)
+#define GPDMA_CxCONFIG_ITC_MASK (0x1 << GPDMA_CxCONFIG_ITC_SHIFT)
+#define GPDMA_CxCONFIG_ITC(x) ((x) << GPDMA_CxCONFIG_ITC_SHIFT)
+
+/* L: Lock */
+#define GPDMA_CxCONFIG_L_SHIFT (16)
+#define GPDMA_CxCONFIG_L_MASK (0x1 << GPDMA_CxCONFIG_L_SHIFT)
+#define GPDMA_CxCONFIG_L(x) ((x) << GPDMA_CxCONFIG_L_SHIFT)
+
+/* A: Active */
+#define GPDMA_CxCONFIG_A_SHIFT (17)
+#define GPDMA_CxCONFIG_A_MASK (0x1 << GPDMA_CxCONFIG_A_SHIFT)
+#define GPDMA_CxCONFIG_A(x) ((x) << GPDMA_CxCONFIG_A_SHIFT)
+
+/* H: Halt */
+#define GPDMA_CxCONFIG_H_SHIFT (18)
+#define GPDMA_CxCONFIG_H_MASK (0x1 << GPDMA_CxCONFIG_H_SHIFT)
+#define GPDMA_CxCONFIG_H(x) ((x) << GPDMA_CxCONFIG_H_SHIFT)
+
+/**@}*/
+
+#endif
diff --git a/libopencm3/include/libopencm3/lpc43xx/gpio.h b/libopencm3/include/libopencm3/lpc43xx/gpio.h
new file mode 100644
index 0000000..6747470
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc43xx/gpio.h
@@ -0,0 +1,784 @@
+/** @defgroup gpio_defines General Purpose I/O Defines
+
+@brief Defined Constants and Types for the LPC43xx General Purpose I/O
+
+@ingroup LPC43xx_defines
+
+@version 1.0.0
+
+@author @htmlonly © @endhtmlonly 2012 Michael Ossmann
+
+@date 10 March 2013
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Uwe Hermann
+ * Copyright (C) 2012 Michael Ossmann
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LPC43XX_GPIO_H
+#define LPC43XX_GPIO_H
+
+/**@{*/
+
+#include
+#include
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* GPIO port base addresses (for convenience) */
+#define GPIO0 (GPIO_PORT_BASE + 0x2000)
+#define GPIO1 (GPIO_PORT_BASE + 0x2004)
+#define GPIO2 (GPIO_PORT_BASE + 0x2008)
+#define GPIO3 (GPIO_PORT_BASE + 0x200C)
+#define GPIO4 (GPIO_PORT_BASE + 0x2010)
+#define GPIO5 (GPIO_PORT_BASE + 0x2014)
+#define GPIO6 (GPIO_PORT_BASE + 0x2018)
+#define GPIO7 (GPIO_PORT_BASE + 0x201C)
+
+/* GPIO number definitions (for convenience) */
+#define GPIOPIN0 (1 << 0)
+#define GPIOPIN1 (1 << 1)
+#define GPIOPIN2 (1 << 2)
+#define GPIOPIN3 (1 << 3)
+#define GPIOPIN4 (1 << 4)
+#define GPIOPIN5 (1 << 5)
+#define GPIOPIN6 (1 << 6)
+#define GPIOPIN7 (1 << 7)
+#define GPIOPIN8 (1 << 8)
+#define GPIOPIN9 (1 << 9)
+#define GPIOPIN10 (1 << 10)
+#define GPIOPIN11 (1 << 11)
+#define GPIOPIN12 (1 << 12)
+#define GPIOPIN13 (1 << 13)
+#define GPIOPIN14 (1 << 14)
+#define GPIOPIN15 (1 << 15)
+#define GPIOPIN16 (1 << 16)
+#define GPIOPIN17 (1 << 17)
+#define GPIOPIN18 (1 << 18)
+#define GPIOPIN19 (1 << 19)
+#define GPIOPIN20 (1 << 20)
+#define GPIOPIN21 (1 << 21)
+#define GPIOPIN22 (1 << 22)
+#define GPIOPIN23 (1 << 23)
+#define GPIOPIN24 (1 << 24)
+#define GPIOPIN25 (1 << 25)
+#define GPIOPIN26 (1 << 26)
+#define GPIOPIN27 (1 << 27)
+#define GPIOPIN28 (1 << 28)
+#define GPIOPIN29 (1 << 29)
+#define GPIOPIN30 (1 << 30)
+#define GPIOPIN31 (1 << 31)
+
+/* --- GPIO registers ------------------------------------------------------ */
+
+/* GPIO pin interrupts */
+
+/* Pin Interrupt Mode register */
+#define GPIO_PIN_INTERRUPT_ISEL MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x000)
+
+/* Pin interrupt level (rising edge) interrupt enable register */
+#define GPIO_PIN_INTERRUPT_IENR MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x004)
+
+/* Pin interrupt level (rising edge) interrupt set register */
+#define GPIO_PIN_INTERRUPT_SIENR MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x008)
+
+/* Pin interrupt level (rising edge interrupt) clear register */
+#define GPIO_PIN_INTERRUPT_CIENR MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x00C)
+
+/* Pin interrupt active level (falling edge) interrupt enable register */
+#define GPIO_PIN_INTERRUPT_IENF MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x010)
+
+/* Pin interrupt active level (falling edge) interrupt set register */
+#define GPIO_PIN_INTERRUPT_SIENF MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x014)
+
+/* Pin interrupt active level (falling edge) interrupt clear register */
+#define GPIO_PIN_INTERRUPT_CIENF MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x018)
+
+/* Pin interrupt rising edge register */
+#define GPIO_PIN_INTERRUPT_RISE MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x01C)
+
+/* Pin interrupt falling edge register */
+#define GPIO_PIN_INTERRUPT_FALL MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x020)
+
+/* Pin interrupt status register */
+#define GPIO_PIN_INTERRUPT_IST MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x024)
+
+/* GPIO GROUP0 interrupt */
+
+/* GPIO grouped interrupt control register */
+#define GPIO_GROUP0_INTERRUPT_CTRL \
+ MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x000)
+
+/* GPIO grouped interrupt port [0..7] polarity register */
+#define GPIO_GROUP0_INTERRUPT_PORT_POL(x) \
+ MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x020 + ((x)*4))
+
+/* GPIO grouped interrupt port [0..7] enable register */
+#define GPIO_GROUP0_INTERRUPT_PORT_ENA(x) \
+ MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x040 + ((x)*4))
+
+/* GPIO GROUP1 interrupt */
+
+/* GPIO grouped interrupt control register */
+#define GPIO_GROUP1_INTERRUPT_CTRL \
+ MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x000)
+
+/* GPIO grouped interrupt port [0..7] polarity register */
+#define GPIO_GROUP1_INTERRUPT_PORT_POL(x) \
+ MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x020 + ((x)*4))
+
+/* GPIO grouped interrupt port [0..7] enable register */
+#define GPIO_GROUP1_INTERRUPT_PORT_ENA(x) \
+ MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x040 + ((x)*4))
+
+/* Byte pin registers port 0; pins PIO0_0 to PIO0_31 (R/W) */
+#define GPIO_B0 (GPIO_PORT_BASE + 0x0000)
+#define GPIO_B1 (GPIO_PORT_BASE + 0x0001)
+#define GPIO_B2 (GPIO_PORT_BASE + 0x0002)
+#define GPIO_B3 (GPIO_PORT_BASE + 0x0003)
+#define GPIO_B4 (GPIO_PORT_BASE + 0x0004)
+#define GPIO_B5 (GPIO_PORT_BASE + 0x0005)
+#define GPIO_B6 (GPIO_PORT_BASE + 0x0006)
+#define GPIO_B7 (GPIO_PORT_BASE + 0x0007)
+#define GPIO_B8 (GPIO_PORT_BASE + 0x0008)
+#define GPIO_B9 (GPIO_PORT_BASE + 0x0009)
+#define GPIO_B10 (GPIO_PORT_BASE + 0x000A)
+#define GPIO_B11 (GPIO_PORT_BASE + 0x000B)
+#define GPIO_B12 (GPIO_PORT_BASE + 0x000C)
+#define GPIO_B13 (GPIO_PORT_BASE + 0x000D)
+#define GPIO_B14 (GPIO_PORT_BASE + 0x000E)
+#define GPIO_B15 (GPIO_PORT_BASE + 0x000F)
+#define GPIO_B16 (GPIO_PORT_BASE + 0x0010)
+#define GPIO_B17 (GPIO_PORT_BASE + 0x0011)
+#define GPIO_B18 (GPIO_PORT_BASE + 0x0012)
+#define GPIO_B19 (GPIO_PORT_BASE + 0x0013)
+#define GPIO_B20 (GPIO_PORT_BASE + 0x0014)
+#define GPIO_B21 (GPIO_PORT_BASE + 0x0015)
+#define GPIO_B22 (GPIO_PORT_BASE + 0x0016)
+#define GPIO_B23 (GPIO_PORT_BASE + 0x0017)
+#define GPIO_B24 (GPIO_PORT_BASE + 0x0018)
+#define GPIO_B25 (GPIO_PORT_BASE + 0x0019)
+#define GPIO_B26 (GPIO_PORT_BASE + 0x001A)
+#define GPIO_B27 (GPIO_PORT_BASE + 0x001B)
+#define GPIO_B28 (GPIO_PORT_BASE + 0x001C)
+#define GPIO_B29 (GPIO_PORT_BASE + 0x001D)
+#define GPIO_B30 (GPIO_PORT_BASE + 0x001E)
+#define GPIO_B31 (GPIO_PORT_BASE + 0x001F)
+
+/* Byte pin registers port 1 (R/W) */
+#define GPIO_B32 (GPIO_PORT_BASE + 0x0020)
+#define GPIO_B33 (GPIO_PORT_BASE + 0x0021)
+#define GPIO_B34 (GPIO_PORT_BASE + 0x0022)
+#define GPIO_B35 (GPIO_PORT_BASE + 0x0023)
+#define GPIO_B36 (GPIO_PORT_BASE + 0x0024)
+#define GPIO_B37 (GPIO_PORT_BASE + 0x0025)
+#define GPIO_B38 (GPIO_PORT_BASE + 0x0026)
+#define GPIO_B39 (GPIO_PORT_BASE + 0x0027)
+#define GPIO_B40 (GPIO_PORT_BASE + 0x0028)
+#define GPIO_B41 (GPIO_PORT_BASE + 0x0029)
+#define GPIO_B42 (GPIO_PORT_BASE + 0x002A)
+#define GPIO_B43 (GPIO_PORT_BASE + 0x002B)
+#define GPIO_B44 (GPIO_PORT_BASE + 0x002C)
+#define GPIO_B45 (GPIO_PORT_BASE + 0x002D)
+#define GPIO_B46 (GPIO_PORT_BASE + 0x002E)
+#define GPIO_B47 (GPIO_PORT_BASE + 0x002F)
+#define GPIO_B48 (GPIO_PORT_BASE + 0x0030)
+#define GPIO_B49 (GPIO_PORT_BASE + 0x0031)
+#define GPIO_B50 (GPIO_PORT_BASE + 0x0032)
+#define GPIO_B51 (GPIO_PORT_BASE + 0x0033)
+#define GPIO_B52 (GPIO_PORT_BASE + 0x0034)
+#define GPIO_B53 (GPIO_PORT_BASE + 0x0035)
+#define GPIO_B54 (GPIO_PORT_BASE + 0x0036)
+#define GPIO_B55 (GPIO_PORT_BASE + 0x0037)
+#define GPIO_B56 (GPIO_PORT_BASE + 0x0038)
+#define GPIO_B57 (GPIO_PORT_BASE + 0x0039)
+#define GPIO_B58 (GPIO_PORT_BASE + 0x003A)
+#define GPIO_B59 (GPIO_PORT_BASE + 0x003B)
+#define GPIO_B60 (GPIO_PORT_BASE + 0x003C)
+#define GPIO_B61 (GPIO_PORT_BASE + 0x003D)
+#define GPIO_B62 (GPIO_PORT_BASE + 0x003E)
+#define GPIO_B63 (GPIO_PORT_BASE + 0x003F)
+
+/* Byte pin registers port 2 (R/W) */
+#define GPIO_B64 (GPIO_PORT_BASE + 0x0040)
+#define GPIO_B65 (GPIO_PORT_BASE + 0x0041)
+#define GPIO_B66 (GPIO_PORT_BASE + 0x0042)
+#define GPIO_B67 (GPIO_PORT_BASE + 0x0043)
+#define GPIO_B68 (GPIO_PORT_BASE + 0x0044)
+#define GPIO_B69 (GPIO_PORT_BASE + 0x0045)
+#define GPIO_B70 (GPIO_PORT_BASE + 0x0046)
+#define GPIO_B71 (GPIO_PORT_BASE + 0x0047)
+#define GPIO_B72 (GPIO_PORT_BASE + 0x0048)
+#define GPIO_B73 (GPIO_PORT_BASE + 0x0049)
+#define GPIO_B74 (GPIO_PORT_BASE + 0x004A)
+#define GPIO_B75 (GPIO_PORT_BASE + 0x004B)
+#define GPIO_B76 (GPIO_PORT_BASE + 0x004C)
+#define GPIO_B77 (GPIO_PORT_BASE + 0x004D)
+#define GPIO_B78 (GPIO_PORT_BASE + 0x004E)
+#define GPIO_B79 (GPIO_PORT_BASE + 0x004F)
+#define GPIO_B80 (GPIO_PORT_BASE + 0x0050)
+#define GPIO_B81 (GPIO_PORT_BASE + 0x0051)
+#define GPIO_B82 (GPIO_PORT_BASE + 0x0052)
+#define GPIO_B83 (GPIO_PORT_BASE + 0x0053)
+#define GPIO_B84 (GPIO_PORT_BASE + 0x0054)
+#define GPIO_B85 (GPIO_PORT_BASE + 0x0055)
+#define GPIO_B86 (GPIO_PORT_BASE + 0x0056)
+#define GPIO_B87 (GPIO_PORT_BASE + 0x0057)
+#define GPIO_B88 (GPIO_PORT_BASE + 0x0058)
+#define GPIO_B89 (GPIO_PORT_BASE + 0x0059)
+#define GPIO_B90 (GPIO_PORT_BASE + 0x005A)
+#define GPIO_B91 (GPIO_PORT_BASE + 0x005B)
+#define GPIO_B92 (GPIO_PORT_BASE + 0x005C)
+#define GPIO_B93 (GPIO_PORT_BASE + 0x005D)
+#define GPIO_B94 (GPIO_PORT_BASE + 0x005E)
+#define GPIO_B95 (GPIO_PORT_BASE + 0x005F)
+
+/* Byte pin registers port 3 (R/W) */
+#define GPIO_B96 (GPIO_PORT_BASE + 0x0060)
+#define GPIO_B97 (GPIO_PORT_BASE + 0x0061)
+#define GPIO_B98 (GPIO_PORT_BASE + 0x0062)
+#define GPIO_B99 (GPIO_PORT_BASE + 0x0063)
+#define GPIO_B100 (GPIO_PORT_BASE + 0x0064)
+#define GPIO_B101 (GPIO_PORT_BASE + 0x0065)
+#define GPIO_B102 (GPIO_PORT_BASE + 0x0066)
+#define GPIO_B103 (GPIO_PORT_BASE + 0x0067)
+#define GPIO_B104 (GPIO_PORT_BASE + 0x0068)
+#define GPIO_B105 (GPIO_PORT_BASE + 0x0069)
+#define GPIO_B106 (GPIO_PORT_BASE + 0x006A)
+#define GPIO_B107 (GPIO_PORT_BASE + 0x006B)
+#define GPIO_B108 (GPIO_PORT_BASE + 0x006C)
+#define GPIO_B109 (GPIO_PORT_BASE + 0x006D)
+#define GPIO_B110 (GPIO_PORT_BASE + 0x006E)
+#define GPIO_B111 (GPIO_PORT_BASE + 0x006F)
+#define GPIO_B112 (GPIO_PORT_BASE + 0x0070)
+#define GPIO_B113 (GPIO_PORT_BASE + 0x0071)
+#define GPIO_B114 (GPIO_PORT_BASE + 0x0072)
+#define GPIO_B115 (GPIO_PORT_BASE + 0x0073)
+#define GPIO_B116 (GPIO_PORT_BASE + 0x0074)
+#define GPIO_B117 (GPIO_PORT_BASE + 0x0075)
+#define GPIO_B118 (GPIO_PORT_BASE + 0x0076)
+#define GPIO_B119 (GPIO_PORT_BASE + 0x0077)
+#define GPIO_B120 (GPIO_PORT_BASE + 0x0078)
+#define GPIO_B121 (GPIO_PORT_BASE + 0x0079)
+#define GPIO_B122 (GPIO_PORT_BASE + 0x007A)
+#define GPIO_B123 (GPIO_PORT_BASE + 0x007B)
+#define GPIO_B124 (GPIO_PORT_BASE + 0x007C)
+#define GPIO_B125 (GPIO_PORT_BASE + 0x007D)
+#define GPIO_B126 (GPIO_PORT_BASE + 0x007E)
+#define GPIO_B127 (GPIO_PORT_BASE + 0x007F)
+
+/* Byte pin registers port 4 (R/W) */
+#define GPIO_B128 (GPIO_PORT_BASE + 0x0080)
+#define GPIO_B129 (GPIO_PORT_BASE + 0x0081)
+#define GPIO_B130 (GPIO_PORT_BASE + 0x0082)
+#define GPIO_B131 (GPIO_PORT_BASE + 0x0083)
+#define GPIO_B132 (GPIO_PORT_BASE + 0x0084)
+#define GPIO_B133 (GPIO_PORT_BASE + 0x0085)
+#define GPIO_B134 (GPIO_PORT_BASE + 0x0086)
+#define GPIO_B135 (GPIO_PORT_BASE + 0x0087)
+#define GPIO_B136 (GPIO_PORT_BASE + 0x0088)
+#define GPIO_B137 (GPIO_PORT_BASE + 0x0089)
+#define GPIO_B138 (GPIO_PORT_BASE + 0x008A)
+#define GPIO_B139 (GPIO_PORT_BASE + 0x008B)
+#define GPIO_B140 (GPIO_PORT_BASE + 0x008C)
+#define GPIO_B141 (GPIO_PORT_BASE + 0x008D)
+#define GPIO_B142 (GPIO_PORT_BASE + 0x008E)
+#define GPIO_B143 (GPIO_PORT_BASE + 0x008F)
+#define GPIO_B144 (GPIO_PORT_BASE + 0x0090)
+#define GPIO_B145 (GPIO_PORT_BASE + 0x0091)
+#define GPIO_B146 (GPIO_PORT_BASE + 0x0092)
+#define GPIO_B147 (GPIO_PORT_BASE + 0x0093)
+#define GPIO_B148 (GPIO_PORT_BASE + 0x0094)
+#define GPIO_B149 (GPIO_PORT_BASE + 0x0095)
+#define GPIO_B150 (GPIO_PORT_BASE + 0x0096)
+#define GPIO_B151 (GPIO_PORT_BASE + 0x0097)
+#define GPIO_B152 (GPIO_PORT_BASE + 0x0098)
+#define GPIO_B153 (GPIO_PORT_BASE + 0x0099)
+#define GPIO_B154 (GPIO_PORT_BASE + 0x009A)
+#define GPIO_B155 (GPIO_PORT_BASE + 0x009B)
+#define GPIO_B156 (GPIO_PORT_BASE + 0x009C)
+#define GPIO_B157 (GPIO_PORT_BASE + 0x009D)
+#define GPIO_B158 (GPIO_PORT_BASE + 0x009E)
+#define GPIO_B159 (GPIO_PORT_BASE + 0x009F)
+
+/* Byte pin registers port 5 (R/W) */
+#define GPIO_B160 (GPIO_PORT_BASE + 0x00A0)
+#define GPIO_B161 (GPIO_PORT_BASE + 0x00A1)
+#define GPIO_B162 (GPIO_PORT_BASE + 0x00A2)
+#define GPIO_B163 (GPIO_PORT_BASE + 0x00A3)
+#define GPIO_B164 (GPIO_PORT_BASE + 0x00A4)
+#define GPIO_B165 (GPIO_PORT_BASE + 0x00A5)
+#define GPIO_B166 (GPIO_PORT_BASE + 0x00A6)
+#define GPIO_B167 (GPIO_PORT_BASE + 0x00A7)
+#define GPIO_B168 (GPIO_PORT_BASE + 0x00A8)
+#define GPIO_B169 (GPIO_PORT_BASE + 0x00A9)
+#define GPIO_B170 (GPIO_PORT_BASE + 0x00AA)
+#define GPIO_B171 (GPIO_PORT_BASE + 0x00AB)
+#define GPIO_B172 (GPIO_PORT_BASE + 0x00AC)
+#define GPIO_B173 (GPIO_PORT_BASE + 0x00AD)
+#define GPIO_B174 (GPIO_PORT_BASE + 0x00AE)
+#define GPIO_B175 (GPIO_PORT_BASE + 0x00AF)
+#define GPIO_B176 (GPIO_PORT_BASE + 0x00B0)
+#define GPIO_B177 (GPIO_PORT_BASE + 0x00B1)
+#define GPIO_B178 (GPIO_PORT_BASE + 0x00B2)
+#define GPIO_B179 (GPIO_PORT_BASE + 0x00B3)
+#define GPIO_B180 (GPIO_PORT_BASE + 0x00B4)
+#define GPIO_B181 (GPIO_PORT_BASE + 0x00B5)
+#define GPIO_B182 (GPIO_PORT_BASE + 0x00B6)
+#define GPIO_B183 (GPIO_PORT_BASE + 0x00B7)
+#define GPIO_B184 (GPIO_PORT_BASE + 0x00B8)
+#define GPIO_B185 (GPIO_PORT_BASE + 0x00B9)
+#define GPIO_B186 (GPIO_PORT_BASE + 0x00BA)
+#define GPIO_B187 (GPIO_PORT_BASE + 0x00BB)
+#define GPIO_B188 (GPIO_PORT_BASE + 0x00BC)
+#define GPIO_B189 (GPIO_PORT_BASE + 0x00BD)
+#define GPIO_B190 (GPIO_PORT_BASE + 0x00BE)
+#define GPIO_B191 (GPIO_PORT_BASE + 0x00BF)
+
+/* Byte pin registers port 6 (R/W) */
+#define GPIO_B192 (GPIO_PORT_BASE + 0x00C0)
+#define GPIO_B193 (GPIO_PORT_BASE + 0x00C1)
+#define GPIO_B194 (GPIO_PORT_BASE + 0x00C2)
+#define GPIO_B195 (GPIO_PORT_BASE + 0x00C3)
+#define GPIO_B196 (GPIO_PORT_BASE + 0x00C4)
+#define GPIO_B197 (GPIO_PORT_BASE + 0x00C5)
+#define GPIO_B198 (GPIO_PORT_BASE + 0x00C6)
+#define GPIO_B199 (GPIO_PORT_BASE + 0x00C7)
+#define GPIO_B200 (GPIO_PORT_BASE + 0x00C8)
+#define GPIO_B201 (GPIO_PORT_BASE + 0x00C9)
+#define GPIO_B202 (GPIO_PORT_BASE + 0x00CA)
+#define GPIO_B203 (GPIO_PORT_BASE + 0x00CB)
+#define GPIO_B204 (GPIO_PORT_BASE + 0x00CC)
+#define GPIO_B205 (GPIO_PORT_BASE + 0x00CD)
+#define GPIO_B206 (GPIO_PORT_BASE + 0x00CE)
+#define GPIO_B207 (GPIO_PORT_BASE + 0x00CF)
+#define GPIO_B208 (GPIO_PORT_BASE + 0x00D0)
+#define GPIO_B209 (GPIO_PORT_BASE + 0x00D1)
+#define GPIO_B210 (GPIO_PORT_BASE + 0x00D2)
+#define GPIO_B211 (GPIO_PORT_BASE + 0x00D3)
+#define GPIO_B212 (GPIO_PORT_BASE + 0x00D4)
+#define GPIO_B213 (GPIO_PORT_BASE + 0x00D5)
+#define GPIO_B214 (GPIO_PORT_BASE + 0x00D6)
+#define GPIO_B215 (GPIO_PORT_BASE + 0x00D7)
+#define GPIO_B216 (GPIO_PORT_BASE + 0x00D8)
+#define GPIO_B217 (GPIO_PORT_BASE + 0x00D9)
+#define GPIO_B218 (GPIO_PORT_BASE + 0x00DA)
+#define GPIO_B219 (GPIO_PORT_BASE + 0x00DB)
+#define GPIO_B220 (GPIO_PORT_BASE + 0x00DC)
+#define GPIO_B221 (GPIO_PORT_BASE + 0x00DD)
+#define GPIO_B222 (GPIO_PORT_BASE + 0x00DE)
+#define GPIO_B223 (GPIO_PORT_BASE + 0x00DF)
+
+/* Byte pin registers port 7 (R/W) */
+#define GPIO_B224 (GPIO_PORT_BASE + 0x00E0)
+#define GPIO_B225 (GPIO_PORT_BASE + 0x00E1)
+#define GPIO_B226 (GPIO_PORT_BASE + 0x00E2)
+#define GPIO_B227 (GPIO_PORT_BASE + 0x00E3)
+#define GPIO_B228 (GPIO_PORT_BASE + 0x00E4)
+#define GPIO_B229 (GPIO_PORT_BASE + 0x00E5)
+#define GPIO_B230 (GPIO_PORT_BASE + 0x00E6)
+#define GPIO_B231 (GPIO_PORT_BASE + 0x00E7)
+#define GPIO_B232 (GPIO_PORT_BASE + 0x00E8)
+#define GPIO_B233 (GPIO_PORT_BASE + 0x00E9)
+#define GPIO_B234 (GPIO_PORT_BASE + 0x00EA)
+#define GPIO_B235 (GPIO_PORT_BASE + 0x00EB)
+#define GPIO_B236 (GPIO_PORT_BASE + 0x00EC)
+#define GPIO_B237 (GPIO_PORT_BASE + 0x00ED)
+#define GPIO_B238 (GPIO_PORT_BASE + 0x00EE)
+#define GPIO_B239 (GPIO_PORT_BASE + 0x00EF)
+#define GPIO_B240 (GPIO_PORT_BASE + 0x00F0)
+#define GPIO_B241 (GPIO_PORT_BASE + 0x00F1)
+#define GPIO_B242 (GPIO_PORT_BASE + 0x00F2)
+#define GPIO_B243 (GPIO_PORT_BASE + 0x00F3)
+#define GPIO_B244 (GPIO_PORT_BASE + 0x00F4)
+#define GPIO_B245 (GPIO_PORT_BASE + 0x00F5)
+#define GPIO_B246 (GPIO_PORT_BASE + 0x00F6)
+#define GPIO_B247 (GPIO_PORT_BASE + 0x00F7)
+#define GPIO_B248 (GPIO_PORT_BASE + 0x00F8)
+#define GPIO_B249 (GPIO_PORT_BASE + 0x00F9)
+#define GPIO_B250 (GPIO_PORT_BASE + 0x00FA)
+#define GPIO_B251 (GPIO_PORT_BASE + 0x00FB)
+#define GPIO_B252 (GPIO_PORT_BASE + 0x00FC)
+#define GPIO_B253 (GPIO_PORT_BASE + 0x00FD)
+#define GPIO_B254 (GPIO_PORT_BASE + 0x00FE)
+#define GPIO_B255 (GPIO_PORT_BASE + 0x00FF)
+
+/* Word pin registers port 0 (R/W) */
+#define GPIO_W0 (GPIO_PORT_BASE + 0x1000)
+#define GPIO_W1 (GPIO_PORT_BASE + 0x1004)
+#define GPIO_W2 (GPIO_PORT_BASE + 0x1008)
+#define GPIO_W3 (GPIO_PORT_BASE + 0x100C)
+#define GPIO_W4 (GPIO_PORT_BASE + 0x1010)
+#define GPIO_W5 (GPIO_PORT_BASE + 0x1014)
+#define GPIO_W6 (GPIO_PORT_BASE + 0x1018)
+#define GPIO_W7 (GPIO_PORT_BASE + 0x101C)
+#define GPIO_W8 (GPIO_PORT_BASE + 0x1020)
+#define GPIO_W9 (GPIO_PORT_BASE + 0x1024)
+#define GPIO_W10 (GPIO_PORT_BASE + 0x1028)
+#define GPIO_W11 (GPIO_PORT_BASE + 0x102C)
+#define GPIO_W12 (GPIO_PORT_BASE + 0x1030)
+#define GPIO_W13 (GPIO_PORT_BASE + 0x1034)
+#define GPIO_W14 (GPIO_PORT_BASE + 0x1038)
+#define GPIO_W15 (GPIO_PORT_BASE + 0x103C)
+#define GPIO_W16 (GPIO_PORT_BASE + 0x1040)
+#define GPIO_W17 (GPIO_PORT_BASE + 0x1044)
+#define GPIO_W18 (GPIO_PORT_BASE + 0x1048)
+#define GPIO_W19 (GPIO_PORT_BASE + 0x104C)
+#define GPIO_W20 (GPIO_PORT_BASE + 0x1050)
+#define GPIO_W21 (GPIO_PORT_BASE + 0x1054)
+#define GPIO_W22 (GPIO_PORT_BASE + 0x1058)
+#define GPIO_W23 (GPIO_PORT_BASE + 0x105C)
+#define GPIO_W24 (GPIO_PORT_BASE + 0x1060)
+#define GPIO_W25 (GPIO_PORT_BASE + 0x1064)
+#define GPIO_W26 (GPIO_PORT_BASE + 0x1068)
+#define GPIO_W27 (GPIO_PORT_BASE + 0x106C)
+#define GPIO_W28 (GPIO_PORT_BASE + 0x1070)
+#define GPIO_W29 (GPIO_PORT_BASE + 0x1074)
+#define GPIO_W30 (GPIO_PORT_BASE + 0x1078)
+#define GPIO_W31 (GPIO_PORT_BASE + 0x107C)
+
+/* Word pin registers port 1 (R/W) */
+#define GPIO_W32 (GPIO_PORT_BASE + 0x1080)
+#define GPIO_W33 (GPIO_PORT_BASE + 0x1084)
+#define GPIO_W34 (GPIO_PORT_BASE + 0x1088)
+#define GPIO_W35 (GPIO_PORT_BASE + 0x108C)
+#define GPIO_W36 (GPIO_PORT_BASE + 0x1090)
+#define GPIO_W37 (GPIO_PORT_BASE + 0x1094)
+#define GPIO_W38 (GPIO_PORT_BASE + 0x1098)
+#define GPIO_W39 (GPIO_PORT_BASE + 0x109C)
+#define GPIO_W40 (GPIO_PORT_BASE + 0x10A0)
+#define GPIO_W41 (GPIO_PORT_BASE + 0x10A4)
+#define GPIO_W42 (GPIO_PORT_BASE + 0x10A8)
+#define GPIO_W43 (GPIO_PORT_BASE + 0x10AC)
+#define GPIO_W44 (GPIO_PORT_BASE + 0x10B0)
+#define GPIO_W45 (GPIO_PORT_BASE + 0x10B4)
+#define GPIO_W46 (GPIO_PORT_BASE + 0x10B8)
+#define GPIO_W47 (GPIO_PORT_BASE + 0x10BC)
+#define GPIO_W48 (GPIO_PORT_BASE + 0x10C0)
+#define GPIO_W49 (GPIO_PORT_BASE + 0x10C4)
+#define GPIO_W50 (GPIO_PORT_BASE + 0x10C8)
+#define GPIO_W51 (GPIO_PORT_BASE + 0x10CC)
+#define GPIO_W52 (GPIO_PORT_BASE + 0x10D0)
+#define GPIO_W53 (GPIO_PORT_BASE + 0x10D4)
+#define GPIO_W54 (GPIO_PORT_BASE + 0x10D8)
+#define GPIO_W55 (GPIO_PORT_BASE + 0x10DC)
+#define GPIO_W56 (GPIO_PORT_BASE + 0x10E0)
+#define GPIO_W57 (GPIO_PORT_BASE + 0x10E4)
+#define GPIO_W58 (GPIO_PORT_BASE + 0x10E8)
+#define GPIO_W59 (GPIO_PORT_BASE + 0x10EC)
+#define GPIO_W60 (GPIO_PORT_BASE + 0x10F0)
+#define GPIO_W61 (GPIO_PORT_BASE + 0x10F4)
+#define GPIO_W62 (GPIO_PORT_BASE + 0x10F8)
+#define GPIO_W63 (GPIO_PORT_BASE + 0x10FC)
+
+/* Word pin registers port 2 (R/W) */
+#define GPIO_W64 (GPIO_PORT_BASE + 0x1100)
+#define GPIO_W65 (GPIO_PORT_BASE + 0x1104)
+#define GPIO_W66 (GPIO_PORT_BASE + 0x1108)
+#define GPIO_W67 (GPIO_PORT_BASE + 0x110C)
+#define GPIO_W68 (GPIO_PORT_BASE + 0x1110)
+#define GPIO_W69 (GPIO_PORT_BASE + 0x1114)
+#define GPIO_W70 (GPIO_PORT_BASE + 0x1118)
+#define GPIO_W71 (GPIO_PORT_BASE + 0x111C)
+#define GPIO_W72 (GPIO_PORT_BASE + 0x1120)
+#define GPIO_W73 (GPIO_PORT_BASE + 0x1124)
+#define GPIO_W74 (GPIO_PORT_BASE + 0x1128)
+#define GPIO_W75 (GPIO_PORT_BASE + 0x112C)
+#define GPIO_W76 (GPIO_PORT_BASE + 0x1130)
+#define GPIO_W77 (GPIO_PORT_BASE + 0x1134)
+#define GPIO_W78 (GPIO_PORT_BASE + 0x1138)
+#define GPIO_W79 (GPIO_PORT_BASE + 0x113C)
+#define GPIO_W80 (GPIO_PORT_BASE + 0x1140)
+#define GPIO_W81 (GPIO_PORT_BASE + 0x1144)
+#define GPIO_W82 (GPIO_PORT_BASE + 0x1148)
+#define GPIO_W83 (GPIO_PORT_BASE + 0x114C)
+#define GPIO_W84 (GPIO_PORT_BASE + 0x1150)
+#define GPIO_W85 (GPIO_PORT_BASE + 0x1154)
+#define GPIO_W86 (GPIO_PORT_BASE + 0x1158)
+#define GPIO_W87 (GPIO_PORT_BASE + 0x115C)
+#define GPIO_W88 (GPIO_PORT_BASE + 0x1160)
+#define GPIO_W89 (GPIO_PORT_BASE + 0x1164)
+#define GPIO_W90 (GPIO_PORT_BASE + 0x1168)
+#define GPIO_W91 (GPIO_PORT_BASE + 0x116C)
+#define GPIO_W92 (GPIO_PORT_BASE + 0x1170)
+#define GPIO_W93 (GPIO_PORT_BASE + 0x1174)
+#define GPIO_W94 (GPIO_PORT_BASE + 0x1178)
+#define GPIO_W95 (GPIO_PORT_BASE + 0x117C)
+
+/* Word pin registers port 3 (R/W) */
+#define GPIO_W96 (GPIO_PORT_BASE + 0x1180)
+#define GPIO_W97 (GPIO_PORT_BASE + 0x1184)
+#define GPIO_W98 (GPIO_PORT_BASE + 0x1188)
+#define GPIO_W99 (GPIO_PORT_BASE + 0x118C)
+#define GPIO_W100 (GPIO_PORT_BASE + 0x1190)
+#define GPIO_W101 (GPIO_PORT_BASE + 0x1194)
+#define GPIO_W102 (GPIO_PORT_BASE + 0x1198)
+#define GPIO_W103 (GPIO_PORT_BASE + 0x119C)
+#define GPIO_W104 (GPIO_PORT_BASE + 0x11A0)
+#define GPIO_W105 (GPIO_PORT_BASE + 0x11A4)
+#define GPIO_W106 (GPIO_PORT_BASE + 0x11A8)
+#define GPIO_W107 (GPIO_PORT_BASE + 0x11AC)
+#define GPIO_W108 (GPIO_PORT_BASE + 0x11B0)
+#define GPIO_W109 (GPIO_PORT_BASE + 0x11B4)
+#define GPIO_W110 (GPIO_PORT_BASE + 0x11B8)
+#define GPIO_W111 (GPIO_PORT_BASE + 0x11BC)
+#define GPIO_W112 (GPIO_PORT_BASE + 0x11C0)
+#define GPIO_W113 (GPIO_PORT_BASE + 0x11C4)
+#define GPIO_W114 (GPIO_PORT_BASE + 0x11C8)
+#define GPIO_W115 (GPIO_PORT_BASE + 0x11CC)
+#define GPIO_W116 (GPIO_PORT_BASE + 0x11D0)
+#define GPIO_W117 (GPIO_PORT_BASE + 0x11D4)
+#define GPIO_W118 (GPIO_PORT_BASE + 0x11D8)
+#define GPIO_W119 (GPIO_PORT_BASE + 0x11DC)
+#define GPIO_W120 (GPIO_PORT_BASE + 0x11E0)
+#define GPIO_W121 (GPIO_PORT_BASE + 0x11E4)
+#define GPIO_W122 (GPIO_PORT_BASE + 0x11E8)
+#define GPIO_W123 (GPIO_PORT_BASE + 0x11EC)
+#define GPIO_W124 (GPIO_PORT_BASE + 0x11F0)
+#define GPIO_W125 (GPIO_PORT_BASE + 0x11F4)
+#define GPIO_W126 (GPIO_PORT_BASE + 0x11F8)
+#define GPIO_W127 (GPIO_PORT_BASE + 0x11FC)
+
+/* Word pin registers port 4 (R/W) */
+#define GPIO_W128 (GPIO_PORT_BASE + 0x1200)
+#define GPIO_W129 (GPIO_PORT_BASE + 0x1204)
+#define GPIO_W130 (GPIO_PORT_BASE + 0x1208)
+#define GPIO_W131 (GPIO_PORT_BASE + 0x120C)
+#define GPIO_W132 (GPIO_PORT_BASE + 0x1210)
+#define GPIO_W133 (GPIO_PORT_BASE + 0x1214)
+#define GPIO_W134 (GPIO_PORT_BASE + 0x1218)
+#define GPIO_W135 (GPIO_PORT_BASE + 0x121C)
+#define GPIO_W136 (GPIO_PORT_BASE + 0x1220)
+#define GPIO_W137 (GPIO_PORT_BASE + 0x1224)
+#define GPIO_W138 (GPIO_PORT_BASE + 0x1228)
+#define GPIO_W139 (GPIO_PORT_BASE + 0x122C)
+#define GPIO_W140 (GPIO_PORT_BASE + 0x1230)
+#define GPIO_W141 (GPIO_PORT_BASE + 0x1234)
+#define GPIO_W142 (GPIO_PORT_BASE + 0x1238)
+#define GPIO_W143 (GPIO_PORT_BASE + 0x123C)
+#define GPIO_W144 (GPIO_PORT_BASE + 0x1240)
+#define GPIO_W145 (GPIO_PORT_BASE + 0x1244)
+#define GPIO_W146 (GPIO_PORT_BASE + 0x1248)
+#define GPIO_W147 (GPIO_PORT_BASE + 0x124C)
+#define GPIO_W148 (GPIO_PORT_BASE + 0x1250)
+#define GPIO_W149 (GPIO_PORT_BASE + 0x1254)
+#define GPIO_W150 (GPIO_PORT_BASE + 0x1258)
+#define GPIO_W151 (GPIO_PORT_BASE + 0x125C)
+#define GPIO_W152 (GPIO_PORT_BASE + 0x1260)
+#define GPIO_W153 (GPIO_PORT_BASE + 0x1264)
+#define GPIO_W154 (GPIO_PORT_BASE + 0x1268)
+#define GPIO_W155 (GPIO_PORT_BASE + 0x126C)
+#define GPIO_W156 (GPIO_PORT_BASE + 0x1270)
+#define GPIO_W157 (GPIO_PORT_BASE + 0x1274)
+#define GPIO_W158 (GPIO_PORT_BASE + 0x1278)
+#define GPIO_W159 (GPIO_PORT_BASE + 0x127C)
+
+/* Word pin registers port 5 (R/W) */
+#define GPIO_W160 (GPIO_PORT_BASE + 0x1280)
+#define GPIO_W161 (GPIO_PORT_BASE + 0x1284)
+#define GPIO_W162 (GPIO_PORT_BASE + 0x1288)
+#define GPIO_W163 (GPIO_PORT_BASE + 0x128C)
+#define GPIO_W164 (GPIO_PORT_BASE + 0x1290)
+#define GPIO_W165 (GPIO_PORT_BASE + 0x1294)
+#define GPIO_W166 (GPIO_PORT_BASE + 0x1298)
+#define GPIO_W167 (GPIO_PORT_BASE + 0x129C)
+#define GPIO_W168 (GPIO_PORT_BASE + 0x12A0)
+#define GPIO_W169 (GPIO_PORT_BASE + 0x12A4)
+#define GPIO_W170 (GPIO_PORT_BASE + 0x12A8)
+#define GPIO_W171 (GPIO_PORT_BASE + 0x12AC)
+#define GPIO_W172 (GPIO_PORT_BASE + 0x12B0)
+#define GPIO_W173 (GPIO_PORT_BASE + 0x12B4)
+#define GPIO_W174 (GPIO_PORT_BASE + 0x12B8)
+#define GPIO_W175 (GPIO_PORT_BASE + 0x12BC)
+#define GPIO_W176 (GPIO_PORT_BASE + 0x12C0)
+#define GPIO_W177 (GPIO_PORT_BASE + 0x12C4)
+#define GPIO_W178 (GPIO_PORT_BASE + 0x12C8)
+#define GPIO_W179 (GPIO_PORT_BASE + 0x12CC)
+#define GPIO_W180 (GPIO_PORT_BASE + 0x12D0)
+#define GPIO_W181 (GPIO_PORT_BASE + 0x12D4)
+#define GPIO_W182 (GPIO_PORT_BASE + 0x12D8)
+#define GPIO_W183 (GPIO_PORT_BASE + 0x12DC)
+#define GPIO_W184 (GPIO_PORT_BASE + 0x12E0)
+#define GPIO_W185 (GPIO_PORT_BASE + 0x12E4)
+#define GPIO_W186 (GPIO_PORT_BASE + 0x12E8)
+#define GPIO_W187 (GPIO_PORT_BASE + 0x12EC)
+#define GPIO_W188 (GPIO_PORT_BASE + 0x12F0)
+#define GPIO_W189 (GPIO_PORT_BASE + 0x12F4)
+#define GPIO_W190 (GPIO_PORT_BASE + 0x12F8)
+#define GPIO_W191 (GPIO_PORT_BASE + 0x12FC)
+
+/* Word pin registers port 6 (R/W) */
+#define GPIO_W192 (GPIO_PORT_BASE + 0x1300)
+#define GPIO_W193 (GPIO_PORT_BASE + 0x1304)
+#define GPIO_W194 (GPIO_PORT_BASE + 0x1308)
+#define GPIO_W195 (GPIO_PORT_BASE + 0x130C)
+#define GPIO_W196 (GPIO_PORT_BASE + 0x1310)
+#define GPIO_W197 (GPIO_PORT_BASE + 0x1314)
+#define GPIO_W198 (GPIO_PORT_BASE + 0x1318)
+#define GPIO_W199 (GPIO_PORT_BASE + 0x131C)
+#define GPIO_W200 (GPIO_PORT_BASE + 0x1320)
+#define GPIO_W201 (GPIO_PORT_BASE + 0x1324)
+#define GPIO_W202 (GPIO_PORT_BASE + 0x1328)
+#define GPIO_W203 (GPIO_PORT_BASE + 0x132C)
+#define GPIO_W204 (GPIO_PORT_BASE + 0x1330)
+#define GPIO_W205 (GPIO_PORT_BASE + 0x1334)
+#define GPIO_W206 (GPIO_PORT_BASE + 0x1338)
+#define GPIO_W207 (GPIO_PORT_BASE + 0x133C)
+#define GPIO_W208 (GPIO_PORT_BASE + 0x1340)
+#define GPIO_W209 (GPIO_PORT_BASE + 0x1344)
+#define GPIO_W210 (GPIO_PORT_BASE + 0x1348)
+#define GPIO_W211 (GPIO_PORT_BASE + 0x134C)
+#define GPIO_W212 (GPIO_PORT_BASE + 0x1350)
+#define GPIO_W213 (GPIO_PORT_BASE + 0x1354)
+#define GPIO_W214 (GPIO_PORT_BASE + 0x1358)
+#define GPIO_W215 (GPIO_PORT_BASE + 0x135C)
+#define GPIO_W216 (GPIO_PORT_BASE + 0x1360)
+#define GPIO_W217 (GPIO_PORT_BASE + 0x1364)
+#define GPIO_W218 (GPIO_PORT_BASE + 0x1368)
+#define GPIO_W219 (GPIO_PORT_BASE + 0x136C)
+#define GPIO_W220 (GPIO_PORT_BASE + 0x1370)
+#define GPIO_W221 (GPIO_PORT_BASE + 0x1374)
+#define GPIO_W222 (GPIO_PORT_BASE + 0x1378)
+#define GPIO_W223 (GPIO_PORT_BASE + 0x137C)
+
+/* Word pin registers port 7 (R/W) */
+#define GPIO_W224 (GPIO_PORT_BASE + 0x1380)
+#define GPIO_W225 (GPIO_PORT_BASE + 0x1384)
+#define GPIO_W226 (GPIO_PORT_BASE + 0x1388)
+#define GPIO_W227 (GPIO_PORT_BASE + 0x138C)
+#define GPIO_W228 (GPIO_PORT_BASE + 0x1390)
+#define GPIO_W229 (GPIO_PORT_BASE + 0x1394)
+#define GPIO_W230 (GPIO_PORT_BASE + 0x1398)
+#define GPIO_W231 (GPIO_PORT_BASE + 0x139C)
+#define GPIO_W232 (GPIO_PORT_BASE + 0x13A0)
+#define GPIO_W233 (GPIO_PORT_BASE + 0x13A4)
+#define GPIO_W234 (GPIO_PORT_BASE + 0x13A8)
+#define GPIO_W235 (GPIO_PORT_BASE + 0x13AC)
+#define GPIO_W236 (GPIO_PORT_BASE + 0x13B0)
+#define GPIO_W237 (GPIO_PORT_BASE + 0x13B4)
+#define GPIO_W238 (GPIO_PORT_BASE + 0x13B8)
+#define GPIO_W239 (GPIO_PORT_BASE + 0x13BC)
+#define GPIO_W240 (GPIO_PORT_BASE + 0x13C0)
+#define GPIO_W241 (GPIO_PORT_BASE + 0x13C4)
+#define GPIO_W242 (GPIO_PORT_BASE + 0x13C8)
+#define GPIO_W243 (GPIO_PORT_BASE + 0x13CC)
+#define GPIO_W244 (GPIO_PORT_BASE + 0x13D0)
+#define GPIO_W245 (GPIO_PORT_BASE + 0x13D4)
+#define GPIO_W246 (GPIO_PORT_BASE + 0x13D8)
+#define GPIO_W247 (GPIO_PORT_BASE + 0x13DC)
+#define GPIO_W248 (GPIO_PORT_BASE + 0x13E0)
+#define GPIO_W249 (GPIO_PORT_BASE + 0x13E4)
+#define GPIO_W250 (GPIO_PORT_BASE + 0x13E8)
+#define GPIO_W251 (GPIO_PORT_BASE + 0x13EC)
+#define GPIO_W252 (GPIO_PORT_BASE + 0x13F0)
+#define GPIO_W253 (GPIO_PORT_BASE + 0x13F4)
+#define GPIO_W254 (GPIO_PORT_BASE + 0x13F8)
+#define GPIO_W255 (GPIO_PORT_BASE + 0x13FC)
+
+/* GPIO data direction register (GPIOn_DIR) */
+#define GPIO_DIR(port) MMIO32(port + 0x00)
+#define GPIO0_DIR GPIO_DIR(GPIO0)
+#define GPIO1_DIR GPIO_DIR(GPIO1)
+#define GPIO2_DIR GPIO_DIR(GPIO2)
+#define GPIO3_DIR GPIO_DIR(GPIO3)
+#define GPIO4_DIR GPIO_DIR(GPIO4)
+#define GPIO5_DIR GPIO_DIR(GPIO5)
+#define GPIO6_DIR GPIO_DIR(GPIO6)
+#define GPIO7_DIR GPIO_DIR(GPIO7)
+
+/* GPIO fast mask register (GPIOn_MASK) */
+#define GPIO_MASK(port) MMIO32(port + 0x80)
+#define GPIO0_MASK GPIO_MASK(GPIO0)
+#define GPIO1_MASK GPIO_MASK(GPIO1)
+#define GPIO2_MASK GPIO_MASK(GPIO2)
+#define GPIO3_MASK GPIO_MASK(GPIO3)
+#define GPIO4_MASK GPIO_MASK(GPIO4)
+#define GPIO5_MASK GPIO_MASK(GPIO5)
+#define GPIO6_MASK GPIO_MASK(GPIO6)
+#define GPIO7_MASK GPIO_MASK(GPIO7)
+
+/* GPIO port pin value register (GPIOn_PIN) */
+#define GPIO_PIN(port) MMIO32(port + 0x100)
+#define GPIO0_PIN GPIO_PIN(GPIO0)
+#define GPIO1_PIN GPIO_PIN(GPIO1)
+#define GPIO2_PIN GPIO_PIN(GPIO2)
+#define GPIO3_PIN GPIO_PIN(GPIO3)
+#define GPIO4_PIN GPIO_PIN(GPIO4)
+#define GPIO5_PIN GPIO_PIN(GPIO5)
+#define GPIO6_PIN GPIO_PIN(GPIO6)
+#define GPIO7_PIN GPIO_PIN(GPIO7)
+
+/* GPIO port masked pin value register (GPIOn_MPIN) */
+#define GPIO_MPIN(port) MMIO32(port + 0x180)
+#define GPIO0_MPIN GPIO_MPIN(GPIO0)
+#define GPIO1_MPIN GPIO_MPIN(GPIO1)
+#define GPIO2_MPIN GPIO_MPIN(GPIO2)
+#define GPIO3_MPIN GPIO_MPIN(GPIO3)
+#define GPIO4_MPIN GPIO_MPIN(GPIO4)
+#define GPIO5_MPIN GPIO_MPIN(GPIO5)
+#define GPIO6_MPIN GPIO_MPIN(GPIO6)
+#define GPIO7_MPIN GPIO_MPIN(GPIO7)
+
+/* GPIO port output set register (GPIOn_SET) */
+#define GPIO_SET(port) MMIO32(port + 0x200)
+#define GPIO0_SET GPIO_SET(GPIO0)
+#define GPIO1_SET GPIO_SET(GPIO1)
+#define GPIO2_SET GPIO_SET(GPIO2)
+#define GPIO3_SET GPIO_SET(GPIO3)
+#define GPIO4_SET GPIO_SET(GPIO4)
+#define GPIO5_SET GPIO_SET(GPIO5)
+#define GPIO6_SET GPIO_SET(GPIO6)
+#define GPIO7_SET GPIO_SET(GPIO7)
+
+/* GPIO port output clear register (GPIOn_CLR) */
+#define GPIO_CLR(port) MMIO32(port + 0x280)
+#define GPIO0_CLR GPIO_CLR(GPIO0)
+#define GPIO1_CLR GPIO_CLR(GPIO1)
+#define GPIO2_CLR GPIO_CLR(GPIO2)
+#define GPIO3_CLR GPIO_CLR(GPIO3)
+#define GPIO4_CLR GPIO_CLR(GPIO4)
+#define GPIO5_CLR GPIO_CLR(GPIO5)
+#define GPIO6_CLR GPIO_CLR(GPIO6)
+#define GPIO7_CLR GPIO_CLR(GPIO7)
+
+/* GPIO port toggle register (GPIOn_NOT) */
+#define GPIO_NOT(port) MMIO32(port + 0x300)
+#define GPIO0_NOT GPIO_NOT(GPIO0)
+#define GPIO1_NOT GPIO_NOT(GPIO1)
+#define GPIO2_NOT GPIO_NOT(GPIO2)
+#define GPIO3_NOT GPIO_NOT(GPIO3)
+#define GPIO4_NOT GPIO_NOT(GPIO4)
+#define GPIO5_NOT GPIO_NOT(GPIO5)
+#define GPIO6_NOT GPIO_NOT(GPIO6)
+#define GPIO7_NOT GPIO_NOT(GPIO7)
+
+/* TODO interrupts */
+
+BEGIN_DECLS
+
+void gpio_set(uint32_t gpioport, uint32_t gpios);
+void gpio_clear(uint32_t gpioport, uint32_t gpios);
+void gpio_toggle(uint32_t gpioport, uint32_t gpios);
+
+END_DECLS
+
+/**@}*/
+
+#endif
diff --git a/libopencm3/include/libopencm3/lpc43xx/i2c.h b/libopencm3/include/libopencm3/lpc43xx/i2c.h
new file mode 100644
index 0000000..2bab0b0
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc43xx/i2c.h
@@ -0,0 +1,164 @@
+/** @defgroup i2c_defines I2C Defines
+
+@brief Defined Constants and Types for the LPC43xx I2C
+
+@ingroup LPC43xx_defines
+
+@version 1.0.0
+
+@author @htmlonly © @endhtmlonly 2012 Michael Ossmann
+
+@date 10 March 2013
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Michael Ossmann
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LPC43XX_I2C_H
+#define LPC43XX_I2C_H
+
+/**@{*/
+
+#include
+#include
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* I2C port base addresses (for convenience) */
+#define I2C0 I2C0_BASE
+#define I2C1 I2C1_BASE
+
+/* --- I2C registers ------------------------------------------------------- */
+
+/* I2C Control Set Register */
+#define I2C_CONSET(port) MMIO32(port + 0x000)
+#define I2C0_CONSET I2C_CONSET(I2C0)
+#define I2C1_CONSET I2C_CONSET(I2C1)
+
+/* I2C Status Register */
+#define I2C_STAT(port) MMIO32(port + 0x004)
+#define I2C0_STAT I2C_STAT(I2C0)
+#define I2C1_STAT I2C_STAT(I2C1)
+
+/* I2C Data Register */
+#define I2C_DAT(port) MMIO32(port + 0x008)
+#define I2C0_DAT I2C_DAT(I2C0)
+#define I2C1_DAT I2C_DAT(I2C1)
+
+/* I2C Slave Address Register 0 */
+#define I2C_ADR0(port) MMIO32(port + 0x00C)
+#define I2C0_ADR0 I2C_ADR0(I2C0)
+#define I2C1_ADR0 I2C_ADR0(I2C1)
+
+/* SCH Duty Cycle Register High Half Word */
+#define I2C_SCLH(port) MMIO32(port + 0x010)
+#define I2C0_SCLH I2C_SCLH(I2C0)
+#define I2C1_SCLH I2C_SCLH(I2C1)
+
+/* SCL Duty Cycle Register Low Half Word */
+#define I2C_SCLL(port) MMIO32(port + 0x014)
+#define I2C0_SCLL I2C_SCLL(I2C0)
+#define I2C1_SCLL I2C_SCLL(I2C1)
+
+/* I2C Control Clear Register */
+#define I2C_CONCLR(port) MMIO32(port + 0x018)
+#define I2C0_CONCLR I2C_CONCLR(I2C0)
+#define I2C1_CONCLR I2C_CONCLR(I2C1)
+
+/* Monitor mode control register */
+#define I2C_MMCTRL(port) MMIO32(port + 0x01C)
+#define I2C0_MMCTRL I2C_MMCTRL(I2C0)
+#define I2C1_MMCTRL I2C_MMCTRL(I2C1)
+
+/* I2C Slave Address Register 1 */
+#define I2C_ADR1(port) MMIO32(port + 0x020)
+#define I2C0_ADR1 I2C_ADR1(I2C0)
+#define I2C1_ADR1 I2C_ADR1(I2C1)
+
+/* I2C Slave Address Register 2 */
+#define I2C_ADR2(port) MMIO32(port + 0x024)
+#define I2C0_ADR2 I2C_ADR2(I2C0)
+#define I2C1_ADR2 I2C_ADR2(I2C1)
+
+/* I2C Slave Address Register 3 */
+#define I2C_ADR3(port) MMIO32(port + 0x028)
+#define I2C0_ADR3 I2C_ADR3(I2C0)
+#define I2C1_ADR3 I2C_ADR3(I2C1)
+
+/* Data buffer register */
+#define I2C_DATA_BUFFER(port) MMIO32(port + 0x02C)
+#define I2C0_DATA_BUFFER I2C_DATA_BUFFER(I2C0)
+#define I2C1_DATA_BUFFER I2C_DATA_BUFFER(I2C1)
+
+/* I2C Slave address mask register 0 */
+#define I2C_MASK0(port) MMIO32(port + 0x030)
+#define I2C0_MASK0 I2C_MASK0(I2C0)
+#define I2C1_MASK0 I2C_MASK0(I2C1)
+
+/* I2C Slave address mask register 1 */
+#define I2C_MASK1(port) MMIO32(port + 0x034)
+#define I2C0_MASK1 I2C_MASK1(I2C0)
+#define I2C1_MASK1 I2C_MASK1(I2C1)
+
+/* I2C Slave address mask register 2 */
+#define I2C_MASK2(port) MMIO32(port + 0x038)
+#define I2C0_MASK2 I2C_MASK2(I2C0)
+#define I2C1_MASK2 I2C_MASK2(I2C1)
+
+/* I2C Slave address mask register 3 */
+#define I2C_MASK3(port) MMIO32(port + 0x03C)
+#define I2C0_MASK3 I2C_MASK3(I2C0)
+#define I2C1_MASK3 I2C_MASK3(I2C1)
+
+/* --- I2Cx_CONCLR values -------------------------------------------------- */
+
+#define I2C_CONCLR_AAC (1 << 2) /* Assert acknowledge Clear */
+#define I2C_CONCLR_SIC (1 << 3) /* I2C interrupt Clear */
+#define I2C_CONCLR_STAC (1 << 5) /* START flag Clear */
+#define I2C_CONCLR_I2ENC (1 << 6) /* I2C interface Disable bit */
+
+/* --- I2Cx_CONSET values -------------------------------------------------- */
+
+#define I2C_CONSET_AA (1 << 2) /* Assert acknowledge flag */
+#define I2C_CONSET_SI (1 << 3) /* I2C interrupt flag */
+#define I2C_CONSET_STO (1 << 4) /* STOP flag */
+#define I2C_CONSET_STA (1 << 5) /* START flag */
+#define I2C_CONSET_I2EN (1 << 6) /* I2C interface enable */
+
+/* --- I2C const definitions ----------------------------------------------- */
+
+#define I2C_WRITE 0
+#define I2C_READ 1
+
+/* --- I2C function prototypes --------------------------------------------- */
+
+BEGIN_DECLS
+
+void i2c0_init(const uint16_t duty_cycle_count);
+void i2c0_tx_start(void);
+void i2c0_tx_byte(uint8_t byte);
+uint8_t i2c0_rx_byte(void);
+void i2c0_stop(void);
+
+END_DECLS
+
+/**@}*/
+
+#endif
diff --git a/libopencm3/include/libopencm3/lpc43xx/i2s.h b/libopencm3/include/libopencm3/lpc43xx/i2s.h
new file mode 100644
index 0000000..63f7afb
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc43xx/i2s.h
@@ -0,0 +1,122 @@
+/** @defgroup i2s_defines I2S Defines
+
+@brief Defined Constants and Types for the LPC43xx I2S
+
+@ingroup LPC43xx_defines
+
+@version 1.0.0
+
+@author @htmlonly © @endhtmlonly 2012 Michael Ossmann
+
+@date 10 March 2013
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Michael Ossmann
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LPC43XX_I2S_H
+#define LPC43XX_I2S_H
+
+/**@{*/
+
+#include
+#include
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* I2S port base addresses (for convenience) */
+#define I2S0 I2S0_BASE
+#define I2S1 I2S1_BASE
+
+/* --- I2S registers ------------------------------------------------------- */
+
+/* I2S Digital Audio Output Register */
+#define I2S_DAO(port) MMIO32(port + 0x000)
+#define I2S0_DAO I2S_DAO(I2S0)
+#define I2S1_DAO I2S_DAO(I2S1)
+
+/* I2S Digital Audio Input Register */
+#define I2S_DAI(port) MMIO32(port + 0x004)
+#define I2S0_DAI I2S_DAI(I2S0)
+#define I2S1_DAI I2S_DAI(I2S1)
+
+/* I2S Transmit FIFO */
+#define I2S_TXFIFO(port) MMIO32(port + 0x008)
+#define I2S0_TXFIFO I2S_TXFIFO(I2S0)
+#define I2S1_TXFIFO I2S_TXFIFO(I2S1)
+
+/* I2S Receive FIFO */
+#define I2S_RXFIFO(port) MMIO32(port + 0x00C)
+#define I2S0_RXFIFO I2S_RXFIFO(I2S0)
+#define I2S1_RXFIFO I2S_RXFIFO(I2S1)
+
+/* I2S Status Feedback Register */
+#define I2S_STATE(port) MMIO32(port + 0x010)
+#define I2S0_STATE I2S_STATE(I2S0)
+#define I2S1_STATE I2S_STATE(I2S1)
+
+/* I2S DMA Configuration Register 1 */
+#define I2S_DMA1(port) MMIO32(port + 0x014)
+#define I2S0_DMA1 I2S_DMA1(I2S0)
+#define I2S1_DMA1 I2S_DMA1(I2S1)
+
+/* I2S DMA Configuration Register 2 */
+#define I2S_DMA2(port) MMIO32(port + 0x018)
+#define I2S0_DMA2 I2S_DMA2(I2S0)
+#define I2S1_DMA2 I2S_DMA2(I2S1)
+
+/* I2S Interrupt Request Control Register */
+#define I2S_IRQ(port) MMIO32(port + 0x01C)
+#define I2S0_IRQ I2S_IRQ(I2S0)
+#define I2S1_IRQ I2S_IRQ(I2S1)
+
+/* I2S Transmit MCLK divider */
+#define I2S_TXRATE(port) MMIO32(port + 0x020)
+#define I2S0_TXRATE I2S_TXRATE(I2S0)
+#define I2S1_TXRATE I2S_TXRATE(I2S1)
+
+/* I2S Receive MCLK divider */
+#define I2S_RXRATE(port) MMIO32(port + 0x024)
+#define I2S0_RXRATE I2S_RXRATE(I2S0)
+#define I2S1_RXRATE I2S_RXRATE(I2S1)
+
+/* I2S Transmit bit rate divider */
+#define I2S_TXBITRATE(port) MMIO32(port + 0x028)
+#define I2S0_TXBITRATE I2S_TXBITRATE(I2S0)
+#define I2S1_TXBITRATE I2S_TXBITRATE(I2S1)
+
+/* I2S Receive bit rate divider */
+#define I2S_RXBITRATE(port) MMIO32(port + 0x02C)
+#define I2S0_RXBITRATE I2S_RXBITRATE(I2S0)
+#define I2S1_RXBITRATE I2S_RXBITRATE(I2S1)
+
+/* I2S Transmit mode control */
+#define I2S_TXMODE(port) MMIO32(port + 0x030)
+#define I2S0_TXMODE I2S_TXMODE(I2S0)
+#define I2S1_TXMODE I2S_TXMODE(I2S1)
+
+/* I2S Receive mode control */
+#define I2S_RXMODE(port) MMIO32(port + 0x034)
+#define I2S0_RXMODE I2S_RXMODE(I2S0)
+#define I2S1_RXMODE I2S_RXMODE(I2S1)
+
+/**@}*/
+
+#endif
diff --git a/libopencm3/include/libopencm3/lpc43xx/ipc.h b/libopencm3/include/libopencm3/lpc43xx/ipc.h
new file mode 100644
index 0000000..ddd81b8
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc43xx/ipc.h
@@ -0,0 +1,30 @@
+/*
+* This file is part of the libopencm3 project.
+*
+* Copyright (C) 2012 Benjamin Vernoux
+*
+* This library is free software: you can redistribute it and/or modify
+* it under the terms of the GNU Lesser General Public License as published by
+* the Free Software Foundation, either version 3 of the License, or
+* (at your option) any later version.
+*
+* This library is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU Lesser General Public License for more details.
+*
+* You should have received a copy of the GNU Lesser General Public License
+* along with this library. If not, see .
+*/
+
+#ifndef LPC43XX_IPC_H
+#define LPC43XX_IPC_H
+
+#include
+#include
+
+void ipc_halt_m0(void);
+
+void ipc_start_m0(uint32_t cm0_baseaddr);
+
+#endif
diff --git a/libopencm3/include/libopencm3/lpc43xx/m0/irq.json b/libopencm3/include/libopencm3/lpc43xx/m0/irq.json
new file mode 100644
index 0000000..828c1dd
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc43xx/m0/irq.json
@@ -0,0 +1,36 @@
+{
+ "irqs": {
+ "0": "rtc",
+ "1": "m4core",
+ "2": "dma",
+ "4": "flasheepromat",
+ "5": "ethernet",
+ "6": "sdio",
+ "7": "lcd",
+ "8": "usb0",
+ "9": "usb1",
+ "10": "sct",
+ "11": "ritimer_or_wwdt",
+ "12": "timer0",
+ "13": "gint1",
+ "14": "pin_int4",
+ "15": "timer3",
+ "16": "mcpwm",
+ "17": "adc0",
+ "18": "i2c0_or_irc1",
+ "19": "sgpio",
+ "20": "spi_or_dac",
+ "21": "adc1",
+ "22": "ssp0_or_ssp1",
+ "23": "eventrouter",
+ "24": "usart0",
+ "25": "uart1",
+ "26": "usart2_or_c_can1",
+ "27": "usart3",
+ "28": "i2s0_or_i2s1",
+ "29": "c_can0"
+ },
+ "partname_humanreadable": "LPC 43xx series M0 core",
+ "partname_doxygen": "LPC43xx (M0)",
+ "includeguard": "LIBOPENCM3_LPC43xx_M0_NVIC_H"
+}
\ No newline at end of file
diff --git a/libopencm3/include/libopencm3/lpc43xx/m4/irq.json b/libopencm3/include/libopencm3/lpc43xx/m4/irq.json
new file mode 100644
index 0000000..376fab1
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc43xx/m4/irq.json
@@ -0,0 +1,54 @@
+{
+ "irqs": {
+ "0": "dac",
+ "1": "m0core",
+ "2": "dma",
+ "5": "ethernet",
+ "6": "sdio",
+ "7": "lcd",
+ "8": "usb0",
+ "9": "usb1",
+ "10": "sct",
+ "11": "ritimer",
+ "12": "timer0",
+ "13": "timer1",
+ "14": "timer2",
+ "15": "timer3",
+ "16": "mcpwm",
+ "17": "adc0",
+ "18": "i2c0",
+ "19": "i2c1",
+ "20": "spi",
+ "21": "adc1",
+ "22": "ssp0",
+ "23": "ssp1",
+ "24": "usart0",
+ "25": "uart1",
+ "26": "usart2",
+ "27": "usart3",
+ "28": "i2s0",
+ "29": "i2s1",
+ "30": "spifi",
+ "31": "sgpio",
+ "32": "pin_int0",
+ "33": "pin_int1",
+ "34": "pin_int2",
+ "35": "pin_int3",
+ "36": "pin_int4",
+ "37": "pin_int5",
+ "38": "pin_int6",
+ "39": "pin_int7",
+ "40": "gint0",
+ "41": "gint1",
+ "42": "eventrouter",
+ "43": "c_can1",
+ "46": "atimer",
+ "47": "rtc",
+ "49": "wwdt",
+ "51": "c_can0",
+ "52": "qei"
+ },
+ "partname_humanreadable": "LPC 43xx series M4 core",
+ "partname_doxygen": "LPC43xx (M4)",
+ "includeguard": "LIBOPENCM3_LPC43xx_M4_NVIC_H"
+}
\ No newline at end of file
diff --git a/libopencm3/include/libopencm3/lpc43xx/memorymap.h b/libopencm3/include/libopencm3/lpc43xx/memorymap.h
new file mode 100644
index 0000000..5d2bdc4
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc43xx/memorymap.h
@@ -0,0 +1,138 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2010 Uwe Hermann
+ * Copyright (C) 2012 Michael Ossmann
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LPC43XX_MEMORYMAP_H
+#define LPC43XX_MEMORYMAP_H
+
+#include
+
+/* --- LPC43XX specific peripheral definitions ----------------------------- */
+
+/* Memory map for all busses */
+#define PERIPH_BASE_AHB (0x40000000U)
+#define PERIPH_BASE_APB0 (0x40080000U)
+#define PERIPH_BASE_APB1 (0x400A0000U)
+#define PERIPH_BASE_APB2 (0x400C0000U)
+#define PERIPH_BASE_APB3 (0x400E0000U)
+
+/* Register boundary addresses */
+
+/* AHB (0x4000 0000 - 0x4001 2000) */
+#define SCT_BASE (PERIPH_BASE_AHB + 0x00000)
+/* PERIPH_BASE_AHB + 0x01000 (0x4000 1000 - 0x4000 1FFF): Reserved */
+#define GPDMA_BASE (PERIPH_BASE_AHB + 0x02000)
+#define SPIFI_BASE (PERIPH_BASE_AHB + 0x03000)
+#define SDIO_BASE (PERIPH_BASE_AHB + 0x04000)
+#define EMC_BASE (PERIPH_BASE_AHB + 0x05000)
+#define USB0_BASE (PERIPH_BASE_AHB + 0x06000)
+#define USB1_BASE (PERIPH_BASE_AHB + 0x07000)
+#define LCD_BASE (PERIPH_BASE_AHB + 0x08000)
+/* PERIPH_BASE_AHB + 0x09000 (0x4000 9000 - 0x4000 FFFF): Reserved */
+#define ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000)
+
+/* 0x4001 2000 - 0x4003 FFFF Reserved */
+
+/* RTC domain peripherals */
+#define ATIMER_BASE (0x40040000U)
+#define BACKUP_REG_BASE (0x40041000U)
+#define PMC_BASE (0x40042000U)
+#define CREG_BASE (0x40043000U)
+#define EVENTROUTER_BASE (0x40044000U)
+#define OTP_BASE (0x40045000U)
+#define RTC_BASE (0x40046000U)
+/* 0x4004 7000 - 0x4004 FFFF Reserved */
+
+/* clocking/reset control peripherals */
+#define CGU_BASE (0x40050000U)
+#define CCU1_BASE (0x40051000U)
+#define CCU2_BASE (0x40052000U)
+#define RGU_BASE (0x40053000U)
+/* 0x4005 4000 - 0x4005 FFFF Reserved */
+
+/* 0x4006 0000 - 0x4007 FFFF Reserved */
+
+/* APB0 ( 0x4008 0000 - 0x4008 FFFF) */
+#define WWDT_BASE (PERIPH_BASE_APB0 + 0x00000)
+#define USART0_BASE (PERIPH_BASE_APB0 + 0x01000)
+#define UART1_BASE (PERIPH_BASE_APB0 + 0x02000)
+#define SSP0_BASE (PERIPH_BASE_APB0 + 0x03000)
+#define TIMER0_BASE (PERIPH_BASE_APB0 + 0x04000)
+#define TIMER1_BASE (PERIPH_BASE_APB0 + 0x05000)
+#define SCU_BASE (PERIPH_BASE_APB0 + 0x06000)
+#define GPIO_PIN_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x07000)
+#define GPIO_GROUP0_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x08000)
+#define GPIO_GROUP1_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x09000)
+/* 0x4008 A000 - 0x4008 FFFF Reserved */
+
+/* 0x4009 0000 - 0x4009 FFFF Reserved */
+
+/* APB1 (0x400A 0000 - 0x400A FFFF) */
+#define MCPWM_BASE (PERIPH_BASE_APB1 + 0x00000)
+#define I2C0_BASE (PERIPH_BASE_APB1 + 0x01000)
+#define I2S0_BASE (PERIPH_BASE_APB1 + 0x02000)
+#define I2S1_BASE (PERIPH_BASE_APB1 + 0x03000)
+#define C_CCAN1_BASE (PERIPH_BASE_APB1 + 0x04000)
+/* 0x400A 5000 - 0x400A FFFF Reserved */
+
+/* 0x400B 0000 - 0x400B FFFF Reserved */
+
+/* APB2 (0x400C 0000 - 0x400C FFFF) */
+#define RITIMER_BASE (PERIPH_BASE_APB2 + 0x00000)
+#define USART2_BASE (PERIPH_BASE_APB2 + 0x01000)
+#define USART3_BASE (PERIPH_BASE_APB2 + 0x02000)
+#define TIMER2_BASE (PERIPH_BASE_APB2 + 0x03000)
+#define TIMER3_BASE (PERIPH_BASE_APB2 + 0x04000)
+#define SSP1_BASE (PERIPH_BASE_APB2 + 0x05000)
+#define QEI_BASE (PERIPH_BASE_APB2 + 0x06000)
+#define GIMA_BASE (PERIPH_BASE_APB2 + 0x07000)
+/* 0x400C 8000 - 0x400C FFFF Reserved */
+
+/* 0x400D 0000 - 0x400D FFFF Reserved */
+
+/* APB3 (0x400E 0000 - 0x400E FFFF) */
+#define I2C1_BASE (PERIPH_BASE_APB3 + 0x00000)
+#define DAC_BASE (PERIPH_BASE_APB3 + 0x01000)
+#define C_CAN0_BASE (PERIPH_BASE_APB3 + 0x02000)
+#define ADC0_BASE (PERIPH_BASE_APB3 + 0x03000)
+#define ADC1_BASE (PERIPH_BASE_APB3 + 0x04000)
+/* 0x400E 5000 - 0x400E FFFF Reserved */
+
+/* 0x400F 0000 - 0x400F 0FFF Reserved */
+
+#define AES_BASE (0x400F1000U)
+
+/* 0x400F 2000 - 0x400F 3FFF Reserved */
+
+#define GPIO_PORT_BASE (0x400F4000U)
+
+/* 0x400F 8000 - 0x400F FFFF Reserved */
+
+#define SPI_PORT_BASE (0x40100000U)
+#define SGPIO_PORT_BASE (0x40101000U)
+
+/* 0x4010 2000 - 0x41FF FFFF Reserved */
+
+/* 0x4200 0000 - 0x43FF FFFF peripheral bit band alias region */
+
+/* 0x4400 0000 - 0x5FFF FFFF Reserved */
+
+/* 0x6000 0000 - 0xFFFF FFFF external memories and ARM private bus */
+
+#endif
diff --git a/libopencm3/include/libopencm3/lpc43xx/rgu.h b/libopencm3/include/libopencm3/lpc43xx/rgu.h
new file mode 100644
index 0000000..0ec0146
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc43xx/rgu.h
@@ -0,0 +1,1206 @@
+/** @defgroup rgu_defines Reset Generation Unit Defines
+
+@brief Defined Constants and Types for the LPC43xx Reset Generation Unit
+
+@ingroup LPC43xx_defines
+
+@version 1.0.0
+
+@author @htmlonly © @endhtmlonly 2012 Michael Ossmann
+
+@date 10 March 2013
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Michael Ossmann
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LPC43XX_RGU_H
+#define LPC43XX_RGU_H
+
+/**@{*/
+
+#include
+#include
+
+/* --- RGU registers ------------------------------------------------------- */
+
+/* Reset control register 0 */
+#define RESET_CTRL0 MMIO32(RGU_BASE + 0x100)
+
+/* Reset control register 1 */
+#define RESET_CTRL1 MMIO32(RGU_BASE + 0x104)
+
+/* Reset status register 0 */
+#define RESET_STATUS0 MMIO32(RGU_BASE + 0x110)
+
+/* Reset status register 1 */
+#define RESET_STATUS1 MMIO32(RGU_BASE + 0x114)
+
+/* Reset status register 2 */
+#define RESET_STATUS2 MMIO32(RGU_BASE + 0x118)
+
+/* Reset status register 3 */
+#define RESET_STATUS3 MMIO32(RGU_BASE + 0x11C)
+
+/* Reset active status register 0 */
+#define RESET_ACTIVE_STATUS0 MMIO32(RGU_BASE + 0x150)
+
+/* Reset active status register 1 */
+#define RESET_ACTIVE_STATUS1 MMIO32(RGU_BASE + 0x154)
+
+/* Reset external status register 0 for CORE_RST */
+#define RESET_EXT_STAT0 MMIO32(RGU_BASE + 0x400)
+
+/* Reset external status register 1 for PERIPH_RST */
+#define RESET_EXT_STAT1 MMIO32(RGU_BASE + 0x404)
+
+/* Reset external status register 2 for MASTER_RST */
+#define RESET_EXT_STAT2 MMIO32(RGU_BASE + 0x408)
+
+/* Reserved */
+#define RESET_EXT_STAT3 MMIO32(RGU_BASE + 0x40C)
+
+/* Reset external status register 4 for WWDT_RST */
+#define RESET_EXT_STAT4 MMIO32(RGU_BASE + 0x410)
+
+/* Reset external status register 5 for CREG_RST */
+#define RESET_EXT_STAT5 MMIO32(RGU_BASE + 0x414)
+
+/* Reserved */
+#define RESET_EXT_STAT6 MMIO32(RGU_BASE + 0x418)
+
+/* Reserved */
+#define RESET_EXT_STAT7 MMIO32(RGU_BASE + 0x41C)
+
+/* Reset external status register 8 for BUS_RST */
+#define RESET_EXT_STAT8 MMIO32(RGU_BASE + 0x420)
+
+/* Reset external status register 9 for SCU_RST */
+#define RESET_EXT_STAT9 MMIO32(RGU_BASE + 0x424)
+
+/* Reserved */
+#define RESET_EXT_STAT10 MMIO32(RGU_BASE + 0x428)
+
+/* Reserved */
+#define RESET_EXT_STAT11 MMIO32(RGU_BASE + 0x42C)
+
+/* Reserved */
+#define RESET_EXT_STAT12 MMIO32(RGU_BASE + 0x430)
+
+/* Reset external status register 13 for M4_RST */
+#define RESET_EXT_STAT13 MMIO32(RGU_BASE + 0x434)
+
+/* Reserved */
+#define RESET_EXT_STAT14 MMIO32(RGU_BASE + 0x438)
+
+/* Reserved */
+#define RESET_EXT_STAT15 MMIO32(RGU_BASE + 0x43C)
+
+/* Reset external status register 16 for LCD_RST */
+#define RESET_EXT_STAT16 MMIO32(RGU_BASE + 0x440)
+
+/* Reset external status register 17 for USB0_RST */
+#define RESET_EXT_STAT17 MMIO32(RGU_BASE + 0x444)
+
+/* Reset external status register 18 for USB1_RST */
+#define RESET_EXT_STAT18 MMIO32(RGU_BASE + 0x448)
+
+/* Reset external status register 19 for DMA_RST */
+#define RESET_EXT_STAT19 MMIO32(RGU_BASE + 0x44C)
+
+/* Reset external status register 20 for SDIO_RST */
+#define RESET_EXT_STAT20 MMIO32(RGU_BASE + 0x450)
+
+/* Reset external status register 21 for EMC_RST */
+#define RESET_EXT_STAT21 MMIO32(RGU_BASE + 0x454)
+
+/* Reset external status register 22 for ETHERNET_RST */
+#define RESET_EXT_STAT22 MMIO32(RGU_BASE + 0x458)
+
+/* Reserved */
+#define RESET_EXT_STAT23 MMIO32(RGU_BASE + 0x45C)
+
+/* Reserved */
+#define RESET_EXT_STAT24 MMIO32(RGU_BASE + 0x460)
+
+/* Reserved */
+#define RESET_EXT_STAT25 MMIO32(RGU_BASE + 0x464)
+
+/* Reserved */
+#define RESET_EXT_STAT26 MMIO32(RGU_BASE + 0x468)
+
+/* Reserved */
+#define RESET_EXT_STAT27 MMIO32(RGU_BASE + 0x46C)
+
+/* Reset external status register 28 for GPIO_RST */
+#define RESET_EXT_STAT28 MMIO32(RGU_BASE + 0x470)
+
+/* Reserved */
+#define RESET_EXT_STAT29 MMIO32(RGU_BASE + 0x474)
+
+/* Reserved */
+#define RESET_EXT_STAT30 MMIO32(RGU_BASE + 0x478)
+
+/* Reserved */
+#define RESET_EXT_STAT31 MMIO32(RGU_BASE + 0x47C)
+
+/* Reset external status register 32 for TIMER0_RST */
+#define RESET_EXT_STAT32 MMIO32(RGU_BASE + 0x480)
+
+/* Reset external status register 33 for TIMER1_RST */
+#define RESET_EXT_STAT33 MMIO32(RGU_BASE + 0x484)
+
+/* Reset external status register 34 for TIMER2_RST */
+#define RESET_EXT_STAT34 MMIO32(RGU_BASE + 0x488)
+
+/* Reset external status register 35 for TIMER3_RST */
+#define RESET_EXT_STAT35 MMIO32(RGU_BASE + 0x48C)
+
+/* Reset external status register 36 for RITIMER_RST */
+#define RESET_EXT_STAT36 MMIO32(RGU_BASE + 0x490)
+
+/* Reset external status register 37 for SCT_RST */
+#define RESET_EXT_STAT37 MMIO32(RGU_BASE + 0x494)
+
+/* Reset external status register 38 for MOTOCONPWM_RST */
+#define RESET_EXT_STAT38 MMIO32(RGU_BASE + 0x498)
+
+/* Reset external status register 39 for QEI_RST */
+#define RESET_EXT_STAT39 MMIO32(RGU_BASE + 0x49C)
+
+/* Reset external status register 40 for ADC0_RST */
+#define RESET_EXT_STAT40 MMIO32(RGU_BASE + 0x4A0)
+
+/* Reset external status register 41 for ADC1_RST */
+#define RESET_EXT_STAT41 MMIO32(RGU_BASE + 0x4A4)
+
+/* Reset external status register 42 for DAC_RST */
+#define RESET_EXT_STAT42 MMIO32(RGU_BASE + 0x4A8)
+
+/* Reserved */
+#define RESET_EXT_STAT43 MMIO32(RGU_BASE + 0x4AC)
+
+/* Reset external status register 44 for UART0_RST */
+#define RESET_EXT_STAT44 MMIO32(RGU_BASE + 0x4B0)
+
+/* Reset external status register 45 for UART1_RST */
+#define RESET_EXT_STAT45 MMIO32(RGU_BASE + 0x4B4)
+
+/* Reset external status register 46 for UART2_RST */
+#define RESET_EXT_STAT46 MMIO32(RGU_BASE + 0x4B8)
+
+/* Reset external status register 47 for UART3_RST */
+#define RESET_EXT_STAT47 MMIO32(RGU_BASE + 0x4BC)
+
+/* Reset external status register 48 for I2C0_RST */
+#define RESET_EXT_STAT48 MMIO32(RGU_BASE + 0x4C0)
+
+/* Reset external status register 49 for I2C1_RST */
+#define RESET_EXT_STAT49 MMIO32(RGU_BASE + 0x4C4)
+
+/* Reset external status register 50 for SSP0_RST */
+#define RESET_EXT_STAT50 MMIO32(RGU_BASE + 0x4C8)
+
+/* Reset external status register 51 for SSP1_RST */
+#define RESET_EXT_STAT51 MMIO32(RGU_BASE + 0x4CC)
+
+/* Reset external status register 52 for I2S_RST */
+#define RESET_EXT_STAT52 MMIO32(RGU_BASE + 0x4D0)
+
+/* Reset external status register 53 for SPIFI_RST */
+#define RESET_EXT_STAT53 MMIO32(RGU_BASE + 0x4D4)
+
+/* Reset external status register 54 for CAN1_RST */
+#define RESET_EXT_STAT54 MMIO32(RGU_BASE + 0x4D8)
+
+/* Reset external status register 55 for CAN0_RST */
+#define RESET_EXT_STAT55 MMIO32(RGU_BASE + 0x4DC)
+
+/* Reset external status register 56 for M0APP_RST */
+#define RESET_EXT_STAT56 MMIO32(RGU_BASE + 0x4E0)
+
+/* Reset external status register 57 for SGPIO_RST */
+#define RESET_EXT_STAT57 MMIO32(RGU_BASE + 0x4E4)
+
+/* Reset external status register 58 for SPI_RST */
+#define RESET_EXT_STAT58 MMIO32(RGU_BASE + 0x4E8)
+
+/* Reserved */
+#define RESET_EXT_STAT59 MMIO32(RGU_BASE + 0x4EC)
+
+/* Reserved */
+#define RESET_EXT_STAT60 MMIO32(RGU_BASE + 0x4F0)
+
+/* Reserved */
+#define RESET_EXT_STAT61 MMIO32(RGU_BASE + 0x4F4)
+
+/* Reserved */
+#define RESET_EXT_STAT62 MMIO32(RGU_BASE + 0x4F8)
+
+/* Reserved */
+#define RESET_EXT_STAT63 MMIO32(RGU_BASE + 0x4FC)
+
+/* --- RESET_CTRL0 values --------------------------------------- */
+
+/* CORE_RST: Writing a one activates the reset */
+#define RESET_CTRL0_CORE_RST_SHIFT (0)
+#define RESET_CTRL0_CORE_RST (1 << RESET_CTRL0_CORE_RST_SHIFT)
+
+/* PERIPH_RST: Writing a one activates the reset */
+#define RESET_CTRL0_PERIPH_RST_SHIFT (1)
+#define RESET_CTRL0_PERIPH_RST (1 << RESET_CTRL0_PERIPH_RST_SHIFT)
+
+/* MASTER_RST: Writing a one activates the reset */
+#define RESET_CTRL0_MASTER_RST_SHIFT (2)
+#define RESET_CTRL0_MASTER_RST (1 << RESET_CTRL0_MASTER_RST_SHIFT)
+
+/* WWDT_RST: Writing a one to this bit has no effect */
+#define RESET_CTRL0_WWDT_RST_SHIFT (4)
+#define RESET_CTRL0_WWDT_RST (1 << RESET_CTRL0_WWDT_RST_SHIFT)
+
+/* CREG_RST: Writing a one to this bit has no effect */
+#define RESET_CTRL0_CREG_RST_SHIFT (5)
+#define RESET_CTRL0_CREG_RST (1 << RESET_CTRL0_CREG_RST_SHIFT)
+
+/* BUS_RST: Writing a one activates the reset */
+#define RESET_CTRL0_BUS_RST_SHIFT (8)
+#define RESET_CTRL0_BUS_RST (1 << RESET_CTRL0_BUS_RST_SHIFT)
+
+/* SCU_RST: Writing a one activates the reset */
+#define RESET_CTRL0_SCU_RST_SHIFT (9)
+#define RESET_CTRL0_SCU_RST (1 << RESET_CTRL0_SCU_RST_SHIFT)
+
+/* M4_RST: Writing a one activates the reset */
+#define RESET_CTRL0_M4_RST_SHIFT (13)
+#define RESET_CTRL0_M4_RST (1 << RESET_CTRL0_M4_RST_SHIFT)
+
+/* LCD_RST: Writing a one activates the reset */
+#define RESET_CTRL0_LCD_RST_SHIFT (16)
+#define RESET_CTRL0_LCD_RST (1 << RESET_CTRL0_LCD_RST_SHIFT)
+
+/* USB0_RST: Writing a one activates the reset */
+#define RESET_CTRL0_USB0_RST_SHIFT (17)
+#define RESET_CTRL0_USB0_RST (1 << RESET_CTRL0_USB0_RST_SHIFT)
+
+/* USB1_RST: Writing a one activates the reset */
+#define RESET_CTRL0_USB1_RST_SHIFT (18)
+#define RESET_CTRL0_USB1_RST (1 << RESET_CTRL0_USB1_RST_SHIFT)
+
+/* DMA_RST: Writing a one activates the reset */
+#define RESET_CTRL0_DMA_RST_SHIFT (19)
+#define RESET_CTRL0_DMA_RST (1 << RESET_CTRL0_DMA_RST_SHIFT)
+
+/* SDIO_RST: Writing a one activates the reset */
+#define RESET_CTRL0_SDIO_RST_SHIFT (20)
+#define RESET_CTRL0_SDIO_RST (1 << RESET_CTRL0_SDIO_RST_SHIFT)
+
+/* EMC_RST: Writing a one activates the reset */
+#define RESET_CTRL0_EMC_RST_SHIFT (21)
+#define RESET_CTRL0_EMC_RST (1 << RESET_CTRL0_EMC_RST_SHIFT)
+
+/* ETHERNET_RST: Writing a one activates the reset */
+#define RESET_CTRL0_ETHERNET_RST_SHIFT (22)
+#define RESET_CTRL0_ETHERNET_RST (1 << RESET_CTRL0_ETHERNET_RST_SHIFT)
+
+/* FLASHA_RST: Writing a one activates the reset */
+#define RESET_CTRL0_FLASHA_RST_SHIFT (25)
+#define RESET_CTRL0_FLASHA_RST (1 << RESET_CTRL0_FLASHA_RST_SHIFT)
+
+/* EEPROM_RST: Writing a one activates the reset */
+#define RESET_CTRL0_EEPROM_RST_SHIFT (27)
+#define RESET_CTRL0_EEPROM_RST (1 << RESET_CTRL0_EEPROM_RST_SHIFT)
+
+/* GPIO_RST: Writing a one activates the reset */
+#define RESET_CTRL0_GPIO_RST_SHIFT (28)
+#define RESET_CTRL0_GPIO_RST (1 << RESET_CTRL0_GPIO_RST_SHIFT)
+
+/* FLASHB_RST: Writing a one activates the reset */
+#define RESET_CTRL0_FLASHB_RST_SHIFT (29)
+#define RESET_CTRL0_FLASHB_RST (1 << RESET_CTRL0_FLASHB_RST_SHIFT)
+
+/* --- RESET_CTRL1 values --------------------------------------- */
+
+/* TIMER0_RST: Writing a one activates the reset */
+#define RESET_CTRL1_TIMER0_RST_SHIFT (0)
+#define RESET_CTRL1_TIMER0_RST (1 << RESET_CTRL1_TIMER0_RST_SHIFT)
+
+/* TIMER1_RST: Writing a one activates the reset */
+#define RESET_CTRL1_TIMER1_RST_SHIFT (1)
+#define RESET_CTRL1_TIMER1_RST (1 << RESET_CTRL1_TIMER1_RST_SHIFT)
+
+/* TIMER2_RST: Writing a one activates the reset */
+#define RESET_CTRL1_TIMER2_RST_SHIFT (2)
+#define RESET_CTRL1_TIMER2_RST (1 << RESET_CTRL1_TIMER2_RST_SHIFT)
+
+/* TIMER3_RST: Writing a one activates the reset */
+#define RESET_CTRL1_TIMER3_RST_SHIFT (3)
+#define RESET_CTRL1_TIMER3_RST (1 << RESET_CTRL1_TIMER3_RST_SHIFT)
+
+/* RTIMER_RST: Writing a one activates the reset */
+#define RESET_CTRL1_RTIMER_RST_SHIFT (4)
+#define RESET_CTRL1_RTIMER_RST (1 << RESET_CTRL1_RTIMER_RST_SHIFT)
+
+/* SCT_RST: Writing a one activates the reset */
+#define RESET_CTRL1_SCT_RST_SHIFT (5)
+#define RESET_CTRL1_SCT_RST (1 << RESET_CTRL1_SCT_RST_SHIFT)
+
+/* MOTOCONPWM_RST: Writing a one activates the reset */
+#define RESET_CTRL1_MOTOCONPWM_RST_SHIFT (6)
+#define RESET_CTRL1_MOTOCONPWM_RST (1 << RESET_CTRL1_MOTOCONPWM_RST_SHIFT)
+
+/* QEI_RST: Writing a one activates the reset */
+#define RESET_CTRL1_QEI_RST_SHIFT (7)
+#define RESET_CTRL1_QEI_RST (1 << RESET_CTRL1_QEI_RST_SHIFT)
+
+/* ADC0_RST: Writing a one activates the reset */
+#define RESET_CTRL1_ADC0_RST_SHIFT (8)
+#define RESET_CTRL1_ADC0_RST (1 << RESET_CTRL1_ADC0_RST_SHIFT)
+
+/* ADC1_RST: Writing a one activates the reset */
+#define RESET_CTRL1_ADC1_RST_SHIFT (9)
+#define RESET_CTRL1_ADC1_RST (1 << RESET_CTRL1_ADC1_RST_SHIFT)
+
+/* DAC_RST: Writing a one activates the reset */
+#define RESET_CTRL1_DAC_RST_SHIFT (10)
+#define RESET_CTRL1_DAC_RST (1 << RESET_CTRL1_DAC_RST_SHIFT)
+
+/* UART0_RST: Writing a one activates the reset */
+#define RESET_CTRL1_UART0_RST_SHIFT (12)
+#define RESET_CTRL1_UART0_RST (1 << RESET_CTRL1_UART0_RST_SHIFT)
+
+/* UART1_RST: Writing a one activates the reset */
+#define RESET_CTRL1_UART1_RST_SHIFT (13)
+#define RESET_CTRL1_UART1_RST (1 << RESET_CTRL1_UART1_RST_SHIFT)
+
+/* UART2_RST: Writing a one activates the reset */
+#define RESET_CTRL1_UART2_RST_SHIFT (14)
+#define RESET_CTRL1_UART2_RST (1 << RESET_CTRL1_UART2_RST_SHIFT)
+
+/* UART3_RST: Writing a one activates the reset */
+#define RESET_CTRL1_UART3_RST_SHIFT (15)
+#define RESET_CTRL1_UART3_RST (1 << RESET_CTRL1_UART3_RST_SHIFT)
+
+/* I2C0_RST: Writing a one activates the reset */
+#define RESET_CTRL1_I2C0_RST_SHIFT (16)
+#define RESET_CTRL1_I2C0_RST (1 << RESET_CTRL1_I2C0_RST_SHIFT)
+
+/* I2C1_RST: Writing a one activates the reset */
+#define RESET_CTRL1_I2C1_RST_SHIFT (17)
+#define RESET_CTRL1_I2C1_RST (1 << RESET_CTRL1_I2C1_RST_SHIFT)
+
+/* SSP0_RST: Writing a one activates the reset */
+#define RESET_CTRL1_SSP0_RST_SHIFT (18)
+#define RESET_CTRL1_SSP0_RST (1 << RESET_CTRL1_SSP0_RST_SHIFT)
+
+/* SSP1_RST: Writing a one activates the reset */
+#define RESET_CTRL1_SSP1_RST_SHIFT (19)
+#define RESET_CTRL1_SSP1_RST (1 << RESET_CTRL1_SSP1_RST_SHIFT)
+
+/* I2S_RST: Writing a one activates the reset */
+#define RESET_CTRL1_I2S_RST_SHIFT (20)
+#define RESET_CTRL1_I2S_RST (1 << RESET_CTRL1_I2S_RST_SHIFT)
+
+/* SPIFI_RST: Writing a one activates the reset */
+#define RESET_CTRL1_SPIFI_RST_SHIFT (21)
+#define RESET_CTRL1_SPIFI_RST (1 << RESET_CTRL1_SPIFI_RST_SHIFT)
+
+/* CAN1_RST: Writing a one activates the reset */
+#define RESET_CTRL1_CAN1_RST_SHIFT (22)
+#define RESET_CTRL1_CAN1_RST (1 << RESET_CTRL1_CAN1_RST_SHIFT)
+
+/* CAN0_RST: Writing a one activates the reset */
+#define RESET_CTRL1_CAN0_RST_SHIFT (23)
+#define RESET_CTRL1_CAN0_RST (1 << RESET_CTRL1_CAN0_RST_SHIFT)
+
+/* M0APP_RST: Writing a one activates the reset */
+#define RESET_CTRL1_M0APP_RST_SHIFT (24)
+#define RESET_CTRL1_M0APP_RST (1 << RESET_CTRL1_M0APP_RST_SHIFT)
+
+/* SGPIO_RST: Writing a one activates the reset */
+#define RESET_CTRL1_SGPIO_RST_SHIFT (25)
+#define RESET_CTRL1_SGPIO_RST (1 << RESET_CTRL1_SGPIO_RST_SHIFT)
+
+/* SPI_RST: Writing a one activates the reset */
+#define RESET_CTRL1_SPI_RST_SHIFT (26)
+#define RESET_CTRL1_SPI_RST (1 << RESET_CTRL1_SPI_RST_SHIFT)
+
+/* --- RESET_STATUS0 values ------------------------------------- */
+
+/* CORE_RST: Status of the CORE_RST reset generator output */
+#define RESET_STATUS0_CORE_RST_SHIFT (0)
+#define RESET_STATUS0_CORE_RST_MASK (0x3 << RESET_STATUS0_CORE_RST_SHIFT)
+#define RESET_STATUS0_CORE_RST(x) ((x) << RESET_STATUS0_CORE_RST_SHIFT)
+
+/* PERIPH_RST: Status of the PERIPH_RST reset generator output */
+#define RESET_STATUS0_PERIPH_RST_SHIFT (2)
+#define RESET_STATUS0_PERIPH_RST_MASK (0x3 << RESET_STATUS0_PERIPH_RST_SHIFT)
+#define RESET_STATUS0_PERIPH_RST(x) ((x) << RESET_STATUS0_PERIPH_RST_SHIFT)
+
+/* MASTER_RST: Status of the MASTER_RST reset generator output */
+#define RESET_STATUS0_MASTER_RST_SHIFT (4)
+#define RESET_STATUS0_MASTER_RST_MASK (0x3 << RESET_STATUS0_MASTER_RST_SHIFT)
+#define RESET_STATUS0_MASTER_RST(x) ((x) << RESET_STATUS0_MASTER_RST_SHIFT)
+
+/* WWDT_RST: Status of the WWDT_RST reset generator output */
+#define RESET_STATUS0_WWDT_RST_SHIFT (8)
+#define RESET_STATUS0_WWDT_RST_MASK (0x3 << RESET_STATUS0_WWDT_RST_SHIFT)
+#define RESET_STATUS0_WWDT_RST(x) ((x) << RESET_STATUS0_WWDT_RST_SHIFT)
+
+/* CREG_RST: Status of the CREG_RST reset generator output */
+#define RESET_STATUS0_CREG_RST_SHIFT (10)
+#define RESET_STATUS0_CREG_RST_MASK (0x3 << RESET_STATUS0_CREG_RST_SHIFT)
+#define RESET_STATUS0_CREG_RST(x) ((x) << RESET_STATUS0_CREG_RST_SHIFT)
+
+/* BUS_RST: Status of the BUS_RST reset generator output */
+#define RESET_STATUS0_BUS_RST_SHIFT (16)
+#define RESET_STATUS0_BUS_RST_MASK (0x3 << RESET_STATUS0_BUS_RST_SHIFT)
+#define RESET_STATUS0_BUS_RST(x) ((x) << RESET_STATUS0_BUS_RST_SHIFT)
+
+/* SCU_RST: Status of the SCU_RST reset generator output */
+#define RESET_STATUS0_SCU_RST_SHIFT (18)
+#define RESET_STATUS0_SCU_RST_MASK (0x3 << RESET_STATUS0_SCU_RST_SHIFT)
+#define RESET_STATUS0_SCU_RST(x) ((x) << RESET_STATUS0_SCU_RST_SHIFT)
+
+/* M4_RST: Status of the M4_RST reset generator output */
+#define RESET_STATUS0_M4_RST_SHIFT (26)
+#define RESET_STATUS0_M4_RST_MASK (0x3 << RESET_STATUS0_M4_RST_SHIFT)
+#define RESET_STATUS0_M4_RST(x) ((x) << RESET_STATUS0_M4_RST_SHIFT)
+
+/* --- RESET_STATUS1 values ------------------------------------- */
+
+/* LCD_RST: Status of the LCD_RST reset generator output */
+#define RESET_STATUS1_LCD_RST_SHIFT (0)
+#define RESET_STATUS1_LCD_RST_MASK (0x3 << RESET_STATUS1_LCD_RST_SHIFT)
+#define RESET_STATUS1_LCD_RST(x) ((x) << RESET_STATUS1_LCD_RST_SHIFT)
+
+/* USB0_RST: Status of the USB0_RST reset generator output */
+#define RESET_STATUS1_USB0_RST_SHIFT (2)
+#define RESET_STATUS1_USB0_RST_MASK (0x3 << RESET_STATUS1_USB0_RST_SHIFT)
+#define RESET_STATUS1_USB0_RST(x) ((x) << RESET_STATUS1_USB0_RST_SHIFT)
+
+/* USB1_RST: Status of the USB1_RST reset generator output */
+#define RESET_STATUS1_USB1_RST_SHIFT (4)
+#define RESET_STATUS1_USB1_RST_MASK (0x3 << RESET_STATUS1_USB1_RST_SHIFT)
+#define RESET_STATUS1_USB1_RST(x) ((x) << RESET_STATUS1_USB1_RST_SHIFT)
+
+/* DMA_RST: Status of the DMA_RST reset generator output */
+#define RESET_STATUS1_DMA_RST_SHIFT (6)
+#define RESET_STATUS1_DMA_RST_MASK (0x3 << RESET_STATUS1_DMA_RST_SHIFT)
+#define RESET_STATUS1_DMA_RST(x) ((x) << RESET_STATUS1_DMA_RST_SHIFT)
+
+/* SDIO_RST: Status of the SDIO_RST reset generator output */
+#define RESET_STATUS1_SDIO_RST_SHIFT (8)
+#define RESET_STATUS1_SDIO_RST_MASK (0x3 << RESET_STATUS1_SDIO_RST_SHIFT)
+#define RESET_STATUS1_SDIO_RST(x) ((x) << RESET_STATUS1_SDIO_RST_SHIFT)
+
+/* EMC_RST: Status of the EMC_RST reset generator output */
+#define RESET_STATUS1_EMC_RST_SHIFT (10)
+#define RESET_STATUS1_EMC_RST_MASK (0x3 << RESET_STATUS1_EMC_RST_SHIFT)
+#define RESET_STATUS1_EMC_RST(x) ((x) << RESET_STATUS1_EMC_RST_SHIFT)
+
+/* ETHERNET_RST: Status of the ETHERNET_RST reset generator output */
+#define RESET_STATUS1_ETHERNET_RST_SHIFT (12)
+#define RESET_STATUS1_ETHERNET_RST_MASK \
+ (0x3 << RESET_STATUS1_ETHERNET_RST_SHIFT)
+#define RESET_STATUS1_ETHERNET_RST(x) ((x) << RESET_STATUS1_ETHERNET_RST_SHIFT)
+
+/* FLASHA_RST: Status of the FLASHA_RST reset generator output */
+#define RESET_STATUS1_FLASHA_RST_SHIFT (18)
+#define RESET_STATUS1_FLASHA_RST_MASK (0x3 << RESET_STATUS1_FLASHA_RST_SHIFT)
+#define RESET_STATUS1_FLASHA_RST(x) ((x) << RESET_STATUS1_FLASHA_RST_SHIFT)
+
+/* EEPROM_RST: Status of the EEPROM_RST reset generator output */
+#define RESET_STATUS1_EEPROM_RST_SHIFT (22)
+#define RESET_STATUS1_EEPROM_RST_MASK (0x3 << RESET_STATUS1_EEPROM_RST_SHIFT)
+#define RESET_STATUS1_EEPROM_RST(x) ((x) << RESET_STATUS1_EEPROM_RST_SHIFT)
+
+/* GPIO_RST: Status of the GPIO_RST reset generator output */
+#define RESET_STATUS1_GPIO_RST_SHIFT (24)
+#define RESET_STATUS1_GPIO_RST_MASK (0x3 << RESET_STATUS1_GPIO_RST_SHIFT)
+#define RESET_STATUS1_GPIO_RST(x) ((x) << RESET_STATUS1_GPIO_RST_SHIFT)
+
+/* FLASHB_RST: Status of the FLASHB_RST reset generator output */
+#define RESET_STATUS1_FLASHB_RST_SHIFT (26)
+#define RESET_STATUS1_FLASHB_RST_MASK (0x3 << RESET_STATUS1_FLASHB_RST_SHIFT)
+#define RESET_STATUS1_FLASHB_RST(x) ((x) << RESET_STATUS1_FLASHB_RST_SHIFT)
+
+/* --- RESET_STATUS2 values ------------------------------------- */
+
+/* TIMER0_RST: Status of the TIMER0_RST reset generator output */
+#define RESET_STATUS2_TIMER0_RST_SHIFT (0)
+#define RESET_STATUS2_TIMER0_RST_MASK (0x3 << RESET_STATUS2_TIMER0_RST_SHIFT)
+#define RESET_STATUS2_TIMER0_RST(x) ((x) << RESET_STATUS2_TIMER0_RST_SHIFT)
+
+/* TIMER1_RST: Status of the TIMER1_RST reset generator output */
+#define RESET_STATUS2_TIMER1_RST_SHIFT (2)
+#define RESET_STATUS2_TIMER1_RST_MASK (0x3 << RESET_STATUS2_TIMER1_RST_SHIFT)
+#define RESET_STATUS2_TIMER1_RST(x) ((x) << RESET_STATUS2_TIMER1_RST_SHIFT)
+
+/* TIMER2_RST: Status of the TIMER2_RST reset generator output */
+#define RESET_STATUS2_TIMER2_RST_SHIFT (4)
+#define RESET_STATUS2_TIMER2_RST_MASK (0x3 << RESET_STATUS2_TIMER2_RST_SHIFT)
+#define RESET_STATUS2_TIMER2_RST(x) ((x) << RESET_STATUS2_TIMER2_RST_SHIFT)
+
+/* TIMER3_RST: Status of the TIMER3_RST reset generator output */
+#define RESET_STATUS2_TIMER3_RST_SHIFT (6)
+#define RESET_STATUS2_TIMER3_RST_MASK (0x3 << RESET_STATUS2_TIMER3_RST_SHIFT)
+#define RESET_STATUS2_TIMER3_RST(x) ((x) << RESET_STATUS2_TIMER3_RST_SHIFT)
+
+/* RITIMER_RST: Status of the RITIMER_RST reset generator output */
+#define RESET_STATUS2_RITIMER_RST_SHIFT (8)
+#define RESET_STATUS2_RITIMER_RST_MASK (0x3 << RESET_STATUS2_RITIMER_RST_SHIFT)
+#define RESET_STATUS2_RITIMER_RST(x) ((x) << RESET_STATUS2_RITIMER_RST_SHIFT)
+
+/* SCT_RST: Status of the SCT_RST reset generator output */
+#define RESET_STATUS2_SCT_RST_SHIFT (10)
+#define RESET_STATUS2_SCT_RST_MASK (0x3 << RESET_STATUS2_SCT_RST_SHIFT)
+#define RESET_STATUS2_SCT_RST(x) ((x) << RESET_STATUS2_SCT_RST_SHIFT)
+
+/* MOTOCONPWM_RST: Status of the MOTOCONPWM_RST reset generator output */
+#define RESET_STATUS2_MOTOCONPWM_RST_SHIFT (12)
+#define RESET_STATUS2_MOTOCONPWM_RST_MASK \
+ (0x3 << RESET_STATUS2_MOTOCONPWM_RST_SHIFT)
+#define RESET_STATUS2_MOTOCONPWM_RST(x) \
+ ((x) << RESET_STATUS2_MOTOCONPWM_RST_SHIFT)
+
+/* QEI_RST: Status of the QEI_RST reset generator output */
+#define RESET_STATUS2_QEI_RST_SHIFT (14)
+#define RESET_STATUS2_QEI_RST_MASK (0x3 << RESET_STATUS2_QEI_RST_SHIFT)
+#define RESET_STATUS2_QEI_RST(x) ((x) << RESET_STATUS2_QEI_RST_SHIFT)
+
+/* ADC0_RST: Status of the ADC0_RST reset generator output */
+#define RESET_STATUS2_ADC0_RST_SHIFT (16)
+#define RESET_STATUS2_ADC0_RST_MASK (0x3 << RESET_STATUS2_ADC0_RST_SHIFT)
+#define RESET_STATUS2_ADC0_RST(x) ((x) << RESET_STATUS2_ADC0_RST_SHIFT)
+
+/* ADC1_RST: Status of the ADC1_RST reset generator output */
+#define RESET_STATUS2_ADC1_RST_SHIFT (18)
+#define RESET_STATUS2_ADC1_RST_MASK (0x3 << RESET_STATUS2_ADC1_RST_SHIFT)
+#define RESET_STATUS2_ADC1_RST(x) ((x) << RESET_STATUS2_ADC1_RST_SHIFT)
+
+/* DAC_RST: Status of the DAC_RST reset generator output */
+#define RESET_STATUS2_DAC_RST_SHIFT (20)
+#define RESET_STATUS2_DAC_RST_MASK (0x3 << RESET_STATUS2_DAC_RST_SHIFT)
+#define RESET_STATUS2_DAC_RST(x) ((x) << RESET_STATUS2_DAC_RST_SHIFT)
+
+/* UART0_RST: Status of the UART0_RST reset generator output */
+#define RESET_STATUS2_UART0_RST_SHIFT (24)
+#define RESET_STATUS2_UART0_RST_MASK (0x3 << RESET_STATUS2_UART0_RST_SHIFT)
+#define RESET_STATUS2_UART0_RST(x) ((x) << RESET_STATUS2_UART0_RST_SHIFT)
+
+/* UART1_RST: Status of the UART1_RST reset generator output */
+#define RESET_STATUS2_UART1_RST_SHIFT (26)
+#define RESET_STATUS2_UART1_RST_MASK (0x3 << RESET_STATUS2_UART1_RST_SHIFT)
+#define RESET_STATUS2_UART1_RST(x) ((x) << RESET_STATUS2_UART1_RST_SHIFT)
+
+/* UART2_RST: Status of the UART2_RST reset generator output */
+#define RESET_STATUS2_UART2_RST_SHIFT (28)
+#define RESET_STATUS2_UART2_RST_MASK (0x3 << RESET_STATUS2_UART2_RST_SHIFT)
+#define RESET_STATUS2_UART2_RST(x) ((x) << RESET_STATUS2_UART2_RST_SHIFT)
+
+/* UART3_RST: Status of the UART3_RST reset generator output */
+#define RESET_STATUS2_UART3_RST_SHIFT (30)
+#define RESET_STATUS2_UART3_RST_MASK (0x3 << RESET_STATUS2_UART3_RST_SHIFT)
+#define RESET_STATUS2_UART3_RST(x) ((x) << RESET_STATUS2_UART3_RST_SHIFT)
+
+/* --- RESET_STATUS3 values ------------------------------------- */
+
+/* I2C0_RST: Status of the I2C0_RST reset generator output */
+#define RESET_STATUS3_I2C0_RST_SHIFT (0)
+#define RESET_STATUS3_I2C0_RST_MASK (0x3 << RESET_STATUS3_I2C0_RST_SHIFT)
+#define RESET_STATUS3_I2C0_RST(x) ((x) << RESET_STATUS3_I2C0_RST_SHIFT)
+
+/* I2C1_RST: Status of the I2C1_RST reset generator output */
+#define RESET_STATUS3_I2C1_RST_SHIFT (2)
+#define RESET_STATUS3_I2C1_RST_MASK (0x3 << RESET_STATUS3_I2C1_RST_SHIFT)
+#define RESET_STATUS3_I2C1_RST(x) ((x) << RESET_STATUS3_I2C1_RST_SHIFT)
+
+/* SSP0_RST: Status of the SSP0_RST reset generator output */
+#define RESET_STATUS3_SSP0_RST_SHIFT (4)
+#define RESET_STATUS3_SSP0_RST_MASK (0x3 << RESET_STATUS3_SSP0_RST_SHIFT)
+#define RESET_STATUS3_SSP0_RST(x) ((x) << RESET_STATUS3_SSP0_RST_SHIFT)
+
+/* SSP1_RST: Status of the SSP1_RST reset generator output */
+#define RESET_STATUS3_SSP1_RST_SHIFT (6)
+#define RESET_STATUS3_SSP1_RST_MASK (0x3 << RESET_STATUS3_SSP1_RST_SHIFT)
+#define RESET_STATUS3_SSP1_RST(x) ((x) << RESET_STATUS3_SSP1_RST_SHIFT)
+
+/* I2S_RST: Status of the I2S_RST reset generator output */
+#define RESET_STATUS3_I2S_RST_SHIFT (8)
+#define RESET_STATUS3_I2S_RST_MASK (0x3 << RESET_STATUS3_I2S_RST_SHIFT)
+#define RESET_STATUS3_I2S_RST(x) ((x) << RESET_STATUS3_I2S_RST_SHIFT)
+
+/* SPIFI_RST: Status of the SPIFI_RST reset generator output */
+#define RESET_STATUS3_SPIFI_RST_SHIFT (10)
+#define RESET_STATUS3_SPIFI_RST_MASK (0x3 << RESET_STATUS3_SPIFI_RST_SHIFT)
+#define RESET_STATUS3_SPIFI_RST(x) ((x) << RESET_STATUS3_SPIFI_RST_SHIFT)
+
+/* CAN1_RST: Status of the CAN1_RST reset generator output */
+#define RESET_STATUS3_CAN1_RST_SHIFT (12)
+#define RESET_STATUS3_CAN1_RST_MASK (0x3 << RESET_STATUS3_CAN1_RST_SHIFT)
+#define RESET_STATUS3_CAN1_RST(x) ((x) << RESET_STATUS3_CAN1_RST_SHIFT)
+
+/* CAN0_RST: Status of the CAN0_RST reset generator output */
+#define RESET_STATUS3_CAN0_RST_SHIFT (14)
+#define RESET_STATUS3_CAN0_RST_MASK (0x3 << RESET_STATUS3_CAN0_RST_SHIFT)
+#define RESET_STATUS3_CAN0_RST(x) ((x) << RESET_STATUS3_CAN0_RST_SHIFT)
+
+/* M0APP_RST: Status of the M0APP_RST reset generator output */
+#define RESET_STATUS3_M0APP_RST_SHIFT (16)
+#define RESET_STATUS3_M0APP_RST_MASK (0x3 << RESET_STATUS3_M0APP_RST_SHIFT)
+#define RESET_STATUS3_M0APP_RST(x) ((x) << RESET_STATUS3_M0APP_RST_SHIFT)
+
+/* SGPIO_RST: Status of the SGPIO_RST reset generator output */
+#define RESET_STATUS3_SGPIO_RST_SHIFT (18)
+#define RESET_STATUS3_SGPIO_RST_MASK (0x3 << RESET_STATUS3_SGPIO_RST_SHIFT)
+#define RESET_STATUS3_SGPIO_RST(x) ((x) << RESET_STATUS3_SGPIO_RST_SHIFT)
+
+/* SPI_RST: Status of the SPI_RST reset generator output */
+#define RESET_STATUS3_SPI_RST_SHIFT (20)
+#define RESET_STATUS3_SPI_RST_MASK (0x3 << RESET_STATUS3_SPI_RST_SHIFT)
+#define RESET_STATUS3_SPI_RST(x) ((x) << RESET_STATUS3_SPI_RST_SHIFT)
+
+/* --- RESET_ACTIVE_STATUS0 values ------------------------------ */
+
+/* CORE_RST: Current status of the CORE_RST */
+#define RESET_ACTIVE_STATUS0_CORE_RST_SHIFT (0)
+#define RESET_ACTIVE_STATUS0_CORE_RST (1 << RESET_ACTIVE_STATUS0_CORE_RST_SHIFT)
+
+/* PERIPH_RST: Current status of the PERIPH_RST */
+#define RESET_ACTIVE_STATUS0_PERIPH_RST_SHIFT (1)
+#define RESET_ACTIVE_STATUS0_PERIPH_RST \
+ (1 << RESET_ACTIVE_STATUS0_PERIPH_RST_SHIFT)
+
+/* MASTER_RST: Current status of the MASTER_RST */
+#define RESET_ACTIVE_STATUS0_MASTER_RST_SHIFT (2)
+#define RESET_ACTIVE_STATUS0_MASTER_RST \
+ (1 << RESET_ACTIVE_STATUS0_MASTER_RST_SHIFT)
+
+/* WWDT_RST: Current status of the WWDT_RST */
+#define RESET_ACTIVE_STATUS0_WWDT_RST_SHIFT (4)
+#define RESET_ACTIVE_STATUS0_WWDT_RST (1 << RESET_ACTIVE_STATUS0_WWDT_RST_SHIFT)
+
+/* CREG_RST: Current status of the CREG_RST */
+#define RESET_ACTIVE_STATUS0_CREG_RST_SHIFT (5)
+#define RESET_ACTIVE_STATUS0_CREG_RST (1 << RESET_ACTIVE_STATUS0_CREG_RST_SHIFT)
+
+/* BUS_RST: Current status of the BUS_RST */
+#define RESET_ACTIVE_STATUS0_BUS_RST_SHIFT (8)
+#define RESET_ACTIVE_STATUS0_BUS_RST (1 << RESET_ACTIVE_STATUS0_BUS_RST_SHIFT)
+
+/* SCU_RST: Current status of the SCU_RST */
+#define RESET_ACTIVE_STATUS0_SCU_RST_SHIFT (9)
+#define RESET_ACTIVE_STATUS0_SCU_RST (1 << RESET_ACTIVE_STATUS0_SCU_RST_SHIFT)
+
+/* M4_RST: Current status of the M4_RST */
+#define RESET_ACTIVE_STATUS0_M4_RST_SHIFT (13)
+#define RESET_ACTIVE_STATUS0_M4_RST (1 << RESET_ACTIVE_STATUS0_M4_RST_SHIFT)
+
+/* LCD_RST: Current status of the LCD_RST */
+#define RESET_ACTIVE_STATUS0_LCD_RST_SHIFT (16)
+#define RESET_ACTIVE_STATUS0_LCD_RST (1 << RESET_ACTIVE_STATUS0_LCD_RST_SHIFT)
+
+/* USB0_RST: Current status of the USB0_RST */
+#define RESET_ACTIVE_STATUS0_USB0_RST_SHIFT (17)
+#define RESET_ACTIVE_STATUS0_USB0_RST (1 << RESET_ACTIVE_STATUS0_USB0_RST_SHIFT)
+
+/* USB1_RST: Current status of the USB1_RST */
+#define RESET_ACTIVE_STATUS0_USB1_RST_SHIFT (18)
+#define RESET_ACTIVE_STATUS0_USB1_RST (1 << RESET_ACTIVE_STATUS0_USB1_RST_SHIFT)
+
+/* DMA_RST: Current status of the DMA_RST */
+#define RESET_ACTIVE_STATUS0_DMA_RST_SHIFT (19)
+#define RESET_ACTIVE_STATUS0_DMA_RST (1 << RESET_ACTIVE_STATUS0_DMA_RST_SHIFT)
+
+/* SDIO_RST: Current status of the SDIO_RST */
+#define RESET_ACTIVE_STATUS0_SDIO_RST_SHIFT (20)
+#define RESET_ACTIVE_STATUS0_SDIO_RST (1 << RESET_ACTIVE_STATUS0_SDIO_RST_SHIFT)
+
+/* EMC_RST: Current status of the EMC_RST */
+#define RESET_ACTIVE_STATUS0_EMC_RST_SHIFT (21)
+#define RESET_ACTIVE_STATUS0_EMC_RST (1 << RESET_ACTIVE_STATUS0_EMC_RST_SHIFT)
+
+/* ETHERNET_RST: Current status of the ETHERNET_RST */
+#define RESET_ACTIVE_STATUS0_ETHERNET_RST_SHIFT (22)
+#define RESET_ACTIVE_STATUS0_ETHERNET_RST \
+ (1 << RESET_ACTIVE_STATUS0_ETHERNET_RST_SHIFT)
+
+/* FLASHA_RST: Current status of the FLASHA_RST */
+#define RESET_ACTIVE_STATUS0_FLASHA_RST_SHIFT (25)
+#define RESET_ACTIVE_STATUS0_FLASHA_RST \
+ (1 << RESET_ACTIVE_STATUS0_FLASHA_RST_SHIFT)
+
+/* EEPROM_RST: Current status of the EEPROM_RST */
+#define RESET_ACTIVE_STATUS0_EEPROM_RST_SHIFT (27)
+#define RESET_ACTIVE_STATUS0_EEPROM_RST \
+ (1 << RESET_ACTIVE_STATUS0_EEPROM_RST_SHIFT)
+
+/* GPIO_RST: Current status of the GPIO_RST */
+#define RESET_ACTIVE_STATUS0_GPIO_RST_SHIFT (28)
+#define RESET_ACTIVE_STATUS0_GPIO_RST (1 << RESET_ACTIVE_STATUS0_GPIO_RST_SHIFT)
+
+/* FLASHB_RST: Current status of the FLASHB_RST */
+#define RESET_ACTIVE_STATUS0_FLASHB_RST_SHIFT (29)
+#define RESET_ACTIVE_STATUS0_FLASHB_RST \
+ (1 << RESET_ACTIVE_STATUS0_FLASHB_RST_SHIFT)
+
+/* --- RESET_ACTIVE_STATUS1 values ------------------------------ */
+
+/* TIMER0_RST: Current status of the TIMER0_RST */
+#define RESET_ACTIVE_STATUS1_TIMER0_RST_SHIFT (0)
+#define RESET_ACTIVE_STATUS1_TIMER0_RST \
+ (1 << RESET_ACTIVE_STATUS1_TIMER0_RST_SHIFT)
+
+/* TIMER1_RST: Current status of the TIMER1_RST */
+#define RESET_ACTIVE_STATUS1_TIMER1_RST_SHIFT (1)
+#define RESET_ACTIVE_STATUS1_TIMER1_RST \
+ (1 << RESET_ACTIVE_STATUS1_TIMER1_RST_SHIFT)
+
+/* TIMER2_RST: Current status of the TIMER2_RST */
+#define RESET_ACTIVE_STATUS1_TIMER2_RST_SHIFT (2)
+#define RESET_ACTIVE_STATUS1_TIMER2_RST \
+ (1 << RESET_ACTIVE_STATUS1_TIMER2_RST_SHIFT)
+
+/* TIMER3_RST: Current status of the TIMER3_RST */
+#define RESET_ACTIVE_STATUS1_TIMER3_RST_SHIFT (3)
+#define RESET_ACTIVE_STATUS1_TIMER3_RST \
+ (1 << RESET_ACTIVE_STATUS1_TIMER3_RST_SHIFT)
+
+/* RITIMER_RST: Current status of the RITIMER_RST */
+#define RESET_ACTIVE_STATUS1_RITIMER_RST_SHIFT (4)
+#define RESET_ACTIVE_STATUS1_RITIMER_RST \
+ (1 << RESET_ACTIVE_STATUS1_RITIMER_RST_SHIFT)
+
+/* SCT_RST: Current status of the SCT_RST */
+#define RESET_ACTIVE_STATUS1_SCT_RST_SHIFT (5)
+#define RESET_ACTIVE_STATUS1_SCT_RST \
+ (1 << RESET_ACTIVE_STATUS1_SCT_RST_SHIFT)
+
+/* MOTOCONPWM_RST: Current status of the MOTOCONPWM_RST */
+#define RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_SHIFT (6)
+#define RESET_ACTIVE_STATUS1_MOTOCONPWM_RST \
+ (1 << RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_SHIFT)
+
+/* QEI_RST: Current status of the QEI_RST */
+#define RESET_ACTIVE_STATUS1_QEI_RST_SHIFT (7)
+#define RESET_ACTIVE_STATUS1_QEI_RST \
+ (1 << RESET_ACTIVE_STATUS1_QEI_RST_SHIFT)
+
+/* ADC0_RST: Current status of the ADC0_RST */
+#define RESET_ACTIVE_STATUS1_ADC0_RST_SHIFT (8)
+#define RESET_ACTIVE_STATUS1_ADC0_RST \
+ (1 << RESET_ACTIVE_STATUS1_ADC0_RST_SHIFT)
+
+/* ADC1_RST: Current status of the ADC1_RST */
+#define RESET_ACTIVE_STATUS1_ADC1_RST_SHIFT (9)
+#define RESET_ACTIVE_STATUS1_ADC1_RST \
+ (1 << RESET_ACTIVE_STATUS1_ADC1_RST_SHIFT)
+
+/* DAC_RST: Current status of the DAC_RST */
+#define RESET_ACTIVE_STATUS1_DAC_RST_SHIFT (10)
+#define RESET_ACTIVE_STATUS1_DAC_RST (1 << RESET_ACTIVE_STATUS1_DAC_RST_SHIFT)
+
+/* UART0_RST: Current status of the UART0_RST */
+#define RESET_ACTIVE_STATUS1_UART0_RST_SHIFT (12)
+#define RESET_ACTIVE_STATUS1_UART0_RST \
+ (1 << RESET_ACTIVE_STATUS1_UART0_RST_SHIFT)
+
+/* UART1_RST: Current status of the UART1_RST */
+#define RESET_ACTIVE_STATUS1_UART1_RST_SHIFT (13)
+#define RESET_ACTIVE_STATUS1_UART1_RST \
+ (1 << RESET_ACTIVE_STATUS1_UART1_RST_SHIFT)
+
+/* UART2_RST: Current status of the UART2_RST */
+#define RESET_ACTIVE_STATUS1_UART2_RST_SHIFT (14)
+#define RESET_ACTIVE_STATUS1_UART2_RST \
+ (1 << RESET_ACTIVE_STATUS1_UART2_RST_SHIFT)
+
+/* UART3_RST: Current status of the UART3_RST */
+#define RESET_ACTIVE_STATUS1_UART3_RST_SHIFT (15)
+#define RESET_ACTIVE_STATUS1_UART3_RST \
+ (1 << RESET_ACTIVE_STATUS1_UART3_RST_SHIFT)
+
+/* I2C0_RST: Current status of the I2C0_RST */
+#define RESET_ACTIVE_STATUS1_I2C0_RST_SHIFT (16)
+#define RESET_ACTIVE_STATUS1_I2C0_RST \
+ (1 << RESET_ACTIVE_STATUS1_I2C0_RST_SHIFT)
+
+/* I2C1_RST: Current status of the I2C1_RST */
+#define RESET_ACTIVE_STATUS1_I2C1_RST_SHIFT (17)
+#define RESET_ACTIVE_STATUS1_I2C1_RST \
+ (1 << RESET_ACTIVE_STATUS1_I2C1_RST_SHIFT)
+
+/* SSP0_RST: Current status of the SSP0_RST */
+#define RESET_ACTIVE_STATUS1_SSP0_RST_SHIFT (18)
+#define RESET_ACTIVE_STATUS1_SSP0_RST \
+ (1 << RESET_ACTIVE_STATUS1_SSP0_RST_SHIFT)
+
+/* SSP1_RST: Current status of the SSP1_RST */
+#define RESET_ACTIVE_STATUS1_SSP1_RST_SHIFT (19)
+#define RESET_ACTIVE_STATUS1_SSP1_RST \
+ (1 << RESET_ACTIVE_STATUS1_SSP1_RST_SHIFT)
+
+/* I2S_RST: Current status of the I2S_RST */
+#define RESET_ACTIVE_STATUS1_I2S_RST_SHIFT (20)
+#define RESET_ACTIVE_STATUS1_I2S_RST (1 << RESET_ACTIVE_STATUS1_I2S_RST_SHIFT)
+
+/* SPIFI_RST: Current status of the SPIFI_RST */
+#define RESET_ACTIVE_STATUS1_SPIFI_RST_SHIFT (21)
+#define RESET_ACTIVE_STATUS1_SPIFI_RST \
+ (1 << RESET_ACTIVE_STATUS1_SPIFI_RST_SHIFT)
+
+/* CAN1_RST: Current status of the CAN1_RST */
+#define RESET_ACTIVE_STATUS1_CAN1_RST_SHIFT (22)
+#define RESET_ACTIVE_STATUS1_CAN1_RST \
+ (1 << RESET_ACTIVE_STATUS1_CAN1_RST_SHIFT)
+
+/* CAN0_RST: Current status of the CAN0_RST */
+#define RESET_ACTIVE_STATUS1_CAN0_RST_SHIFT (23)
+#define RESET_ACTIVE_STATUS1_CAN0_RST \
+ (1 << RESET_ACTIVE_STATUS1_CAN0_RST_SHIFT)
+
+/* M0APP_RST: Current status of the M0APP_RST */
+#define RESET_ACTIVE_STATUS1_M0APP_RST_SHIFT (24)
+#define RESET_ACTIVE_STATUS1_M0APP_RST \
+ (1 << RESET_ACTIVE_STATUS1_M0APP_RST_SHIFT)
+
+/* SGPIO_RST: Current status of the SGPIO_RST */
+#define RESET_ACTIVE_STATUS1_SGPIO_RST_SHIFT (25)
+#define RESET_ACTIVE_STATUS1_SGPIO_RST \
+ (1 << RESET_ACTIVE_STATUS1_SGPIO_RST_SHIFT)
+
+/* SPI_RST: Current status of the SPI_RST */
+#define RESET_ACTIVE_STATUS1_SPI_RST_SHIFT (26)
+#define RESET_ACTIVE_STATUS1_SPI_RST (1 << RESET_ACTIVE_STATUS1_SPI_RST_SHIFT)
+
+/* --- RESET_EXT_STAT0 values ----------------------------------- */
+
+/* EXT_RESET: Reset activated by external reset from reset pin */
+#define RESET_EXT_STAT0_EXT_RESET_SHIFT (0)
+#define RESET_EXT_STAT0_EXT_RESET (1 << RESET_EXT_STAT0_EXT_RESET_SHIFT)
+
+/* BOD_RESET: Reset activated by BOD reset */
+#define RESET_EXT_STAT0_BOD_RESET_SHIFT (4)
+#define RESET_EXT_STAT0_BOD_RESET (1 << RESET_EXT_STAT0_BOD_RESET_SHIFT)
+
+/* WWDT_RESET: Reset activated by WWDT time-out */
+#define RESET_EXT_STAT0_WWDT_RESET_SHIFT (5)
+#define RESET_EXT_STAT0_WWDT_RESET (1 << RESET_EXT_STAT0_WWDT_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT1 values ----------------------------------- */
+
+/* CORE_RESET: Reset activated by CORE_RST output */
+#define RESET_EXT_STAT1_CORE_RESET_SHIFT (1)
+#define RESET_EXT_STAT1_CORE_RESET (1 << RESET_EXT_STAT1_CORE_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT2 values ----------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT2_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT2_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT2_PERIPHERAL_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT4 values ----------------------------------- */
+
+/* CORE_RESET: Reset activated by CORE_RST output */
+#define RESET_EXT_STAT4_CORE_RESET_SHIFT (1)
+#define RESET_EXT_STAT4_CORE_RESET (1 << RESET_EXT_STAT4_CORE_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT5 values ----------------------------------- */
+
+/* CORE_RESET: Reset activated by CORE_RST output */
+#define RESET_EXT_STAT5_CORE_RESET_SHIFT (1)
+#define RESET_EXT_STAT5_CORE_RESET (1 << RESET_EXT_STAT5_CORE_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT8 values ----------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT8_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT8_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT8_PERIPHERAL_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT9 values ----------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT9_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT9_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT9_PERIPHERAL_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT13 values ---------------------------------- */
+
+/* MASTER_RESET: Reset activated by MASTER_RST output */
+#define RESET_EXT_STAT13_MASTER_RESET_SHIFT (3)
+#define RESET_EXT_STAT13_MASTER_RESET (1 << RESET_EXT_STAT13_MASTER_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT16 values ---------------------------------- */
+
+/* MASTER_RESET: Reset activated by MASTER_RST output */
+#define RESET_EXT_STAT16_MASTER_RESET_SHIFT (3)
+#define RESET_EXT_STAT16_MASTER_RESET (1 << RESET_EXT_STAT16_MASTER_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT17 values ---------------------------------- */
+
+/* MASTER_RESET: Reset activated by MASTER_RST output */
+#define RESET_EXT_STAT17_MASTER_RESET_SHIFT (3)
+#define RESET_EXT_STAT17_MASTER_RESET (1 << RESET_EXT_STAT17_MASTER_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT18 values ---------------------------------- */
+
+/* MASTER_RESET: Reset activated by MASTER_RST output */
+#define RESET_EXT_STAT18_MASTER_RESET_SHIFT (3)
+#define RESET_EXT_STAT18_MASTER_RESET (1 << RESET_EXT_STAT18_MASTER_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT19 values ---------------------------------- */
+
+/* MASTER_RESET: Reset activated by MASTER_RST output */
+#define RESET_EXT_STAT19_MASTER_RESET_SHIFT (3)
+#define RESET_EXT_STAT19_MASTER_RESET (1 << RESET_EXT_STAT19_MASTER_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT20 values ---------------------------------- */
+
+/* MASTER_RESET: Reset activated by MASTER_RST output */
+#define RESET_EXT_STAT20_MASTER_RESET_SHIFT (3)
+#define RESET_EXT_STAT20_MASTER_RESET (1 << RESET_EXT_STAT20_MASTER_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT21 values ---------------------------------- */
+
+/* MASTER_RESET: Reset activated by MASTER_RST output */
+#define RESET_EXT_STAT21_MASTER_RESET_SHIFT (3)
+#define RESET_EXT_STAT21_MASTER_RESET (1 << RESET_EXT_STAT21_MASTER_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT22 values ---------------------------------- */
+
+/* MASTER_RESET: Reset activated by MASTER_RST output */
+#define RESET_EXT_STAT22_MASTER_RESET_SHIFT (3)
+#define RESET_EXT_STAT22_MASTER_RESET (1 << RESET_EXT_STAT22_MASTER_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT25 values ---------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT25_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT25_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT25_PERIPHERAL_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT27 values ---------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT27_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT27_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT27_PERIPHERAL_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT28 values ---------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT28_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT28_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT28_PERIPHERAL_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT29 values ---------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT29_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT29_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT29_PERIPHERAL_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT32 values ---------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT32_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT32_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT32_PERIPHERAL_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT33 values ---------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT33_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT33_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT33_PERIPHERAL_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT34 values ---------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT34_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT34_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT34_PERIPHERAL_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT35 values ---------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT35_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT35_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT35_PERIPHERAL_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT36 values ---------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT36_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT36_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT36_PERIPHERAL_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT37 values ---------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT37_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT37_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT37_PERIPHERAL_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT38 values ---------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT38_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT38_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT38_PERIPHERAL_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT39 values ---------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT39_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT39_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT39_PERIPHERAL_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT40 values ---------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT40_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT40_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT40_PERIPHERAL_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT41 values ---------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT41_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT41_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT41_PERIPHERAL_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT42 values ---------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT42_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT42_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT42_PERIPHERAL_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT44 values ---------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT44_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT44_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT44_PERIPHERAL_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT45 values ---------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT45_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT45_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT45_PERIPHERAL_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT46 values ---------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT46_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT46_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT46_PERIPHERAL_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT47 values ---------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT47_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT47_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT47_PERIPHERAL_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT48 values ---------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT48_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT48_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT48_PERIPHERAL_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT49 values ---------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT49_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT49_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT49_PERIPHERAL_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT50 values ---------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT50_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT50_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT50_PERIPHERAL_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT51 values ---------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT51_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT51_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT51_PERIPHERAL_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT52 values ---------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT52_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT52_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT52_PERIPHERAL_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT53 values ---------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT53_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT53_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT53_PERIPHERAL_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT54 values ---------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT54_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT54_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT54_PERIPHERAL_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT55 values ---------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT55_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT55_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT55_PERIPHERAL_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT56 values ---------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT56_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT56_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT56_PERIPHERAL_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT57 values ---------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT57_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT57_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT57_PERIPHERAL_RESET_SHIFT)
+
+/* --- RESET_EXT_STAT58 values ---------------------------------- */
+
+/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */
+#define RESET_EXT_STAT58_PERIPHERAL_RESET_SHIFT (2)
+#define RESET_EXT_STAT58_PERIPHERAL_RESET \
+ (1 << RESET_EXT_STAT58_PERIPHERAL_RESET_SHIFT)
+
+/**@}*/
+
+#endif
diff --git a/libopencm3/include/libopencm3/lpc43xx/ritimer.h b/libopencm3/include/libopencm3/lpc43xx/ritimer.h
new file mode 100644
index 0000000..e736bc3
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc43xx/ritimer.h
@@ -0,0 +1,59 @@
+/** @defgroup ritimer_defines Repetitive Interrupt Timer Defines
+
+@brief Defined Constants and Types for the LPC43xx Repetitive Interrupt
+Timer
+
+@ingroup LPC43xx_defines
+
+@version 1.0.0
+
+@author @htmlonly © @endhtmlonly 2012 Michael Ossmann
+
+@date 10 March 2013
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Michael Ossmann
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LPC43XX_RITIMER_H
+#define LPC43XX_RITIMER_H
+
+/**@{*/
+
+#include
+#include
+
+/* --- Repetitive Interrupt Timer registers -------------------------------- */
+
+/* Compare register */
+#define RITIMER_COMPVAL MMIO32(RITIMER_BASE + 0x000)
+
+/* Mask register */
+#define RITIMER_MASK MMIO32(RITIMER_BASE + 0x004)
+
+/* Control register */
+#define RITIMER_CTRL MMIO32(RITIMER_BASE + 0x008)
+
+/* 32-bit counter */
+#define RITIMER_COUNTER MMIO32(RITIMER_BASE + 0x00C)
+
+/**@}*/
+
+#endif
diff --git a/libopencm3/include/libopencm3/lpc43xx/scu.h b/libopencm3/include/libopencm3/lpc43xx/scu.h
new file mode 100644
index 0000000..b869318
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc43xx/scu.h
@@ -0,0 +1,780 @@
+/** @defgroup scu_defines System Control Unit Defines
+
+@brief Defined Constants and Types for the LPC43xx System Control Unit
+
+@ingroup LPC43xx_defines
+
+@version 1.0.0
+
+@author @htmlonly © @endhtmlonly 2012 Michael Ossmann
+
+@date 10 March 2013
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+* This file is part of the libopencm3 project.
+*
+* Copyright (C) 2012 Michael Ossmann
+* Copyright (C) 2012 Benjamin Vernoux
+*
+* This library is free software: you can redistribute it and/or modify
+* it under the terms of the GNU Lesser General Public License as published by
+* the Free Software Foundation, either version 3 of the License, or
+* (at your option) any later version.
+*
+* This library is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU Lesser General Public License for more details.
+*
+* You should have received a copy of the GNU Lesser General Public License
+* along with this library. If not, see .
+*/
+
+#ifndef LPC43XX_SCU_H
+#define LPC43XX_SCU_H
+
+/**@{*/
+
+#include
+#include
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* Pin group base addresses */
+#define PIN_GROUP0 (SCU_BASE + 0x000)
+#define PIN_GROUP1 (SCU_BASE + 0x080)
+#define PIN_GROUP2 (SCU_BASE + 0x100)
+#define PIN_GROUP3 (SCU_BASE + 0x180)
+#define PIN_GROUP4 (SCU_BASE + 0x200)
+#define PIN_GROUP5 (SCU_BASE + 0x280)
+#define PIN_GROUP6 (SCU_BASE + 0x300)
+#define PIN_GROUP7 (SCU_BASE + 0x380)
+#define PIN_GROUP8 (SCU_BASE + 0x400)
+#define PIN_GROUP9 (SCU_BASE + 0x480)
+#define PIN_GROUPA (SCU_BASE + 0x500)
+#define PIN_GROUPB (SCU_BASE + 0x580)
+#define PIN_GROUPC (SCU_BASE + 0x600)
+#define PIN_GROUPD (SCU_BASE + 0x680)
+#define PIN_GROUPE (SCU_BASE + 0x700)
+#define PIN_GROUPF (SCU_BASE + 0x780)
+
+#define PIN0 0x000
+#define PIN1 0x004
+#define PIN2 0x008
+#define PIN3 0x00C
+#define PIN4 0x010
+#define PIN5 0x014
+#define PIN6 0x018
+#define PIN7 0x01C
+#define PIN8 0x020
+#define PIN9 0x024
+#define PIN10 0x028
+#define PIN11 0x02C
+#define PIN12 0x030
+#define PIN13 0x034
+#define PIN14 0x038
+#define PIN15 0x03C
+#define PIN16 0x040
+#define PIN17 0x044
+#define PIN18 0x048
+#define PIN19 0x04C
+#define PIN20 0x050
+
+
+/* --- SCU registers ------------------------------------------------------- */
+
+/* Pin configuration registers */
+
+#define SCU_SFS(group, pin) MMIO32(group + pin)
+
+/* Pins P0_n */
+#define SCU_SFSP0_0 SCU_SFS(PIN_GROUP0, PIN0)
+#define SCU_SFSP0_1 SCU_SFS(PIN_GROUP0, PIN1)
+
+/* Pins P1_n */
+#define SCU_SFSP1_0 SCU_SFS(PIN_GROUP1, PIN0)
+#define SCU_SFSP1_1 SCU_SFS(PIN_GROUP1, PIN1)
+#define SCU_SFSP1_2 SCU_SFS(PIN_GROUP1, PIN2)
+#define SCU_SFSP1_3 SCU_SFS(PIN_GROUP1, PIN3)
+#define SCU_SFSP1_4 SCU_SFS(PIN_GROUP1, PIN4)
+#define SCU_SFSP1_5 SCU_SFS(PIN_GROUP1, PIN5)
+#define SCU_SFSP1_6 SCU_SFS(PIN_GROUP1, PIN6)
+#define SCU_SFSP1_7 SCU_SFS(PIN_GROUP1, PIN7)
+#define SCU_SFSP1_8 SCU_SFS(PIN_GROUP1, PIN8)
+#define SCU_SFSP1_9 SCU_SFS(PIN_GROUP1, PIN9)
+#define SCU_SFSP1_10 SCU_SFS(PIN_GROUP1, PIN10)
+#define SCU_SFSP1_11 SCU_SFS(PIN_GROUP1, PIN11)
+#define SCU_SFSP1_12 SCU_SFS(PIN_GROUP1, PIN12)
+#define SCU_SFSP1_13 SCU_SFS(PIN_GROUP1, PIN13)
+#define SCU_SFSP1_14 SCU_SFS(PIN_GROUP1, PIN14)
+#define SCU_SFSP1_15 SCU_SFS(PIN_GROUP1, PIN15)
+#define SCU_SFSP1_16 SCU_SFS(PIN_GROUP1, PIN16)
+#define SCU_SFSP1_17 SCU_SFS(PIN_GROUP1, PIN17)
+#define SCU_SFSP1_18 SCU_SFS(PIN_GROUP1, PIN18)
+#define SCU_SFSP1_19 SCU_SFS(PIN_GROUP1, PIN19)
+#define SCU_SFSP1_20 SCU_SFS(PIN_GROUP1, PIN20)
+
+/* Pins P2_n */
+#define SCU_SFSP2_0 SCU_SFS(PIN_GROUP2, PIN0)
+#define SCU_SFSP2_1 SCU_SFS(PIN_GROUP2, PIN1)
+#define SCU_SFSP2_2 SCU_SFS(PIN_GROUP2, PIN2)
+#define SCU_SFSP2_3 SCU_SFS(PIN_GROUP2, PIN3)
+#define SCU_SFSP2_4 SCU_SFS(PIN_GROUP2, PIN4)
+#define SCU_SFSP2_5 SCU_SFS(PIN_GROUP2, PIN5)
+#define SCU_SFSP2_6 SCU_SFS(PIN_GROUP2, PIN6)
+#define SCU_SFSP2_7 SCU_SFS(PIN_GROUP2, PIN7)
+#define SCU_SFSP2_8 SCU_SFS(PIN_GROUP2, PIN8)
+#define SCU_SFSP2_9 SCU_SFS(PIN_GROUP2, PIN9)
+#define SCU_SFSP2_10 SCU_SFS(PIN_GROUP2, PIN10)
+#define SCU_SFSP2_11 SCU_SFS(PIN_GROUP2, PIN11)
+#define SCU_SFSP2_12 SCU_SFS(PIN_GROUP2, PIN12)
+#define SCU_SFSP2_13 SCU_SFS(PIN_GROUP2, PIN13)
+
+/* Pins P3_n */
+#define SCU_SFSP3_0 SCU_SFS(PIN_GROUP3, PIN0)
+#define SCU_SFSP3_1 SCU_SFS(PIN_GROUP3, PIN1)
+#define SCU_SFSP3_2 SCU_SFS(PIN_GROUP3, PIN2)
+#define SCU_SFSP3_3 SCU_SFS(PIN_GROUP3, PIN3)
+#define SCU_SFSP3_4 SCU_SFS(PIN_GROUP3, PIN4)
+#define SCU_SFSP3_5 SCU_SFS(PIN_GROUP3, PIN5)
+#define SCU_SFSP3_6 SCU_SFS(PIN_GROUP3, PIN6)
+#define SCU_SFSP3_7 SCU_SFS(PIN_GROUP3, PIN7)
+#define SCU_SFSP3_8 SCU_SFS(PIN_GROUP3, PIN8)
+
+/* Pins P4_n */
+#define SCU_SFSP4_0 SCU_SFS(PIN_GROUP4, PIN0)
+#define SCU_SFSP4_1 SCU_SFS(PIN_GROUP4, PIN1)
+#define SCU_SFSP4_2 SCU_SFS(PIN_GROUP4, PIN2)
+#define SCU_SFSP4_3 SCU_SFS(PIN_GROUP4, PIN3)
+#define SCU_SFSP4_4 SCU_SFS(PIN_GROUP4, PIN4)
+#define SCU_SFSP4_5 SCU_SFS(PIN_GROUP4, PIN5)
+#define SCU_SFSP4_6 SCU_SFS(PIN_GROUP4, PIN6)
+#define SCU_SFSP4_7 SCU_SFS(PIN_GROUP4, PIN7)
+#define SCU_SFSP4_8 SCU_SFS(PIN_GROUP4, PIN8)
+#define SCU_SFSP4_9 SCU_SFS(PIN_GROUP4, PIN9)
+#define SCU_SFSP4_10 SCU_SFS(PIN_GROUP4, PIN10)
+
+/* Pins P5_n */
+#define SCU_SFSP5_0 SCU_SFS(PIN_GROUP5, PIN0)
+#define SCU_SFSP5_1 SCU_SFS(PIN_GROUP5, PIN1)
+#define SCU_SFSP5_2 SCU_SFS(PIN_GROUP5, PIN2)
+#define SCU_SFSP5_3 SCU_SFS(PIN_GROUP5, PIN3)
+#define SCU_SFSP5_4 SCU_SFS(PIN_GROUP5, PIN4)
+#define SCU_SFSP5_5 SCU_SFS(PIN_GROUP5, PIN5)
+#define SCU_SFSP5_6 SCU_SFS(PIN_GROUP5, PIN6)
+#define SCU_SFSP5_7 SCU_SFS(PIN_GROUP5, PIN7)
+
+/* Pins P6_n */
+#define SCU_SFSP6_0 SCU_SFS(PIN_GROUP6, PIN0)
+#define SCU_SFSP6_1 SCU_SFS(PIN_GROUP6, PIN1)
+#define SCU_SFSP6_2 SCU_SFS(PIN_GROUP6, PIN2)
+#define SCU_SFSP6_3 SCU_SFS(PIN_GROUP6, PIN3)
+#define SCU_SFSP6_4 SCU_SFS(PIN_GROUP6, PIN4)
+#define SCU_SFSP6_5 SCU_SFS(PIN_GROUP6, PIN5)
+#define SCU_SFSP6_6 SCU_SFS(PIN_GROUP6, PIN6)
+#define SCU_SFSP6_7 SCU_SFS(PIN_GROUP6, PIN7)
+#define SCU_SFSP6_8 SCU_SFS(PIN_GROUP6, PIN8)
+#define SCU_SFSP6_9 SCU_SFS(PIN_GROUP6, PIN9)
+#define SCU_SFSP6_10 SCU_SFS(PIN_GROUP6, PIN10)
+#define SCU_SFSP6_11 SCU_SFS(PIN_GROUP6, PIN11)
+#define SCU_SFSP6_12 SCU_SFS(PIN_GROUP6, PIN12)
+
+/* Pins P7_n */
+#define SCU_SFSP7_0 SCU_SFS(PIN_GROUP7, PIN0)
+#define SCU_SFSP7_1 SCU_SFS(PIN_GROUP7, PIN1)
+#define SCU_SFSP7_2 SCU_SFS(PIN_GROUP7, PIN2)
+#define SCU_SFSP7_3 SCU_SFS(PIN_GROUP7, PIN3)
+#define SCU_SFSP7_4 SCU_SFS(PIN_GROUP7, PIN4)
+#define SCU_SFSP7_5 SCU_SFS(PIN_GROUP7, PIN5)
+#define SCU_SFSP7_6 SCU_SFS(PIN_GROUP7, PIN6)
+#define SCU_SFSP7_7 SCU_SFS(PIN_GROUP7, PIN7)
+
+/* Pins P8_n */
+#define SCU_SFSP8_0 SCU_SFS(PIN_GROUP8, PIN0)
+#define SCU_SFSP8_1 SCU_SFS(PIN_GROUP8, PIN1)
+#define SCU_SFSP8_2 SCU_SFS(PIN_GROUP8, PIN2)
+#define SCU_SFSP8_3 SCU_SFS(PIN_GROUP8, PIN3)
+#define SCU_SFSP8_4 SCU_SFS(PIN_GROUP8, PIN4)
+#define SCU_SFSP8_5 SCU_SFS(PIN_GROUP8, PIN5)
+#define SCU_SFSP8_6 SCU_SFS(PIN_GROUP8, PIN6)
+#define SCU_SFSP8_7 SCU_SFS(PIN_GROUP8, PIN7)
+#define SCU_SFSP8_8 SCU_SFS(PIN_GROUP8, PIN8)
+
+/* Pins P9_n */
+#define SCU_SFSP9_0 SCU_SFS(PIN_GROUP9, PIN0)
+#define SCU_SFSP9_1 SCU_SFS(PIN_GROUP9, PIN1)
+#define SCU_SFSP9_2 SCU_SFS(PIN_GROUP9, PIN2)
+#define SCU_SFSP9_3 SCU_SFS(PIN_GROUP9, PIN3)
+#define SCU_SFSP9_4 SCU_SFS(PIN_GROUP9, PIN4)
+#define SCU_SFSP9_5 SCU_SFS(PIN_GROUP9, PIN5)
+#define SCU_SFSP9_6 SCU_SFS(PIN_GROUP9, PIN6)
+
+/* Pins PA_n */
+#define SCU_SFSPA_0 SCU_SFS(PIN_GROUPA, PIN0)
+#define SCU_SFSPA_1 SCU_SFS(PIN_GROUPA, PIN1)
+#define SCU_SFSPA_2 SCU_SFS(PIN_GROUPA, PIN2)
+#define SCU_SFSPA_3 SCU_SFS(PIN_GROUPA, PIN3)
+#define SCU_SFSPA_4 SCU_SFS(PIN_GROUPA, PIN4)
+
+/* Pins PB_n */
+#define SCU_SFSPB_0 SCU_SFS(PIN_GROUPB, PIN0)
+#define SCU_SFSPB_1 SCU_SFS(PIN_GROUPB, PIN1)
+#define SCU_SFSPB_2 SCU_SFS(PIN_GROUPB, PIN2)
+#define SCU_SFSPB_3 SCU_SFS(PIN_GROUPB, PIN3)
+#define SCU_SFSPB_4 SCU_SFS(PIN_GROUPB, PIN4)
+#define SCU_SFSPB_5 SCU_SFS(PIN_GROUPB, PIN5)
+#define SCU_SFSPB_6 SCU_SFS(PIN_GROUPB, PIN6)
+
+/* Pins PC_n */
+#define SCU_SFSPC_0 SCU_SFS(PIN_GROUPC, PIN0)
+#define SCU_SFSPC_1 SCU_SFS(PIN_GROUPC, PIN1)
+#define SCU_SFSPC_2 SCU_SFS(PIN_GROUPC, PIN2)
+#define SCU_SFSPC_3 SCU_SFS(PIN_GROUPC, PIN3)
+#define SCU_SFSPC_4 SCU_SFS(PIN_GROUPC, PIN4)
+#define SCU_SFSPC_5 SCU_SFS(PIN_GROUPC, PIN5)
+#define SCU_SFSPC_6 SCU_SFS(PIN_GROUPC, PIN6)
+#define SCU_SFSPC_7 SCU_SFS(PIN_GROUPC, PIN7)
+#define SCU_SFSPC_8 SCU_SFS(PIN_GROUPC, PIN8)
+#define SCU_SFSPC_9 SCU_SFS(PIN_GROUPC, PIN9)
+#define SCU_SFSPC_10 SCU_SFS(PIN_GROUPC, PIN10)
+#define SCU_SFSPC_11 SCU_SFS(PIN_GROUPC, PIN11)
+#define SCU_SFSPC_12 SCU_SFS(PIN_GROUPC, PIN12)
+#define SCU_SFSPC_13 SCU_SFS(PIN_GROUPC, PIN13)
+#define SCU_SFSPC_14 SCU_SFS(PIN_GROUPC, PIN14)
+
+/* Pins PD_n */
+#define SCU_SFSPD_0 SCU_SFS(PIN_GROUPD, PIN0)
+#define SCU_SFSPD_1 SCU_SFS(PIN_GROUPD, PIN1)
+#define SCU_SFSPD_2 SCU_SFS(PIN_GROUPD, PIN2)
+#define SCU_SFSPD_3 SCU_SFS(PIN_GROUPD, PIN3)
+#define SCU_SFSPD_4 SCU_SFS(PIN_GROUPD, PIN4)
+#define SCU_SFSPD_5 SCU_SFS(PIN_GROUPD, PIN5)
+#define SCU_SFSPD_6 SCU_SFS(PIN_GROUPD, PIN6)
+#define SCU_SFSPD_7 SCU_SFS(PIN_GROUPD, PIN7)
+#define SCU_SFSPD_8 SCU_SFS(PIN_GROUPD, PIN8)
+#define SCU_SFSPD_9 SCU_SFS(PIN_GROUPD, PIN9)
+#define SCU_SFSPD_10 SCU_SFS(PIN_GROUPD, PIN10)
+#define SCU_SFSPD_11 SCU_SFS(PIN_GROUPD, PIN11)
+#define SCU_SFSPD_12 SCU_SFS(PIN_GROUPD, PIN12)
+#define SCU_SFSPD_13 SCU_SFS(PIN_GROUPD, PIN13)
+#define SCU_SFSPD_14 SCU_SFS(PIN_GROUPD, PIN14)
+#define SCU_SFSPD_15 SCU_SFS(PIN_GROUPD, PIN15)
+#define SCU_SFSPD_16 SCU_SFS(PIN_GROUPD, PIN16)
+
+/* Pins PE_n */
+#define SCU_SFSPE_0 SCU_SFS(PIN_GROUPE, PIN0)
+#define SCU_SFSPE_1 SCU_SFS(PIN_GROUPE, PIN1)
+#define SCU_SFSPE_2 SCU_SFS(PIN_GROUPE, PIN2)
+#define SCU_SFSPE_3 SCU_SFS(PIN_GROUPE, PIN3)
+#define SCU_SFSPE_4 SCU_SFS(PIN_GROUPE, PIN4)
+#define SCU_SFSPE_5 SCU_SFS(PIN_GROUPE, PIN5)
+#define SCU_SFSPE_6 SCU_SFS(PIN_GROUPE, PIN6)
+#define SCU_SFSPE_7 SCU_SFS(PIN_GROUPE, PIN7)
+#define SCU_SFSPE_8 SCU_SFS(PIN_GROUPE, PIN8)
+#define SCU_SFSPE_9 SCU_SFS(PIN_GROUPE, PIN9)
+#define SCU_SFSPE_10 SCU_SFS(PIN_GROUPE, PIN10)
+#define SCU_SFSPE_11 SCU_SFS(PIN_GROUPE, PIN11)
+#define SCU_SFSPE_12 SCU_SFS(PIN_GROUPE, PIN12)
+#define SCU_SFSPE_13 SCU_SFS(PIN_GROUPE, PIN13)
+#define SCU_SFSPE_14 SCU_SFS(PIN_GROUPE, PIN14)
+#define SCU_SFSPE_15 SCU_SFS(PIN_GROUPE, PIN15)
+
+/* Pins PF_n */
+#define SCU_SFSPF_0 SCU_SFS(PIN_GROUPF, PIN0)
+#define SCU_SFSPF_1 SCU_SFS(PIN_GROUPF, PIN1)
+#define SCU_SFSPF_2 SCU_SFS(PIN_GROUPF, PIN2)
+#define SCU_SFSPF_3 SCU_SFS(PIN_GROUPF, PIN3)
+#define SCU_SFSPF_4 SCU_SFS(PIN_GROUPF, PIN4)
+#define SCU_SFSPF_5 SCU_SFS(PIN_GROUPF, PIN5)
+#define SCU_SFSPF_6 SCU_SFS(PIN_GROUPF, PIN6)
+#define SCU_SFSPF_7 SCU_SFS(PIN_GROUPF, PIN7)
+#define SCU_SFSPF_8 SCU_SFS(PIN_GROUPF, PIN8)
+#define SCU_SFSPF_9 SCU_SFS(PIN_GROUPF, PIN9)
+#define SCU_SFSPF_10 SCU_SFS(PIN_GROUPF, PIN10)
+#define SCU_SFSPF_11 SCU_SFS(PIN_GROUPF, PIN11)
+
+/* CLKn pins */
+#define SCU_SFSCLK0 MMIO32(SCU_BASE + 0xC00)
+#define SCU_SFSCLK1 MMIO32(SCU_BASE + 0xC04)
+#define SCU_SFSCLK2 MMIO32(SCU_BASE + 0xC08)
+#define SCU_SFSCLK3 MMIO32(SCU_BASE + 0xC0C)
+
+/* USB1 USB1_DP/USB1_DM pins and I2C-bus open-drain pins */
+#define SCU_SFSUSB MMIO32(SCU_BASE + 0xC80)
+#define SCU_SFSI2C0 MMIO32(SCU_BASE + 0xC84)
+
+/* ADC pin select registers */
+
+/* ADC0 function select register */
+#define SCU_ENAIO0 MMIO32(SCU_BASE + 0xC88)
+
+/* ADC1 function select register */
+#define SCU_ENAIO1 MMIO32(SCU_BASE + 0xC8C)
+
+/* Analog function select register */
+#define SCU_ENAIO2 MMIO32(SCU_BASE + 0xC90)
+
+/* EMC clock delay register */
+#define SCU_EMCDELAYCLK MMIO32(SCU_BASE + 0xD00)
+
+/* Pin interrupt select registers */
+
+/* Pin interrupt select register for pin interrupts 0 to 3 */
+#define SCU_PINTSEL0 MMIO32(SCU_BASE + 0xE00)
+
+/* Pin interrupt select register for pin interrupts 4 to 7 */
+#define SCU_PINTSEL1 MMIO32(SCU_BASE + 0xE04)
+
+/**************************/
+/* SCU I2C0 Configuration */
+/**************************/
+/*
+* Select input glitch filter time constant for the SCL pin.
+* 0 = 50 ns glitch filter.
+* 1 = 3ns glitch filter.
+*/
+#define SCU_SCL_EFP (BIT0)
+
+/* BIT1 Reserved. Always write a 0 to this bit. */
+
+/*
+* Select I2C mode for the SCL pin.
+* 0 = Standard/Fast mode transmit.
+* 1 = Fast-mode Plus transmit.
+*/
+#define SCU_SCL_EHD (BIT2)
+
+/*
+* Enable the input receiver for the SCL pin.
+* Always write a 1 to this bit when using the
+* I2C0.
+* 0 = Disabled.
+* 1 = Enabled.
+*/
+#define SCU_SCL_EZI_EN (BIT3)
+
+/* BIT4-6 Reserved. */
+
+/*
+* Enable or disable input glitch filter for the
+* SCL pin. The filter time constant is
+* determined by bit EFP.
+* 0 = Enable input filter.
+* 1 = Disable input filter.
+*/
+#define SCU_SCL_ZIF_DIS (BIT7)
+
+/*
+* Select input glitch filter time constant for the SDA pin.
+* 0 = 50 ns glitch filter.
+* 1 = 3ns glitch filter.
+*/
+#define SCU_SDA_EFP (BIT8)
+
+/* BIT9 Reserved. Always write a 0 to this bit. */
+
+/*
+* Select I2C mode for the SDA pin.
+* 0 = Standard/Fast mode transmit.
+* 1 = Fast-mode Plus transmit.
+*/
+#define SCU_SDA_EHD (BIT10)
+
+/*
+* Enable the input receiver for the SDA pin.
+* Always write a 1 to this bit when using the
+* I2C0.
+* 0 = Disabled.
+* 1 = Enabled.
+*/
+#define SCU_SDA_EZI_EN (BIT11)
+
+/* BIT 12-14 - Reserved */
+
+/*
+* Enable or disable input glitch filter for the
+* SDA pin. The filter time constant is
+* determined by bit SDA_EFP.
+* 0 = Enable input filter.
+* 1 = Disable input filter.
+*/
+#define SCU_SDA_ZIF_DIS (BIT15)
+
+/* Standard mode for I2C SCL/SDA Standard/Fast mode */
+#define SCU_I2C0_NOMINAL (SCU_SCL_EZI_EN | SCU_SDA_EZI_EN)
+
+/* Standard mode for I2C SCL/SDA Fast-mode Plus transmit */
+#define SCU_I2C0_FAST (SCU_SCL_EFP | SCU_SCL_EHD | SCU_SCL_EZI_EN | \
+ SCU_SCL_ZIF_DIS | SCU_SDA_EFP | SCU_SDA_EHD | \
+ SCU_SDA_EZI_EN)
+
+/*
+* SCU PIN Normal Drive:
+* The configuration registers for normal-drive pins control the following pins:
+* - P0_0 and P0_1
+* - P1_0 to P1_16 and P1_18 to P1_20
+* - P2_0 to P2_2 and P2_6 to P2_13
+* - P3_0 to P3_2 and P3_4 to P3_8
+* - P4_0 to P4_10
+* - P5_0 to P5_7
+* - P6_0 to P6_12
+* - P7_0 to P7_7
+* - P8_3 to P8_8
+* - P9_0 to P9_6
+* - PA_0 and PA_4
+* - PB_0 to PB_6
+* - PC_0 to PC_14
+* - PE_0 to PE_15
+* - PF_0 to PF_11
+*
+* Pin configuration registers for High-Drive pins.
+* The configuration registers for high-drive pins control the following pins:
+* - P1_17
+* - P2_3 to P2_5
+* - P8_0 to P8_2
+* - PA_1 to PA_3
+*
+* Pin configuration registers for High-Speed pins.
+* This register controls the following pins:
+* - P3_3 and pins CLK0 to CLK3.
+*/
+typedef enum {
+ /* Group Port 0 */
+ P0_0 = (PIN_GROUP0+PIN0),
+ P0_1 = (PIN_GROUP0+PIN1),
+
+ /* Group Port 1 */
+ P1_0 = (PIN_GROUP1+PIN0),
+ P1_1 = (PIN_GROUP1+PIN1),
+ P1_2 = (PIN_GROUP1+PIN2),
+ P1_3 = (PIN_GROUP1+PIN3),
+ P1_4 = (PIN_GROUP1+PIN4),
+ P1_5 = (PIN_GROUP1+PIN5),
+ P1_6 = (PIN_GROUP1+PIN6),
+ P1_7 = (PIN_GROUP1+PIN7),
+ P1_8 = (PIN_GROUP1+PIN8),
+ P1_9 = (PIN_GROUP1+PIN9),
+ P1_10 = (PIN_GROUP1+PIN10),
+ P1_11 = (PIN_GROUP1+PIN11),
+ P1_12 = (PIN_GROUP1+PIN12),
+ P1_13 = (PIN_GROUP1+PIN13),
+ P1_14 = (PIN_GROUP1+PIN14),
+ P1_15 = (PIN_GROUP1+PIN15),
+ P1_16 = (PIN_GROUP1+PIN16),
+
+ /* P1_17 is High-Drive pin */
+ P1_17 = (PIN_GROUP1+PIN17),
+
+ P1_18 = (PIN_GROUP1+PIN18),
+ P1_19 = (PIN_GROUP1+PIN19),
+ P1_20 = (PIN_GROUP1+PIN20),
+
+ /* Group Port 2 */
+ P2_0 = (PIN_GROUP2+PIN0),
+ P2_1 = (PIN_GROUP2+PIN1),
+ P2_2 = (PIN_GROUP2+PIN2),
+
+ /* P2_3 to P2_5 are High-Drive pins */
+ P2_3 = (PIN_GROUP2+PIN3),
+ P2_4 = (PIN_GROUP2+PIN4),
+ P2_5 = (PIN_GROUP2+PIN5),
+
+ P2_6 = (PIN_GROUP2+PIN6),
+ P2_7 = (PIN_GROUP2+PIN7),
+ P2_8 = (PIN_GROUP2+PIN8),
+ P2_9 = (PIN_GROUP2+PIN9),
+ P2_10 = (PIN_GROUP2+PIN10),
+ P2_11 = (PIN_GROUP2+PIN11),
+ P2_12 = (PIN_GROUP2+PIN12),
+ P2_13 = (PIN_GROUP2+PIN13),
+
+ /* Group Port 3 */
+ P3_0 = (PIN_GROUP3+PIN0),
+ P3_1 = (PIN_GROUP3+PIN1),
+ P3_2 = (PIN_GROUP3+PIN2),
+
+ /* P3_3 is High-Speed pin */
+ P3_3 = (PIN_GROUP3+PIN3),
+
+ P3_4 = (PIN_GROUP3+PIN4),
+ P3_5 = (PIN_GROUP3+PIN5),
+ P3_6 = (PIN_GROUP3+PIN6),
+ P3_7 = (PIN_GROUP3+PIN7),
+ P3_8 = (PIN_GROUP3+PIN8),
+
+ /* Group Port 4 */
+ P4_0 = (PIN_GROUP4+PIN0),
+ P4_1 = (PIN_GROUP4+PIN1),
+ P4_2 = (PIN_GROUP4+PIN2),
+ P4_3 = (PIN_GROUP4+PIN3),
+ P4_4 = (PIN_GROUP4+PIN4),
+ P4_5 = (PIN_GROUP4+PIN5),
+ P4_6 = (PIN_GROUP4+PIN6),
+ P4_7 = (PIN_GROUP4+PIN7),
+ P4_8 = (PIN_GROUP4+PIN8),
+ P4_9 = (PIN_GROUP4+PIN9),
+ P4_10 = (PIN_GROUP4+PIN10),
+
+ /* Group Port 5 */
+ P5_0 = (PIN_GROUP5+PIN0),
+ P5_1 = (PIN_GROUP5+PIN1),
+ P5_2 = (PIN_GROUP5+PIN2),
+ P5_3 = (PIN_GROUP5+PIN3),
+ P5_4 = (PIN_GROUP5+PIN4),
+ P5_5 = (PIN_GROUP5+PIN5),
+ P5_6 = (PIN_GROUP5+PIN6),
+ P5_7 = (PIN_GROUP5+PIN7),
+
+ /* Group Port 6 */
+ P6_0 = (PIN_GROUP6+PIN0),
+ P6_1 = (PIN_GROUP6+PIN1),
+ P6_2 = (PIN_GROUP6+PIN2),
+ P6_3 = (PIN_GROUP6+PIN3),
+ P6_4 = (PIN_GROUP6+PIN4),
+ P6_5 = (PIN_GROUP6+PIN5),
+ P6_6 = (PIN_GROUP6+PIN6),
+ P6_7 = (PIN_GROUP6+PIN7),
+ P6_8 = (PIN_GROUP6+PIN8),
+ P6_9 = (PIN_GROUP6+PIN9),
+ P6_10 = (PIN_GROUP6+PIN10),
+ P6_11 = (PIN_GROUP6+PIN11),
+ P6_12 = (PIN_GROUP6+PIN12),
+
+ /* Group Port 7 */
+ P7_0 = (PIN_GROUP7+PIN0),
+ P7_1 = (PIN_GROUP7+PIN1),
+ P7_2 = (PIN_GROUP7+PIN2),
+ P7_3 = (PIN_GROUP7+PIN3),
+ P7_4 = (PIN_GROUP7+PIN4),
+ P7_5 = (PIN_GROUP7+PIN5),
+ P7_6 = (PIN_GROUP7+PIN6),
+ P7_7 = (PIN_GROUP7+PIN7),
+
+ /* Group Port 8 */
+ /* P8_0 to P8_2 are High-Drive pins */
+ P8_0 = (PIN_GROUP8+PIN0),
+ P8_1 = (PIN_GROUP8+PIN1),
+ P8_2 = (PIN_GROUP8+PIN2),
+
+ P8_3 = (PIN_GROUP8+PIN3),
+ P8_4 = (PIN_GROUP8+PIN4),
+ P8_5 = (PIN_GROUP8+PIN5),
+ P8_6 = (PIN_GROUP8+PIN6),
+ P8_7 = (PIN_GROUP8+PIN7),
+ P8_8 = (PIN_GROUP8+PIN8),
+
+ /* Group Port 9 */
+ P9_0 = (PIN_GROUP9+PIN0),
+ P9_1 = (PIN_GROUP9+PIN1),
+ P9_2 = (PIN_GROUP9+PIN2),
+ P9_3 = (PIN_GROUP9+PIN3),
+ P9_4 = (PIN_GROUP9+PIN4),
+ P9_5 = (PIN_GROUP9+PIN5),
+ P9_6 = (PIN_GROUP9+PIN6),
+
+ /* Group Port A */
+ PA_0 = (PIN_GROUPA+PIN0),
+ /* PA_1 to PA_3 are Normal & High-Drive Pins */
+ PA_1 = (PIN_GROUPA+PIN1),
+ PA_2 = (PIN_GROUPA+PIN2),
+ PA_3 = (PIN_GROUPA+PIN3),
+ PA_4 = (PIN_GROUPA+PIN4),
+
+ /* Group Port B */
+ PB_0 = (PIN_GROUPB+PIN0),
+ PB_1 = (PIN_GROUPB+PIN1),
+ PB_2 = (PIN_GROUPB+PIN2),
+ PB_3 = (PIN_GROUPB+PIN3),
+ PB_4 = (PIN_GROUPB+PIN4),
+ PB_5 = (PIN_GROUPB+PIN5),
+ PB_6 = (PIN_GROUPB+PIN6),
+
+ /* Group Port C */
+ PC_0 = (PIN_GROUPC+PIN0),
+ PC_1 = (PIN_GROUPC+PIN1),
+ PC_2 = (PIN_GROUPC+PIN2),
+ PC_3 = (PIN_GROUPC+PIN3),
+ PC_4 = (PIN_GROUPC+PIN4),
+ PC_5 = (PIN_GROUPC+PIN5),
+ PC_6 = (PIN_GROUPC+PIN6),
+ PC_7 = (PIN_GROUPC+PIN7),
+ PC_8 = (PIN_GROUPC+PIN8),
+ PC_9 = (PIN_GROUPC+PIN9),
+ PC_10 = (PIN_GROUPC+PIN10),
+ PC_11 = (PIN_GROUPC+PIN11),
+ PC_12 = (PIN_GROUPC+PIN12),
+ PC_13 = (PIN_GROUPC+PIN13),
+ PC_14 = (PIN_GROUPC+PIN14),
+
+ /* Group Port D (seems not configurable through SCU, not defined in
+ * UM10503.pdf Rev.1, keep it here)
+ */
+ PD_0 = (PIN_GROUPD+PIN0),
+ PD_1 = (PIN_GROUPD+PIN1),
+ PD_2 = (PIN_GROUPD+PIN2),
+ PD_3 = (PIN_GROUPD+PIN3),
+ PD_4 = (PIN_GROUPD+PIN4),
+ PD_5 = (PIN_GROUPD+PIN5),
+ PD_6 = (PIN_GROUPD+PIN6),
+ PD_7 = (PIN_GROUPD+PIN7),
+ PD_8 = (PIN_GROUPD+PIN8),
+ PD_9 = (PIN_GROUPD+PIN9),
+ PD_10 = (PIN_GROUPD+PIN10),
+ PD_11 = (PIN_GROUPD+PIN11),
+ PD_12 = (PIN_GROUPD+PIN12),
+ PD_13 = (PIN_GROUPD+PIN13),
+ PD_14 = (PIN_GROUPD+PIN14),
+ PD_15 = (PIN_GROUPD+PIN15),
+ PD_16 = (PIN_GROUPD+PIN16),
+
+ /* Group Port E */
+ PE_0 = (PIN_GROUPE+PIN0),
+ PE_1 = (PIN_GROUPE+PIN1),
+ PE_2 = (PIN_GROUPE+PIN2),
+ PE_3 = (PIN_GROUPE+PIN3),
+ PE_4 = (PIN_GROUPE+PIN4),
+ PE_5 = (PIN_GROUPE+PIN5),
+ PE_6 = (PIN_GROUPE+PIN6),
+ PE_7 = (PIN_GROUPE+PIN7),
+ PE_8 = (PIN_GROUPE+PIN8),
+ PE_9 = (PIN_GROUPE+PIN9),
+ PE_10 = (PIN_GROUPE+PIN10),
+ PE_11 = (PIN_GROUPE+PIN11),
+ PE_12 = (PIN_GROUPE+PIN12),
+ PE_13 = (PIN_GROUPE+PIN13),
+ PE_14 = (PIN_GROUPE+PIN14),
+ PE_15 = (PIN_GROUPE+PIN15),
+
+ /* Group Port F */
+ PF_0 = (PIN_GROUPF+PIN0),
+ PF_1 = (PIN_GROUPF+PIN1),
+ PF_2 = (PIN_GROUPF+PIN2),
+ PF_3 = (PIN_GROUPF+PIN3),
+ PF_4 = (PIN_GROUPF+PIN4),
+ PF_5 = (PIN_GROUPF+PIN5),
+ PF_6 = (PIN_GROUPF+PIN6),
+ PF_7 = (PIN_GROUPF+PIN7),
+ PF_8 = (PIN_GROUPF+PIN8),
+ PF_9 = (PIN_GROUPF+PIN9),
+ PF_10 = (PIN_GROUPF+PIN10),
+ PF_11 = (PIN_GROUPF+PIN11),
+
+ /* Group Clock 0 to 3 High-Speed pins */
+ CLK0 = (SCU_BASE + 0xC00),
+ CLK1 = (SCU_BASE + 0xC04),
+ CLK2 = (SCU_BASE + 0xC08),
+ CLK3 = (SCU_BASE + 0xC0C)
+
+} scu_grp_pin_t;
+
+/*
+* Pin Configuration to be used for scu_pinmux() parameter scu_conf
+* For normal-drive pins, high-drive pins, high-speed pins
+*/
+/*
+* Function BIT0 to 2.
+* Common to normal-drive pins, high-drive pins, high-speed pins.
+*/
+#define SCU_CONF_FUNCTION0 (0x0)
+#define SCU_CONF_FUNCTION1 (0x1)
+#define SCU_CONF_FUNCTION2 (0x2)
+#define SCU_CONF_FUNCTION3 (0x3)
+#define SCU_CONF_FUNCTION4 (0x4)
+#define SCU_CONF_FUNCTION5 (0x5)
+#define SCU_CONF_FUNCTION6 (0x6)
+#define SCU_CONF_FUNCTION7 (0x7)
+
+/*
+* Enable pull-down resistor at pad
+* By default=0 Disable pull-down.
+* Available to normal-drive pins, high-drive pins, high-speed pins
+*/
+#define SCU_CONF_EPD_EN_PULLDOWN (BIT3)
+
+/*
+* Disable pull-up resistor at pad.
+* By default=0 the pull-up resistor is enabled at reset.
+* Available to normal-drive pins, high-drive pins, high-speed pins
+*/
+#define SCU_CONF_EPUN_DIS_PULLUP (BIT4)
+
+/*
+* Select Slew Rate.
+* By Default=0 Slow.
+* Available to normal-drive and high-speed pins, reserved for high-drive pins.
+*/
+#define SCU_CONF_EHS_FAST (BIT5)
+
+/*
+* Input buffer enable.
+* By Default=0 Disable Input Buffer.
+* The input buffer is disabled by default at reset and must be enabled for
+* receiving(in normal/highspeed-drive) or to transfer data from the I/O buffer
+* to the pad(in high-drive pins).
+* Available to normal-drive pins, high-drive pins, high-speed pins.
+*/
+#define SCU_CONF_EZI_EN_IN_BUFFER (BIT6)
+
+/*
+* Input glitch filter. Disable the input glitch filter for clocking signals
+* higher than 30 MHz.
+* Available to normal-drive pins, high-drive pins, high-speed pins.
+*/
+#define SCU_CONF_ZIF_DIS_IN_GLITCH_FILT (BIT7)
+
+/*
+* Select drive strength. (default=0 Normal-drive: 4 mA drive strength) (BIT8/9).
+* Available to high-drive pins, reserved for others.
+*/
+#define SCU_CONF_EHD_NORMAL_DRIVE_8MILLIA (0x100)
+#define SCU_CONF_EHD_NORMAL_DRIVE_14MILLIA (0x200)
+#define SCU_CONF_EHD_NORMAL_DRIVE_20MILLIA (0x300)
+
+/* BIT10 to 31 are Reserved */
+
+/* Configuration for different I/O pins types */
+#define SCU_EMC_IO (SCU_CONF_EPD_EN_PULLDOWN | \
+ SCU_CONF_EHS_FAST | \
+ SCU_CONF_EZI_EN_IN_BUFFER | \
+ SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
+#define SCU_LCD (SCU_CONF_EPUN_DIS_PULLUP | \
+ SCU_CONF_EHS_FAST | \
+ SCU_CONF_EZI_EN_IN_BUFFER | \
+ SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
+#define SCU_CLK_IN (SCU_CONF_EPD_EN_PULLDOWN | \
+ SCU_CONF_EHS_FAST | \
+ SCU_CONF_EZI_EN_IN_BUFFER | \
+ SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
+#define SCU_CLK_OUT (SCU_CONF_EPD_EN_PULLDOWN | \
+ SCU_CONF_EHS_FAST | \
+ SCU_CONF_EZI_EN_IN_BUFFER | \
+ SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
+#define SCU_GPIO_PUP (SCU_CONF_EZI_EN_IN_BUFFER)
+#define SCU_GPIO_PDN (SCU_CONF_EPUN_DIS_PULLUP | \
+ SCU_CONF_EPD_EN_PULLDOWN | \
+ SCU_CONF_EZI_EN_IN_BUFFER)
+#define SCU_GPIO_NOPULL (SCU_CONF_EPUN_DIS_PULLUP | \
+ SCU_CONF_EZI_EN_IN_BUFFER)
+#define SCU_GPIO_FAST (SCU_CONF_EPUN_DIS_PULLUP | \
+ SCU_CONF_EHS_FAST | \
+ SCU_CONF_EZI_EN_IN_BUFFER | \
+ SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
+#define SCU_UART_RX_TX (SCU_CONF_EPUN_DIS_PULLUP | \
+ SCU_CONF_EPD_EN_PULLDOWN | \
+ SCU_CONF_EZI_EN_IN_BUFFER)
+#define SCU_SSP_IO (SCU_CONF_EPUN_DIS_PULLUP | \
+ SCU_CONF_EHS_FAST | \
+ SCU_CONF_EZI_EN_IN_BUFFER | \
+ SCU_CONF_ZIF_DIS_IN_GLITCH_FILT)
+
+BEGIN_DECLS
+
+void scu_pinmux(scu_grp_pin_t group_pin, uint32_t scu_conf);
+
+END_DECLS
+
+/**@}*/
+
+#endif
diff --git a/libopencm3/include/libopencm3/lpc43xx/sdio.h b/libopencm3/include/libopencm3/lpc43xx/sdio.h
new file mode 100644
index 0000000..164dda4
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc43xx/sdio.h
@@ -0,0 +1,151 @@
+/** @defgroup sdio_defines SDIO
+
+@brief Defined Constants and Types for the LPC43xx SDIO
+
+@ingroup LPC43xx_defines
+
+@version 1.0.0
+
+@author @htmlonly © @endhtmlonly 2012 Michael Ossmann
+
+@date 10 March 2013
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Michael Ossmann
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LPC43XX_SDIO_H
+#define LPC43XX_SDIO_H
+
+/**@{*/
+
+#include
+#include
+
+/* --- SDIO registers ----------------------------------------------------- */
+
+/* Control Register */
+#define SDIO_CTRL MMIO32(SDIO_BASE + 0x000)
+
+/* Power Enable Register */
+#define SDIO_PWREN MMIO32(SDIO_BASE + 0x004)
+
+/* Clock Divider Register */
+#define SDIO_CLKDIV MMIO32(SDIO_BASE + 0x008)
+
+/* SD Clock Source Register */
+#define SDIO_CLKSRC MMIO32(SDIO_BASE + 0x00C)
+
+/* Clock Enable Register */
+#define SDIO_CLKENA MMIO32(SDIO_BASE + 0x010)
+
+/* Time-out Register */
+#define SDIO_TMOUT MMIO32(SDIO_BASE + 0x014)
+
+/* Card Type Register */
+#define SDIO_CTYPE MMIO32(SDIO_BASE + 0x018)
+
+/* Block Size Register */
+#define SDIO_BLKSIZ MMIO32(SDIO_BASE + 0x01C)
+
+/* Byte Count Register */
+#define SDIO_BYTCNT MMIO32(SDIO_BASE + 0x020)
+
+/* Interrupt Mask Register */
+#define SDIO_INTMASK MMIO32(SDIO_BASE + 0x024)
+
+/* Command Argument Register */
+#define SDIO_CMDARG MMIO32(SDIO_BASE + 0x028)
+
+/* Command Register */
+#define SDIO_CMD MMIO32(SDIO_BASE + 0x02C)
+
+/* Response Register 0 */
+#define SDIO_RESP0 MMIO32(SDIO_BASE + 0x030)
+
+/* Response Register 1 */
+#define SDIO_RESP1 MMIO32(SDIO_BASE + 0x034)
+
+/* Response Register 2 */
+#define SDIO_RESP2 MMIO32(SDIO_BASE + 0x038)
+
+/* Response Register 3 */
+#define SDIO_RESP3 MMIO32(SDIO_BASE + 0x03C)
+
+/* Masked Interrupt Status Register */
+#define SDIO_MINTSTS MMIO32(SDIO_BASE + 0x040)
+
+/* Raw Interrupt Status Register */
+#define SDIO_RINTSTS MMIO32(SDIO_BASE + 0x044)
+
+/* Status Register */
+#define SDIO_STATUS MMIO32(SDIO_BASE + 0x048)
+
+/* FIFO Threshold Watermark Register */
+#define SDIO_FIFOTH MMIO32(SDIO_BASE + 0x04C)
+
+/* Card Detect Register */
+#define SDIO_CDETECT MMIO32(SDIO_BASE + 0x050)
+
+/* Write Protect Register */
+#define SDIO_WRTPRT MMIO32(SDIO_BASE + 0x054)
+
+/* Transferred CIU Card Byte Count Register */
+#define SDIO_TCBCNT MMIO32(SDIO_BASE + 0x05C)
+
+/* Transferred Host to BIU-FIFO Byte Count Register */
+#define SDIO_TBBCNT MMIO32(SDIO_BASE + 0x060)
+
+/* Debounce Count Register */
+#define SDIO_DEBNCE MMIO32(SDIO_BASE + 0x064)
+
+/* UHS-1 Register */
+#define SDIO_UHS_REG MMIO32(SDIO_BASE + 0x074)
+
+/* Hardware Reset */
+#define SDIO_RST_N MMIO32(SDIO_BASE + 0x078)
+
+/* Bus Mode Register */
+#define SDIO_BMOD MMIO32(SDIO_BASE + 0x080)
+
+/* Poll Demand Register */
+#define SDIO_PLDMND MMIO32(SDIO_BASE + 0x084)
+
+/* Descriptor List Base Address Register */
+#define SDIO_DBADDR MMIO32(SDIO_BASE + 0x088)
+
+/* Internal DMAC Status Register */
+#define SDIO_IDSTS MMIO32(SDIO_BASE + 0x08C)
+
+/* Internal DMAC Interrupt Enable Register */
+#define SDIO_IDINTEN MMIO32(SDIO_BASE + 0x090)
+
+/* Current Host Descriptor Address Register */
+#define SDIO_DSCADDR MMIO32(SDIO_BASE + 0x094)
+
+/* Current Buffer Descriptor Address Register */
+#define SDIO_BUFADDR MMIO32(SDIO_BASE + 0x098)
+
+/* Data FIFO read/write */
+#define SDIO_DATA MMIO32(SDIO_BASE + 0x100)
+
+/**@}*/
+
+#endif
diff --git a/libopencm3/include/libopencm3/lpc43xx/sgpio.h b/libopencm3/include/libopencm3/lpc43xx/sgpio.h
new file mode 100644
index 0000000..4b8d5b6
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc43xx/sgpio.h
@@ -0,0 +1,691 @@
+/** @defgroup sgpio_defines Serial General Purpose I/O
+
+@brief Defined Constants and Types for the LPC43xx Serial General Purpose
+I/O
+
+@ingroup LPC43xx_defines
+
+@version 1.0.0
+
+@author @htmlonly © @endhtmlonly 2012 Michael Ossmann
+
+@date 10 March 2013
+
+LGPL License Terms @ref lgpl_license
+ */
+/** @defgroup sdio_defines SDIO
+
+@brief Defined Constants and Types for the LPC43xx SDIO
+
+@ingroup LPC43xx_defines
+
+@version 1.0.0
+
+@author @htmlonly © @endhtmlonly 2012 Michael Ossmann
+
+@date 10 March 2013
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Michael Ossmann
+ * Copyright (C) 2012 Jared Boone
+ * Copyright (C) 2012 Benjamin Vernoux
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LPC43XX_SGPIO_H
+#define LPC43XX_SGPIO_H
+
+/**@{*/
+
+#include
+#include
+
+/* --- SGPIO registers ----------------------------------------------------- */
+
+/* Pin multiplexer configuration registers (OUT_MUX_CFG0 to 15) */
+#define SGPIO_OUT_MUX_CFG(pin) MMIO32(SGPIO_PORT_BASE + (pin * 0x04))
+#define SGPIO_OUT_MUX_CFG0 MMIO32(SGPIO_PORT_BASE + 0x00)
+#define SGPIO_OUT_MUX_CFG1 MMIO32(SGPIO_PORT_BASE + 0x04)
+#define SGPIO_OUT_MUX_CFG2 MMIO32(SGPIO_PORT_BASE + 0x08)
+#define SGPIO_OUT_MUX_CFG3 MMIO32(SGPIO_PORT_BASE + 0x0C)
+#define SGPIO_OUT_MUX_CFG4 MMIO32(SGPIO_PORT_BASE + 0x10)
+#define SGPIO_OUT_MUX_CFG5 MMIO32(SGPIO_PORT_BASE + 0x14)
+#define SGPIO_OUT_MUX_CFG6 MMIO32(SGPIO_PORT_BASE + 0x18)
+#define SGPIO_OUT_MUX_CFG7 MMIO32(SGPIO_PORT_BASE + 0x1C)
+#define SGPIO_OUT_MUX_CFG8 MMIO32(SGPIO_PORT_BASE + 0x20)
+#define SGPIO_OUT_MUX_CFG9 MMIO32(SGPIO_PORT_BASE + 0x24)
+#define SGPIO_OUT_MUX_CFG10 MMIO32(SGPIO_PORT_BASE + 0x28)
+#define SGPIO_OUT_MUX_CFG11 MMIO32(SGPIO_PORT_BASE + 0x2C)
+#define SGPIO_OUT_MUX_CFG12 MMIO32(SGPIO_PORT_BASE + 0x30)
+#define SGPIO_OUT_MUX_CFG13 MMIO32(SGPIO_PORT_BASE + 0x34)
+#define SGPIO_OUT_MUX_CFG14 MMIO32(SGPIO_PORT_BASE + 0x38)
+#define SGPIO_OUT_MUX_CFG15 MMIO32(SGPIO_PORT_BASE + 0x3C)
+
+/* SGPIO multiplexer configuration registers (SGPIO_MUX_CFG0 to 15) */
+#define SGPIO_MUX_CFG(slice) MMIO32(SGPIO_PORT_BASE + 0x40 + \
+ (slice * 0x04))
+#define SGPIO_MUX_CFG0 MMIO32(SGPIO_PORT_BASE + 0x40)
+#define SGPIO_MUX_CFG1 MMIO32(SGPIO_PORT_BASE + 0x44)
+#define SGPIO_MUX_CFG2 MMIO32(SGPIO_PORT_BASE + 0x48)
+#define SGPIO_MUX_CFG3 MMIO32(SGPIO_PORT_BASE + 0x4C)
+#define SGPIO_MUX_CFG4 MMIO32(SGPIO_PORT_BASE + 0x50)
+#define SGPIO_MUX_CFG5 MMIO32(SGPIO_PORT_BASE + 0x54)
+#define SGPIO_MUX_CFG6 MMIO32(SGPIO_PORT_BASE + 0x58)
+#define SGPIO_MUX_CFG7 MMIO32(SGPIO_PORT_BASE + 0x5C)
+#define SGPIO_MUX_CFG8 MMIO32(SGPIO_PORT_BASE + 0x60)
+#define SGPIO_MUX_CFG9 MMIO32(SGPIO_PORT_BASE + 0x64)
+#define SGPIO_MUX_CFG10 MMIO32(SGPIO_PORT_BASE + 0x68)
+#define SGPIO_MUX_CFG11 MMIO32(SGPIO_PORT_BASE + 0x6C)
+#define SGPIO_MUX_CFG12 MMIO32(SGPIO_PORT_BASE + 0x70)
+#define SGPIO_MUX_CFG13 MMIO32(SGPIO_PORT_BASE + 0x74)
+#define SGPIO_MUX_CFG14 MMIO32(SGPIO_PORT_BASE + 0x78)
+#define SGPIO_MUX_CFG15 MMIO32(SGPIO_PORT_BASE + 0x7C)
+
+/* Slice multiplexer configuration registers (SLICE_MUX_CFG0 to 15) */
+#define SGPIO_SLICE_MUX_CFG(slice) MMIO32(SGPIO_PORT_BASE + 0x80 + \
+ (slice * 0x04))
+#define SGPIO_SLICE_MUX_CFG0 MMIO32(SGPIO_PORT_BASE + 0x80)
+#define SGPIO_SLICE_MUX_CFG1 MMIO32(SGPIO_PORT_BASE + 0x84)
+#define SGPIO_SLICE_MUX_CFG2 MMIO32(SGPIO_PORT_BASE + 0x88)
+#define SGPIO_SLICE_MUX_CFG3 MMIO32(SGPIO_PORT_BASE + 0x8C)
+#define SGPIO_SLICE_MUX_CFG4 MMIO32(SGPIO_PORT_BASE + 0x90)
+#define SGPIO_SLICE_MUX_CFG5 MMIO32(SGPIO_PORT_BASE + 0x94)
+#define SGPIO_SLICE_MUX_CFG6 MMIO32(SGPIO_PORT_BASE + 0x98)
+#define SGPIO_SLICE_MUX_CFG7 MMIO32(SGPIO_PORT_BASE + 0x9C)
+#define SGPIO_SLICE_MUX_CFG8 MMIO32(SGPIO_PORT_BASE + 0xA0)
+#define SGPIO_SLICE_MUX_CFG9 MMIO32(SGPIO_PORT_BASE + 0xA4)
+#define SGPIO_SLICE_MUX_CFG10 MMIO32(SGPIO_PORT_BASE + 0xA8)
+#define SGPIO_SLICE_MUX_CFG11 MMIO32(SGPIO_PORT_BASE + 0xAC)
+#define SGPIO_SLICE_MUX_CFG12 MMIO32(SGPIO_PORT_BASE + 0xB0)
+#define SGPIO_SLICE_MUX_CFG13 MMIO32(SGPIO_PORT_BASE + 0xB4)
+#define SGPIO_SLICE_MUX_CFG14 MMIO32(SGPIO_PORT_BASE + 0xB8)
+#define SGPIO_SLICE_MUX_CFG15 MMIO32(SGPIO_PORT_BASE + 0xBC)
+
+/* Slice data registers (REG0 to 15) */
+#define SGPIO_REG(slice) MMIO32(SGPIO_PORT_BASE + 0xC0 + \
+ (slice * 0x04))
+#define SGPIO_REG0 MMIO32(SGPIO_PORT_BASE + 0xC0)
+#define SGPIO_REG1 MMIO32(SGPIO_PORT_BASE + 0xC4)
+#define SGPIO_REG2 MMIO32(SGPIO_PORT_BASE + 0xC8)
+#define SGPIO_REG3 MMIO32(SGPIO_PORT_BASE + 0xCC)
+#define SGPIO_REG4 MMIO32(SGPIO_PORT_BASE + 0xD0)
+#define SGPIO_REG5 MMIO32(SGPIO_PORT_BASE + 0xD4)
+#define SGPIO_REG6 MMIO32(SGPIO_PORT_BASE + 0xD8)
+#define SGPIO_REG7 MMIO32(SGPIO_PORT_BASE + 0xDC)
+#define SGPIO_REG8 MMIO32(SGPIO_PORT_BASE + 0xE0)
+#define SGPIO_REG9 MMIO32(SGPIO_PORT_BASE + 0xE4)
+#define SGPIO_REG10 MMIO32(SGPIO_PORT_BASE + 0xE8)
+#define SGPIO_REG11 MMIO32(SGPIO_PORT_BASE + 0xEC)
+#define SGPIO_REG12 MMIO32(SGPIO_PORT_BASE + 0xF0)
+#define SGPIO_REG13 MMIO32(SGPIO_PORT_BASE + 0xF4)
+#define SGPIO_REG14 MMIO32(SGPIO_PORT_BASE + 0xF8)
+#define SGPIO_REG15 MMIO32(SGPIO_PORT_BASE + 0xFC)
+
+/* Slice data shadow registers (REG_SS0 to 15) */
+#define SGPIO_REG_SS(slice) MMIO32(SGPIO_PORT_BASE + 0x100 + \
+ (slice * 0x04))
+#define SGPIO_REG_SS0 MMIO32(SGPIO_PORT_BASE + 0x100)
+#define SGPIO_REG_SS1 MMIO32(SGPIO_PORT_BASE + 0x104)
+#define SGPIO_REG_SS2 MMIO32(SGPIO_PORT_BASE + 0x108)
+#define SGPIO_REG_SS3 MMIO32(SGPIO_PORT_BASE + 0x10C)
+#define SGPIO_REG_SS4 MMIO32(SGPIO_PORT_BASE + 0x110)
+#define SGPIO_REG_SS5 MMIO32(SGPIO_PORT_BASE + 0x114)
+#define SGPIO_REG_SS6 MMIO32(SGPIO_PORT_BASE + 0x118)
+#define SGPIO_REG_SS7 MMIO32(SGPIO_PORT_BASE + 0x11C)
+#define SGPIO_REG_SS8 MMIO32(SGPIO_PORT_BASE + 0x120)
+#define SGPIO_REG_SS9 MMIO32(SGPIO_PORT_BASE + 0x124)
+#define SGPIO_REG_SS10 MMIO32(SGPIO_PORT_BASE + 0x128)
+#define SGPIO_REG_SS11 MMIO32(SGPIO_PORT_BASE + 0x12C)
+#define SGPIO_REG_SS12 MMIO32(SGPIO_PORT_BASE + 0x130)
+#define SGPIO_REG_SS13 MMIO32(SGPIO_PORT_BASE + 0x134)
+#define SGPIO_REG_SS14 MMIO32(SGPIO_PORT_BASE + 0x138)
+#define SGPIO_REG_SS15 MMIO32(SGPIO_PORT_BASE + 0x13C)
+
+/* Reload registers (PRESET0 to 15) */
+#define SGPIO_PRESET(slice) MMIO32(SGPIO_PORT_BASE + 0x140 + \
+ (slice * 0x04))
+#define SGPIO_PRESET0 MMIO32(SGPIO_PORT_BASE + 0x140)
+#define SGPIO_PRESET1 MMIO32(SGPIO_PORT_BASE + 0x144)
+#define SGPIO_PRESET2 MMIO32(SGPIO_PORT_BASE + 0x148)
+#define SGPIO_PRESET3 MMIO32(SGPIO_PORT_BASE + 0x14C)
+#define SGPIO_PRESET4 MMIO32(SGPIO_PORT_BASE + 0x150)
+#define SGPIO_PRESET5 MMIO32(SGPIO_PORT_BASE + 0x154)
+#define SGPIO_PRESET6 MMIO32(SGPIO_PORT_BASE + 0x158)
+#define SGPIO_PRESET7 MMIO32(SGPIO_PORT_BASE + 0x15C)
+#define SGPIO_PRESET8 MMIO32(SGPIO_PORT_BASE + 0x160)
+#define SGPIO_PRESET9 MMIO32(SGPIO_PORT_BASE + 0x164)
+#define SGPIO_PRESET10 MMIO32(SGPIO_PORT_BASE + 0x168)
+#define SGPIO_PRESET11 MMIO32(SGPIO_PORT_BASE + 0x16C)
+#define SGPIO_PRESET12 MMIO32(SGPIO_PORT_BASE + 0x170)
+#define SGPIO_PRESET13 MMIO32(SGPIO_PORT_BASE + 0x174)
+#define SGPIO_PRESET14 MMIO32(SGPIO_PORT_BASE + 0x178)
+#define SGPIO_PRESET15 MMIO32(SGPIO_PORT_BASE + 0x17C)
+
+/* Down counter registers (COUNT0 to 15) */
+#define SGPIO_COUNT(slice) MMIO32(SGPIO_PORT_BASE + 0x180 + \
+ (slice * 0x04))
+#define SGPIO_COUNT0 MMIO32(SGPIO_PORT_BASE + 0x180)
+#define SGPIO_COUNT1 MMIO32(SGPIO_PORT_BASE + 0x184)
+#define SGPIO_COUNT2 MMIO32(SGPIO_PORT_BASE + 0x188)
+#define SGPIO_COUNT3 MMIO32(SGPIO_PORT_BASE + 0x18C)
+#define SGPIO_COUNT4 MMIO32(SGPIO_PORT_BASE + 0x190)
+#define SGPIO_COUNT5 MMIO32(SGPIO_PORT_BASE + 0x194)
+#define SGPIO_COUNT6 MMIO32(SGPIO_PORT_BASE + 0x198)
+#define SGPIO_COUNT7 MMIO32(SGPIO_PORT_BASE + 0x19C)
+#define SGPIO_COUNT8 MMIO32(SGPIO_PORT_BASE + 0x1A0)
+#define SGPIO_COUNT9 MMIO32(SGPIO_PORT_BASE + 0x1A4)
+#define SGPIO_COUNT10 MMIO32(SGPIO_PORT_BASE + 0x1A8)
+#define SGPIO_COUNT11 MMIO32(SGPIO_PORT_BASE + 0x1AC)
+#define SGPIO_COUNT12 MMIO32(SGPIO_PORT_BASE + 0x1B0)
+#define SGPIO_COUNT13 MMIO32(SGPIO_PORT_BASE + 0x1B4)
+#define SGPIO_COUNT14 MMIO32(SGPIO_PORT_BASE + 0x1B8)
+#define SGPIO_COUNT15 MMIO32(SGPIO_PORT_BASE + 0x1BC)
+
+/* Position registers (POS0 to 15) */
+#define SGPIO_POS(slice) MMIO32(SGPIO_PORT_BASE + 0x1C0 + \
+ (slice * 0x04))
+#define SGPIO_POS0 MMIO32(SGPIO_PORT_BASE + 0x1C0)
+#define SGPIO_POS1 MMIO32(SGPIO_PORT_BASE + 0x1C4)
+#define SGPIO_POS2 MMIO32(SGPIO_PORT_BASE + 0x1C8)
+#define SGPIO_POS3 MMIO32(SGPIO_PORT_BASE + 0x1CC)
+#define SGPIO_POS4 MMIO32(SGPIO_PORT_BASE + 0x1D0)
+#define SGPIO_POS5 MMIO32(SGPIO_PORT_BASE + 0x1D4)
+#define SGPIO_POS6 MMIO32(SGPIO_PORT_BASE + 0x1D8)
+#define SGPIO_POS7 MMIO32(SGPIO_PORT_BASE + 0x1DC)
+#define SGPIO_POS8 MMIO32(SGPIO_PORT_BASE + 0x1E0)
+#define SGPIO_POS9 MMIO32(SGPIO_PORT_BASE + 0x1E4)
+#define SGPIO_POS10 MMIO32(SGPIO_PORT_BASE + 0x1E8)
+#define SGPIO_POS11 MMIO32(SGPIO_PORT_BASE + 0x1EC)
+#define SGPIO_POS12 MMIO32(SGPIO_PORT_BASE + 0x1F0)
+#define SGPIO_POS13 MMIO32(SGPIO_PORT_BASE + 0x1F4)
+#define SGPIO_POS14 MMIO32(SGPIO_PORT_BASE + 0x1F8)
+#define SGPIO_POS15 MMIO32(SGPIO_PORT_BASE + 0x1FC)
+
+/* Slice name to slice index mapping */
+#define SGPIO_SLICE_A 0
+#define SGPIO_SLICE_B 1
+#define SGPIO_SLICE_C 2
+#define SGPIO_SLICE_D 3
+#define SGPIO_SLICE_E 4
+#define SGPIO_SLICE_F 5
+#define SGPIO_SLICE_G 6
+#define SGPIO_SLICE_H 7
+#define SGPIO_SLICE_I 8
+#define SGPIO_SLICE_J 9
+#define SGPIO_SLICE_K 10
+#define SGPIO_SLICE_L 11
+#define SGPIO_SLICE_M 12
+#define SGPIO_SLICE_N 13
+#define SGPIO_SLICE_O 14
+#define SGPIO_SLICE_P 15
+
+/* Mask for pattern match function of slice A */
+#define SGPIO_MASK_A MMIO32(SGPIO_PORT_BASE + 0x200)
+
+/* Mask for pattern match function of slice H */
+#define SGPIO_MASK_H MMIO32(SGPIO_PORT_BASE + 0x204)
+
+/* Mask for pattern match function of slice I */
+#define SGPIO_MASK_I MMIO32(SGPIO_PORT_BASE + 0x208)
+
+/* Mask for pattern match function of slice P */
+#define SGPIO_MASK_P MMIO32(SGPIO_PORT_BASE + 0x20C)
+
+/* GPIO input status register */
+#define SGPIO_GPIO_INREG MMIO32(SGPIO_PORT_BASE + 0x210)
+
+/* GPIO output control register */
+#define SGPIO_GPIO_OUTREG MMIO32(SGPIO_PORT_BASE + 0x214)
+
+/* GPIO OE control register */
+#define SGPIO_GPIO_OENREG MMIO32(SGPIO_PORT_BASE + 0x218)
+
+/* Enables the slice COUNT counter */
+#define SGPIO_CTRL_ENABLE MMIO32(SGPIO_PORT_BASE + 0x21C)
+
+/* Disables the slice COUNT counter */
+#define SGPIO_CTRL_DISABLE MMIO32(SGPIO_PORT_BASE + 0x220)
+
+/* Shift clock interrupt clear mask */
+#define SGPIO_CLR_EN_0 MMIO32(SGPIO_PORT_BASE + 0xF00)
+
+/* Shift clock interrupt set mask */
+#define SGPIO_SET_EN_0 MMIO32(SGPIO_PORT_BASE + 0xF04)
+
+/* Shift clock interrupt enable */
+#define SGPIO_ENABLE_0 MMIO32(SGPIO_PORT_BASE + 0xF08)
+
+/* Shift clock interrupt status */
+#define SGPIO_STATUS_0 MMIO32(SGPIO_PORT_BASE + 0xF0C)
+
+/* Shift clock interrupt clear status */
+#define SGPIO_CLR_STATUS_0 MMIO32(SGPIO_PORT_BASE + 0xF10)
+
+/* Shift clock interrupt set status */
+#define SGPIO_SET_STATUS_0 MMIO32(SGPIO_PORT_BASE + 0xF14)
+
+/* Exchange clock interrupt clear mask */
+#define SGPIO_CLR_EN_1 MMIO32(SGPIO_PORT_BASE + 0xF20)
+
+/* Exchange clock interrupt set mask */
+#define SGPIO_SET_EN_1 MMIO32(SGPIO_PORT_BASE + 0xF24)
+
+/* Exchange clock interrupt enable */
+#define SGPIO_ENABLE_1 MMIO32(SGPIO_PORT_BASE + 0xF28)
+
+/* Exchange clock interrupt status */
+#define SGPIO_STATUS_1 MMIO32(SGPIO_PORT_BASE + 0xF2C)
+
+/* Exchange clock interrupt clear status */
+#define SGPIO_CLR_STATUS_1 MMIO32(SGPIO_PORT_BASE + 0xF30)
+
+/* Exchange clock interrupt set status */
+#define SGPIO_SET_STATUS_1 MMIO32(SGPIO_PORT_BASE + 0xF34)
+
+/* Pattern match interrupt clear mask */
+#define SGPIO_CLR_EN_2 MMIO32(SGPIO_PORT_BASE + 0xF40)
+
+/* Pattern match interrupt set mask */
+#define SGPIO_SET_EN_2 MMIO32(SGPIO_PORT_BASE + 0xF44)
+
+/* Pattern match interrupt enable */
+#define SGPIO_ENABLE_2 MMIO32(SGPIO_PORT_BASE + 0xF48)
+
+/* Pattern match interrupt status */
+#define SGPIO_STATUS_2 MMIO32(SGPIO_PORT_BASE + 0xF4C)
+
+/* Pattern match interrupt clear status */
+#define SGPIO_CLR_STATUS_2 MMIO32(SGPIO_PORT_BASE + 0xF50)
+
+/* Pattern match interrupt set status */
+#define SGPIO_SET_STATUS_2 MMIO32(SGPIO_PORT_BASE + 0xF54)
+
+/* Input interrupt clear mask */
+#define SGPIO_CLR_EN_3 MMIO32(SGPIO_PORT_BASE + 0xF60)
+
+/* Input bit match interrupt set mask */
+#define SGPIO_SET_EN_3 MMIO32(SGPIO_PORT_BASE + 0xF64)
+
+/* Input bit match interrupt enable */
+#define SGPIO_ENABLE_3 MMIO32(SGPIO_PORT_BASE + 0xF68)
+
+/* Input bit match interrupt status */
+#define SGPIO_STATUS_3 MMIO32(SGPIO_PORT_BASE + 0xF6C)
+
+/* Input bit match interrupt clear status */
+#define SGPIO_CLR_STATUS_3 MMIO32(SGPIO_PORT_BASE + 0xF70)
+
+/* Input bit match interrupt set status */
+#define SGPIO_SET_STATUS_3 MMIO32(SGPIO_PORT_BASE + 0xF74)
+
+/* --- Common register fields ----------------------------------- */
+/* TODO: Generate this stuff with the gen.py script as well! */
+
+#define SGPIO_OUT_MUX_CFG_P_OUT_CFG_SHIFT (0)
+#define SGPIO_OUT_MUX_CFG_P_OUT_CFG_MASK \
+ (0xf << SGPIO_OUT_MUX_CFG_P_OUT_CFG_SHIFT)
+#define SGPIO_OUT_MUX_CFG_P_OUT_CFG(x) \
+ ((x) << SGPIO_OUT_MUX_CFG_P_OUT_CFG_SHIFT)
+
+#define SGPIO_OUT_MUX_CFG_P_OE_CFG_SHIFT (4)
+#define SGPIO_OUT_MUX_CFG_P_OE_CFG_MASK \
+ (0x7 << SGPIO_OUT_MUX_CFG_P_OE_CFG_SHIFT)
+#define SGPIO_OUT_MUX_CFG_P_OE_CFG(x) \
+ ((x) << SGPIO_OUT_MUX_CFG_P_OE_CFG_SHIFT)
+
+#define SGPIO_MUX_CFG_EXT_CLK_ENABLE_SHIFT (0)
+#define SGPIO_MUX_CFG_EXT_CLK_ENABLE_MASK \
+ (1 << SGPIO_MUX_CFG_EXT_CLK_ENABLE_SHIFT)
+#define SGPIO_MUX_CFG_EXT_CLK_ENABLE(x) \
+ ((x) << SGPIO_MUX_CFG_EXT_CLK_ENABLE_SHIFT)
+
+#define SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_SHIFT (1)
+#define SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_MASK \
+ (0x3 << SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_SHIFT)
+#define SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE(x) \
+ ((x) << SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_SHIFT)
+
+#define SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_SHIFT (3)
+#define SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_MASK \
+ (0x3 << SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_SHIFT)
+#define SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE(x) \
+ ((x) << SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_SHIFT)
+
+#define SGPIO_MUX_CFG_QUALIFIER_MODE_SHIFT (5)
+#define SGPIO_MUX_CFG_QUALIFIER_MODE_MASK \
+ (0x3 << SGPIO_MUX_CFG_QUALIFIER_MODE_SHIFT)
+#define SGPIO_MUX_CFG_QUALIFIER_MODE(x) \
+ ((x) << SGPIO_MUX_CFG_QUALIFIER_MODE_SHIFT)
+
+#define SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_SHIFT (7)
+#define SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_MASK \
+ (0x3 << SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_SHIFT)
+#define SGPIO_MUX_CFG_QUALIFIER_PIN_MODE(x) \
+ ((x) << SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_SHIFT)
+
+#define SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_SHIFT (9)
+#define SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_MASK \
+ (0x3 << SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_SHIFT)
+#define SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE(x) \
+ ((x) << SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_SHIFT)
+
+#define SGPIO_MUX_CFG_CONCAT_ENABLE_SHIFT (11)
+#define SGPIO_MUX_CFG_CONCAT_ENABLE_MASK \
+ (1 << SGPIO_MUX_CFG_CONCAT_ENABLE_SHIFT)
+#define SGPIO_MUX_CFG_CONCAT_ENABLE(x) \
+ ((x) << SGPIO_MUX_CFG_CONCAT_ENABLE_SHIFT)
+
+#define SGPIO_MUX_CFG_CONCAT_ORDER_SHIFT (12)
+#define SGPIO_MUX_CFG_CONCAT_ORDER_MASK \
+ (0x3 << SGPIO_MUX_CFG_CONCAT_ORDER_SHIFT)
+#define SGPIO_MUX_CFG_CONCAT_ORDER(x) \
+ ((x) << SGPIO_MUX_CFG_CONCAT_ORDER_SHIFT)
+
+#define SGPIO_SLICE_MUX_CFG_MATCH_MODE_SHIFT (0)
+#define SGPIO_SLICE_MUX_CFG_MATCH_MODE_MASK \
+ (1 << SGPIO_SLICE_MUX_CFG_MATCH_MODE_SHIFT)
+#define SGPIO_SLICE_MUX_CFG_MATCH_MODE(x) \
+ ((x) << SGPIO_SLICE_MUX_CFG_MATCH_MODE_SHIFT)
+
+#define SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_SHIFT (1)
+#define SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_MASK \
+ (1 << SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_SHIFT)
+#define SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE(x) \
+ ((x) << SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_SHIFT)
+
+#define SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_SHIFT (2)
+#define SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_MASK \
+ (1 << SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_SHIFT)
+#define SGPIO_SLICE_MUX_CFG_CLKGEN_MODE(x) \
+ ((x) << SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_SHIFT)
+
+#define SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_SHIFT (3)
+#define SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_MASK \
+ (1 << SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_SHIFT)
+#define SGPIO_SLICE_MUX_CFG_INV_OUT_CLK(x) \
+ ((x) << SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_SHIFT)
+
+#define SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_SHIFT (4)
+#define SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_MASK \
+ (0x3 << SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_SHIFT)
+#define SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE(x) \
+ ((x) << SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_SHIFT)
+
+#define SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_SHIFT (6)
+#define SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_MASK \
+ (0x3 << SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_SHIFT)
+#define SGPIO_SLICE_MUX_CFG_PARALLEL_MODE(x) \
+ ((x) << SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_SHIFT)
+
+#define SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_SHIFT (8)
+#define SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_MASK \
+ (1 << SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_SHIFT)
+#define SGPIO_SLICE_MUX_CFG_INV_QUALIFIER(x) \
+ ((x) << SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_SHIFT)
+
+#define SGPIO_POS_POS_SHIFT (0)
+#define SGPIO_POS_POS_MASK (0xff << SGPIO_POS_POS_SHIFT)
+#define SGPIO_POS_POS(x) ((x) << SGPIO_POS_POS_SHIFT)
+
+#define SGPIO_POS_POS_RESET_SHIFT (8)
+#define SGPIO_POS_POS_RESET_MASK (0xff << SGPIO_POS_POS_RESET_SHIFT)
+#define SGPIO_POS_POS_RESET(x) ((x) << SGPIO_POS_POS_RESET_SHIFT)
+
+/* --- AUTO-GENERATED STUFF FOLLOWS ----------------------------- */
+
+/* --- SGPIO_OUT_MUX_CFG[0..15] values ------------------------------------ */
+
+/* P_OUT_CFG: Output control of output SGPIOn */
+#define SGPIO_OUT_MUX_CFGx_P_OUT_CFG_SHIFT (0)
+#define SGPIO_OUT_MUX_CFGx_P_OUT_CFG_MASK \
+ (0xf << SGPIO_OUT_MUX_CFGx_P_OUT_CFG_SHIFT)
+#define SGPIO_OUT_MUX_CFGx_P_OUT_CFG(x) \
+ ((x) << SGPIO_OUT_MUX_CFGx_P_OUT_CFG_SHIFT)
+
+/* P_OE_CFG: Output enable source */
+#define SGPIO_OUT_MUX_CFGx_P_OE_CFG_SHIFT (4)
+#define SGPIO_OUT_MUX_CFGx_P_OE_CFG_MASK \
+ (0x7 << SGPIO_OUT_MUX_CFGx_P_OE_CFG_SHIFT)
+#define SGPIO_OUT_MUX_CFGx_P_OE_CFG(x) \
+ ((x) << SGPIO_OUT_MUX_CFGx_P_OE_CFG_SHIFT)
+
+/* --- SGPIO_MUX_CFG[0..15] values ---------------------------------------- */
+
+/* EXT_CLK_ENABLE: Select clock signal */
+#define SGPIO_MUX_CFGx_EXT_CLK_ENABLE_SHIFT (0)
+#define SGPIO_MUX_CFGx_EXT_CLK_ENABLE \
+ (1 << SGPIO_MUX_CFGx_EXT_CLK_ENABLE_SHIFT)
+
+/* CLK_SOURCE_PIN_MODE: Select source clock pin */
+#define SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE_SHIFT (1)
+#define SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE_MASK \
+ (0x3 << SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE_SHIFT)
+#define SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE(x) \
+ ((x) << SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE_SHIFT)
+
+/* CLK_SOURCE_SLICE_MODE: Select clock source slice */
+#define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_SHIFT (3)
+#define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_MASK \
+ (0x3 << SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_SHIFT)
+#define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE(x) \
+ ((x) << SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_SHIFT)
+
+/* QUALIFIER_MODE: Select qualifier mode */
+#define SGPIO_MUX_CFGx_QUALIFIER_MODE_SHIFT (5)
+#define SGPIO_MUX_CFGx_QUALIFIER_MODE_MASK \
+ (0x3 << SGPIO_MUX_CFGx_QUALIFIER_MODE_SHIFT)
+#define SGPIO_MUX_CFGx_QUALIFIER_MODE(x) \
+ ((x) << SGPIO_MUX_CFGx_QUALIFIER_MODE_SHIFT)
+
+/* QUALIFIER_PIN_MODE: Select qualifier pin */
+#define SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE_SHIFT (7)
+#define SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE_MASK \
+ (0x3 << SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE_SHIFT)
+#define SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE(x) \
+ ((x) << SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE_SHIFT)
+
+/* QUALIFIER_SLICE_MODE: Select qualifier slice */
+#define SGPIO_MUX_CFGx_QUALIFIER_SLICE_MODE_SHIFT (9)
+#define SGPIO_MUX_CFGx_QUALIFIER_SLICE_MODE_MASK \
+ (0x3 << SGPIO_MUX_CFGx_QUALIFIER_SLICE_MODE_SHIFT)
+#define SGPIO_MUX_CFGx_QUALIFIER_SLICE_MODE(x) \
+ ((x) << SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_SHIFT)
+
+/* CONCAT_ENABLE: Enable concatenation */
+#define SGPIO_MUX_CFGx_CONCAT_ENABLE_SHIFT (11)
+#define SGPIO_MUX_CFGx_CONCAT_ENABLE \
+ (1 << SGPIO_MUX_CFGx_CONCAT_ENABLE_SHIFT)
+
+/* CONCAT_ORDER: Select concatenation order */
+#define SGPIO_MUX_CFGx_CONCAT_ORDER_SHIFT (12)
+#define SGPIO_MUX_CFGx_CONCAT_ORDER_MASK \
+ (0x3 << SGPIO_MUX_CFGx_CONCAT_ORDER_SHIFT)
+#define SGPIO_MUX_CFGx_CONCAT_ORDER(x) \
+ ((x) << SGPIO_MUX_CFGx_CONCAT_ORDER_SHIFT)
+
+/* --- SGPIO_SLICE_MUX_CFG[0..15] values ---------------------------------- */
+
+/* MATCH_MODE: Match mode */
+#define SGPIO_SLICE_MUX_CFGx_MATCH_MODE_SHIFT (0)
+#define SGPIO_SLICE_MUX_CFGx_MATCH_MODE \
+ (1 << SGPIO_SLICE_MUX_CFG0_MATCH_MODE_SHIFT)
+
+/* CLK_CAPTURE_MODE: Capture clock mode */
+#define SGPIO_SLICE_MUX_CFGx_CLK_CAPTURE_MODE_SHIFT (1)
+#define SGPIO_SLICE_MUX_CFGx_CLK_CAPTURE_MODE \
+ (1 << SGPIO_SLICE_MUX_CFGx_CLK_CAPTURE_MODE_SHIFT)
+
+/* CLKGEN_MODE: Clock generation mode */
+#define SGPIO_SLICE_MUX_CFGx_CLKGEN_MODE_SHIFT (2)
+#define SGPIO_SLICE_MUX_CFGx_CLKGEN_MODE \
+ (1 << SGPIO_SLICE_MUX_CFGx_CLKGEN_MODE_SHIFT)
+
+/* INV_OUT_CLK: Invert output clock */
+#define SGPIO_SLICE_MUX_CFGx_INV_OUT_CLK_SHIFT (3)
+#define SGPIO_SLICE_MUX_CFGx_INV_OUT_CLK \
+ (1 << SGPIO_SLICE_MUX_CFGx_INV_OUT_CLK_SHIFT)
+
+/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */
+#define SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE_SHIFT (4)
+#define SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE_MASK \
+ (0x3 << SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE_SHIFT)
+#define SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE(x) \
+ ((x) << SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE_SHIFT)
+
+/* PARALLEL_MODE: Parallel mode */
+#define SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE_SHIFT (6)
+#define SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE_MASK \
+ (0x3 << SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE_SHIFT)
+#define SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE(x) \
+ ((x) << SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE_SHIFT)
+
+/* INV_QUALIFIER: Inversion qualifier */
+#define SGPIO_SLICE_MUX_CFGx_INV_QUALIFIER_SHIFT (8)
+#define SGPIO_SLICE_MUX_CFGx_INV_QUALIFIER \
+ (1 << SGPIO_SLICE_MUX_CFGx_INV_QUALIFIER_SHIFT)
+
+
+/* --- SGPIO_POS[0..15] values -------------------------------------------- */
+
+/* POS: Each time COUNT reaches 0x0 POS counts down */
+#define SGPIO_POSx_POS_SHIFT (0)
+#define SGPIO_POSx_POS_MASK (0xff << SGPIO_POSx_POS_SHIFT)
+#define SGPIO_POSx_POS(x) ((x) << SGPIO_POSx_POS_SHIFT)
+
+/* POS_RESET: Reload value for POS after POS reaches 0x0 */
+#define SGPIO_POSx_POS_RESET_SHIFT (8)
+#define SGPIO_POSx_POS_RESET_MASK (0xff << SGPIO_POSx_POS_RESET_SHIFT)
+#define SGPIO_POSx_POS_RESET(x) ((x) << SGPIO_POSx_POS_RESET_SHIFT)
+
+
+/* SGPIO structure for faster/better code generation (especially when optimized
+ * with -O2/-O3)
+ */
+/* This structure is compliant with LPC43xx User Manual UM10503 Rev.1.4 - 3
+ * September 2012
+ */
+typedef struct {
+ /* Pin multiplexer configuration registers. RW */
+ volatile uint32_t OUT_MUX_CFG[16];
+ /* SGPIO multiplexer configuration registers. RW */
+ volatile uint32_t SGPIO_MUX_CFG[16];
+ /* Slice multiplexer configuration registers. RW */
+ volatile uint32_t SLICE_MUX_CFG[16];
+ /* Slice data registers. RW */
+ volatile uint32_t REG[16];
+ /* Slice data shadow registers. Each time POS reaches 0x0 the contents
+ * of REG_SS is exchanged with the content of REG. RW
+ */
+ volatile uint32_t REG_SS[16];
+ /* Reload registers. Counter reload value; loaded when COUNT reaches
+ * 0x0 RW
+ */
+ volatile uint32_t PRESET[16];
+ /* Down counter registers, counts down each shift clock cycle. RW */
+ volatile uint32_t COUNT[16];
+ /* Position registers. POS Each time COUNT reaches 0x0 POS counts down.
+ * POS_RESET Reload value for POS after POS reaches 0x0. RW
+ */
+ volatile uint32_t POS[16];
+ /* Slice A mask register. Mask for pattern match function of slice A.
+ * RW
+ */
+ volatile uint32_t MASK_A;
+ /* Slice H mask register. Mask for pattern match function of slice H.
+ * RW
+ */
+ volatile uint32_t MASK_H;
+ /* Slice I mask register. Mask for pattern match function of slice I.
+ * RW
+ */
+ volatile uint32_t MASK_I;
+ /* Slice P mask register. Mask for pattern match function of slice P.
+ * RW
+ */
+ volatile uint32_t MASK_P;
+ /* GPIO input status register. R */
+ volatile uint32_t GPIO_INREG;
+ /* GPIO output control register. RW */
+ volatile uint32_t GPIO_OUTREG;
+ /* GPIO output enable register. RW */
+ volatile uint32_t GPIO_OENREG;
+ /* Slice count enable register. RW */
+ volatile uint32_t CTRL_ENABLE;
+ /* Slice count disable register. RW */
+ volatile uint32_t CTRL_DISABLE;
+ volatile uint32_t RES0[823];
+ /* Shift clock interrupt clear mask register. W */
+ volatile uint32_t CLR_EN_0;
+ /* Shift clock interrupt set mask register. W */
+ volatile uint32_t SET_EN_0;
+ /* Shift clock interrupt enable register. R */
+ volatile uint32_t ENABLE_0;
+ /* Shift clock interrupt status register. R */
+ volatile uint32_t STATUS_0;
+ /* Shift clock interrupt clear status register. W */
+ volatile uint32_t CLR_STATUS_0;
+ /* Shift clock interrupt set status register. W */
+ volatile uint32_t SET_STATUS_0;
+ volatile uint32_t RES1[2];
+ /* Exchange clock interrupt clear mask register. W */
+ volatile uint32_t CLR_EN_1;
+ /* Exchange clock interrupt set mask register. W */
+ volatile uint32_t SET_EN_1;
+ /* Exchange clock interrupt enable. R */
+ volatile uint32_t ENABLE_1;
+ /* Exchange clock interrupt status register. R */
+ volatile uint32_t STATUS_1;
+ /* Exchange clock interrupt clear status register. W */
+ volatile uint32_t CLR_STATUS_1;
+ /* Exchange clock interrupt set status register. W */
+ volatile uint32_t SET_STATUS_1;
+ volatile uint32_t RES2[2];
+ /* Pattern match interrupt clear mask register. W */
+ volatile uint32_t CLR_EN_2;
+ /* Pattern match interrupt set mask register. W */
+ volatile uint32_t SET_EN_2;
+ /* Pattern match interrupt enable register. R */
+ volatile uint32_t ENABLE_2;
+ /* Pattern match interrupt status register. R */
+ volatile uint32_t STATUS_2;
+ /* Pattern match interrupt clear status register. W */
+ volatile uint32_t CLR_STATUS_2;
+ /* Pattern match interrupt set status register. W */
+ volatile uint32_t SET_STATUS_2;
+ volatile uint32_t RES3[2];
+ /* Input interrupt clear mask register. W */
+ volatile uint32_t CLR_EN_3;
+ /* Input bit match interrupt set mask register. W */
+ volatile uint32_t SET_EN_3;
+ /* Input bit match interrupt enable register. R */
+ volatile uint32_t ENABLE_3;
+ /* Input bit match interrupt status register. R */
+ volatile uint32_t STATUS_3;
+ /* Input bit match interrupt clear status register. W */
+ volatile uint32_t CLR_STATUS_3;
+ /* Input bit match interrupt set status register. W */
+ volatile uint32_t SET_STATUS_3;
+} sgpio_t;
+
+/* Global access to SGPIO structure */
+#define SGPIO ((sgpio_t *)SGPIO_PORT_BASE)
+
+/**@}*/
+
+#endif
diff --git a/libopencm3/include/libopencm3/lpc43xx/ssp.h b/libopencm3/include/libopencm3/lpc43xx/ssp.h
new file mode 100644
index 0000000..a336652
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc43xx/ssp.h
@@ -0,0 +1,209 @@
+/** @defgroup ssp_defines Synchronous Serial Port
+
+@brief Defined Constants and Types for the LPC43xx Synchronous Serial
+Port
+
+@ingroup LPC43xx_defines
+
+@version 1.0.0
+
+@author @htmlonly © @endhtmlonly 2012 Michael Ossmann
+
+@date 10 March 2013
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+* This file is part of the libopencm3 project.
+*
+* Copyright (C) 2012 Michael Ossmann
+*
+* This library is free software: you can redistribute it and/or modify
+* it under the terms of the GNU Lesser General Public License as published by
+* the Free Software Foundation, either version 3 of the License, or
+* (at your option) any later version.
+*
+* This library is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU Lesser General Public License for more details.
+*
+* You should have received a copy of the GNU Lesser General Public License
+* along with this library. If not, see .
+*/
+
+#ifndef LPC43XX_SSP_H
+#define LPC43XX_SSP_H
+
+/**@{*/
+
+#include
+#include
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* SSP port base addresses (for convenience) */
+#define SSP0 SSP0_BASE
+#define SSP1 SSP1_BASE
+
+
+/* --- SSP registers ------------------------------------------------------- */
+
+/* Control Register 0 */
+#define SSP_CR0(port) MMIO32(port + 0x000)
+#define SSP0_CR0 SSP_CR0(SSP0)
+#define SSP1_CR0 SSP_CR0(SSP1)
+
+/* Control Register 1 */
+#define SSP_CR1(port) MMIO32(port + 0x004)
+#define SSP0_CR1 SSP_CR1(SSP0)
+#define SSP1_CR1 SSP_CR1(SSP1)
+
+/* Data Register */
+#define SSP_DR(port) MMIO32(port + 0x008)
+#define SSP0_DR SSP_DR(SSP0)
+#define SSP1_DR SSP_DR(SSP1)
+
+/* Status Register */
+#define SSP_SR(port) MMIO32(port + 0x00C)
+#define SSP0_SR SSP_SR(SSP0)
+#define SSP1_SR SSP_SR(SSP1)
+
+#define SSP_SR_TFE BIT0
+#define SSP_SR_TNF BIT1
+#define SSP_SR_RNE BIT2
+#define SSP_SR_RFF BIT3
+#define SSP_SR_BSY BIT4
+
+/* Clock Prescale Register */
+#define SSP_CPSR(port) MMIO32(port + 0x010)
+#define SSP0_CPSR SSP_CPSR(SSP0)
+#define SSP1_CPSR SSP_CPSR(SSP1)
+
+/* Interrupt Mask Set and Clear Register */
+#define SSP_IMSC(port) MMIO32(port + 0x014)
+#define SSP0_IMSC SSP_IMSC(SSP0)
+#define SSP1_IMSC SSP_IMSC(SSP1)
+
+/* Raw Interrupt Status Register */
+#define SSP_RIS(port) MMIO32(port + 0x018)
+#define SSP0_RIS SSP_RIS(SSP0)
+#define SSP1_RIS SSP_RIS(SSP1)
+
+/* Masked Interrupt Status Register */
+#define SSP_MIS(port) MMIO32(port + 0x01C)
+#define SSP0_MIS SSP_MIS(SSP0)
+#define SSP1_MIS SSP_MIS(SSP1)
+
+/* SSPICR Interrupt Clear Register */
+#define SSP_ICR(port) MMIO32(port + 0x020)
+#define SSP0_ICR SSP_ICR(SSP0)
+#define SSP1_ICR SSP_ICR(SSP1)
+
+/* SSP1 DMA control register */
+#define SSP_DMACR(port) MMIO32(port + 0x024)
+#define SSP0_DMACR SSP_DMACR(SSP0)
+#define SSP1_DMACR SSP_DMACR(SSP1)
+
+/* RXDMAE: Receive DMA enable */
+#define SSP_DMACR_RXDMAE 0x1
+
+/* RXDMAE: Transmit DMA enable */
+#define SSP_DMACR_TXDMAE 0x2
+
+typedef enum {
+ SSP0_NUM = 0x0,
+ SSP1_NUM = 0x1
+} ssp_num_t;
+
+/*
+ * SSP Control Register 0
+ */
+/* SSP Data Size Bits 0 to 3 */
+typedef enum {
+ SSP_DATA_4BITS = 0x3,
+ SSP_DATA_5BITS = 0x4,
+ SSP_DATA_6BITS = 0x5,
+ SSP_DATA_7BITS = 0x6,
+ SSP_DATA_8BITS = 0x7,
+ SSP_DATA_9BITS = 0x8,
+ SSP_DATA_10BITS = 0x9,
+ SSP_DATA_11BITS = 0xA,
+ SSP_DATA_12BITS = 0xB,
+ SSP_DATA_13BITS = 0xC,
+ SSP_DATA_14BITS = 0xD,
+ SSP_DATA_15BITS = 0xE,
+ SSP_DATA_16BITS = 0xF
+} ssp_datasize_t;
+
+/* SSP Frame Format/Type Bits 4 & 5 */
+typedef enum {
+ SSP_FRAME_SPI = 0x00,
+ SSP_FRAME_TI = BIT4,
+ SSP_FRAM_MICROWIRE = BIT5
+} ssp_frame_format_t;
+
+/* Clock Out Polarity / Clock Out Phase Bits Bits 6 & 7 */
+typedef enum {
+ SSP_CPOL_0_CPHA_0 = 0x0,
+ SSP_CPOL_1_CPHA_0 = BIT6,
+ SSP_CPOL_0_CPHA_1 = BIT7,
+ SSP_CPOL_1_CPHA_1 = (BIT6|BIT7)
+} ssp_cpol_cpha_t;
+
+/*
+ * SSP Control Register 1
+ */
+/* SSP Mode Bit0 */
+typedef enum {
+ SSP_MODE_NORMAL = 0x0,
+ SSP_MODE_LOOPBACK = BIT0
+} ssp_mode_t;
+
+/* SSP Enable Bit1 */
+#define SSP_ENABLE BIT1
+
+/* SSP Master/Slave Mode Bit2 */
+typedef enum {
+ SSP_MASTER = 0x0,
+ SSP_SLAVE = BIT2
+} ssp_master_slave_t;
+
+/*
+* SSP Slave Output Disable Bit3
+* Slave Output Disable. This bit is relevant only in slave mode
+* (MS = 1). If it is 1, this blocks this SSP controller from driving the
+* transmit data line (MISO).
+*/
+typedef enum {
+ SSP_SLAVE_OUT_ENABLE = 0x0,
+ SSP_SLAVE_OUT_DISABLE = BIT3
+} ssp_slave_option_t; /* This option is relevant only in slave mode */
+
+BEGIN_DECLS
+
+void ssp_disable(ssp_num_t ssp_num);
+
+/*
+ * SSP Init
+ * clk_prescale shall be in range 2 to 254 (even number only).
+ * Clock computation: PCLK / (CPSDVSR * [SCR+1]) => CPSDVSR=clk_prescale,
+ * SCR=serial_clock_rate
+ */
+void ssp_init(ssp_num_t ssp_num,
+ ssp_datasize_t data_size,
+ ssp_frame_format_t frame_format,
+ ssp_cpol_cpha_t cpol_cpha_format,
+ uint8_t serial_clock_rate,
+ uint8_t clk_prescale,
+ ssp_mode_t mode,
+ ssp_master_slave_t master_slave,
+ ssp_slave_option_t slave_option);
+
+uint16_t ssp_transfer(ssp_num_t ssp_num, uint16_t data);
+
+END_DECLS
+
+/**@}*/
+
+#endif
diff --git a/libopencm3/include/libopencm3/lpc43xx/timer.h b/libopencm3/include/libopencm3/lpc43xx/timer.h
new file mode 100644
index 0000000..2c691e7
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc43xx/timer.h
@@ -0,0 +1,270 @@
+/** @defgroup timer_defines Timer
+
+@brief Defined Constants and Types for the LPC43xx timer
+
+@ingroup LPC43xx_defines
+
+@version 1.0.0
+
+@author @htmlonly © @endhtmlonly 2012 Michael Ossmann
+
+@date 10 March 2013
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Michael Ossmann
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LPC43XX_TIMER_H
+#define LPC43XX_TIMER_H
+
+/**@{*/
+
+#include
+#include
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* Timer base addresses */
+#define TIMER0 TIMER0_BASE
+#define TIMER1 TIMER1_BASE
+#define TIMER2 TIMER2_BASE
+#define TIMER3 TIMER3_BASE
+
+
+/* --- Timer registers ----------------------------------------------------- */
+
+/* Interrupt Register */
+#define TIMER_IR(timer) MMIO32(timer + 0x000)
+#define TIMER0_IR TIMER_IR(TIMER0)
+#define TIMER1_IR TIMER_IR(TIMER1)
+#define TIMER2_IR TIMER_IR(TIMER2)
+#define TIMER3_IR TIMER_IR(TIMER3)
+
+/* Timer Control Register */
+#define TIMER_TCR(timer) MMIO32(timer + 0x004)
+#define TIMER0_TCR TIMER_TCR(TIMER0)
+#define TIMER1_TCR TIMER_TCR(TIMER1)
+#define TIMER2_TCR TIMER_TCR(TIMER2)
+#define TIMER3_TCR TIMER_TCR(TIMER3)
+
+/* Timer Counter */
+#define TIMER_TC(timer) MMIO32(timer + 0x008)
+#define TIMER0_TC TIMER_TC(TIMER0)
+#define TIMER1_TC TIMER_TC(TIMER1)
+#define TIMER2_TC TIMER_TC(TIMER2)
+#define TIMER3_TC TIMER_TC(TIMER3)
+
+/* Prescale Register */
+#define TIMER_PR(timer) MMIO32(timer + 0x00C)
+#define TIMER0_PR TIMER_PR(TIMER0)
+#define TIMER1_PR TIMER_PR(TIMER1)
+#define TIMER2_PR TIMER_PR(TIMER2)
+#define TIMER3_PR TIMER_PR(TIMER3)
+
+/* Prescale Counter */
+#define TIMER_PC(timer) MMIO32(timer + 0x010)
+#define TIMER0_PC TIMER_PC(TIMER0)
+#define TIMER1_PC TIMER_PC(TIMER1)
+#define TIMER2_PC TIMER_PC(TIMER2)
+#define TIMER3_PC TIMER_PC(TIMER3)
+
+/* Match Control Register */
+#define TIMER_MCR(timer) MMIO32(timer + 0x014)
+#define TIMER0_MCR TIMER_MCR(TIMER0)
+#define TIMER1_MCR TIMER_MCR(TIMER1)
+#define TIMER2_MCR TIMER_MCR(TIMER2)
+#define TIMER3_MCR TIMER_MCR(TIMER3)
+
+/* Match Register 0 */
+#define TIMER_MR0(timer) MMIO32(timer + 0x018)
+#define TIMER0_MR0 TIMER_MR0(TIMER0)
+#define TIMER1_MR0 TIMER_MR0(TIMER1)
+#define TIMER2_MR0 TIMER_MR0(TIMER2)
+#define TIMER3_MR0 TIMER_MR0(TIMER3)
+
+/* Match Register 1 */
+#define TIMER_MR1(timer) MMIO32(timer + 0x01C)
+#define TIMER0_MR1 TIMER_MR1(TIMER0)
+#define TIMER1_MR1 TIMER_MR1(TIMER1)
+#define TIMER2_MR1 TIMER_MR1(TIMER2)
+#define TIMER3_MR1 TIMER_MR1(TIMER3)
+
+/* Match Register 2 */
+#define TIMER_MR2(timer) MMIO32(timer + 0x020)
+#define TIMER0_MR2 TIMER_MR2(TIMER0)
+#define TIMER1_MR2 TIMER_MR2(TIMER1)
+#define TIMER2_MR2 TIMER_MR2(TIMER2)
+#define TIMER3_MR2 TIMER_MR2(TIMER3)
+
+/* Match Register 3 */
+#define TIMER_MR3(timer) MMIO32(timer + 0x024)
+#define TIMER0_MR3 TIMER_MR3(TIMER0)
+#define TIMER1_MR3 TIMER_MR3(TIMER1)
+#define TIMER2_MR3 TIMER_MR3(TIMER2)
+#define TIMER3_MR3 TIMER_MR3(TIMER3)
+
+/* Capture Control Register */
+#define TIMER_CCR(timer) MMIO32(timer + 0x028)
+#define TIMER0_CCR TIMER_CCR(TIMER0)
+#define TIMER1_CCR TIMER_CCR(TIMER1)
+#define TIMER2_CCR TIMER_CCR(TIMER2)
+#define TIMER3_CCR TIMER_CCR(TIMER3)
+
+/* Capture Register 0 */
+#define TIMER_CR0(timer) MMIO32(timer + 0x02C)
+#define TIMER0_CR0 TIMER_CR0(TIMER0)
+#define TIMER1_CR0 TIMER_CR0(TIMER1)
+#define TIMER2_CR0 TIMER_CR0(TIMER2)
+#define TIMER3_CR0 TIMER_CR0(TIMER3)
+
+/* Capture Register 1 */
+#define TIMER_CR1(timer) MMIO32(timer + 0x030)
+#define TIMER0_CR1 TIMER_CR1(TIMER0)
+#define TIMER1_CR1 TIMER_CR1(TIMER1)
+#define TIMER2_CR1 TIMER_CR1(TIMER2)
+#define TIMER3_CR1 TIMER_CR1(TIMER3)
+
+/* Capture Register 2 */
+#define TIMER_CR2(timer) MMIO32(timer + 0x034)
+#define TIMER0_CR2 TIMER_CR2(TIMER0)
+#define TIMER1_CR2 TIMER_CR2(TIMER1)
+#define TIMER2_CR2 TIMER_CR2(TIMER2)
+#define TIMER3_CR2 TIMER_CR2(TIMER3)
+
+/* Capture Register 3 */
+#define TIMER_CR3(timer) MMIO32(timer + 0x038)
+#define TIMER0_CR3 TIMER_CR3(TIMER0)
+#define TIMER1_CR3 TIMER_CR3(TIMER1)
+#define TIMER2_CR3 TIMER_CR3(TIMER2)
+#define TIMER3_CR3 TIMER_CR3(TIMER3)
+
+/* External Match Register */
+#define TIMER_EMR(timer) MMIO32(timer + 0x03C)
+#define TIMER0_EMR TIMER_EMR(TIMER0)
+#define TIMER1_EMR TIMER_EMR(TIMER1)
+#define TIMER2_EMR TIMER_EMR(TIMER2)
+#define TIMER3_EMR TIMER_EMR(TIMER3)
+
+/* Count Control Register */
+#define TIMER_CTCR(timer) MMIO32(timer + 0x070)
+#define TIMER0_CTCR TIMER_CTCR(TIMER0)
+#define TIMER1_CTCR TIMER_CTCR(TIMER1)
+#define TIMER2_CTCR TIMER_CTCR(TIMER2)
+#define TIMER3_CTCR TIMER_CTCR(TIMER3)
+
+/* --- TIMERx_IR values ----------------------------------------------------- */
+
+#define TIMER_IR_MR0INT (1 << 0)
+#define TIMER_IR_MR1INT (1 << 1)
+#define TIMER_IR_MR2INT (1 << 2)
+#define TIMER_IR_MR3INT (1 << 3)
+#define TIMER_IR_CR0INT (1 << 4)
+#define TIMER_IR_CR1INT (1 << 5)
+#define TIMER_IR_CR2INT (1 << 6)
+#define TIMER_IR_CR3INT (1 << 7)
+
+/* --- TIMERx_TCR values --------------------------------------------------- */
+
+#define TIMER_TCR_CEN (1 << 0)
+#define TIMER_TCR_CRST (1 << 1)
+
+/* --- TIMERx_MCR values --------------------------------------------------- */
+
+#define TIMER_MCR_MR0I (1 << 0)
+#define TIMER_MCR_MR0R (1 << 1)
+#define TIMER_MCR_MR0S (1 << 2)
+#define TIMER_MCR_MR1I (1 << 3)
+#define TIMER_MCR_MR1R (1 << 4)
+#define TIMER_MCR_MR1S (1 << 5)
+#define TIMER_MCR_MR2I (1 << 6)
+#define TIMER_MCR_MR2R (1 << 7)
+#define TIMER_MCR_MR2S (1 << 8)
+#define TIMER_MCR_MR3I (1 << 9)
+#define TIMER_MCR_MR3R (1 << 10)
+#define TIMER_MCR_MR3S (1 << 11)
+
+/* --- TIMERx_MCR values --------------------------------------------------- */
+
+#define TIMER_CCR_CAP0RE (1 << 0)
+#define TIMER_CCR_CAP0FE (1 << 1)
+#define TIMER_CCR_CAP0I (1 << 2)
+#define TIMER_CCR_CAP1RE (1 << 3)
+#define TIMER_CCR_CAP1FE (1 << 4)
+#define TIMER_CCR_CAP1I (1 << 5)
+#define TIMER_CCR_CAP2RE (1 << 6)
+#define TIMER_CCR_CAP2FE (1 << 7)
+#define TIMER_CCR_CAP2I (1 << 8)
+#define TIMER_CCR_CAP3RE (1 << 9)
+#define TIMER_CCR_CAP3FE (1 << 10)
+#define TIMER_CCR_CAP3I (1 << 11)
+
+/* --- TIMERx_EMR values --------------------------------------------------- */
+
+#define TIMER_EMR_EM0 (1 << 0)
+#define TIMER_EMR_EM1 (1 << 1)
+#define TIMER_EMR_EM2 (1 << 2)
+#define TIMER_EMR_EM3 (1 << 3)
+#define TIMER_EMR_EMC0_SHIFT 4
+#define TIMER_EMR_EMC0_MASK (0x3 << TIMER_EMR_EMC0_SHIFT)
+#define TIMER_EMR_EMC1_SHIFT 6
+#define TIMER_EMR_EMC1_MASK (0x3 << TIMER_EMR_EMC1_SHIFT)
+#define TIMER_EMR_EMC2_SHIFT 8
+#define TIMER_EMR_EMC2_MASK (0x3 << TIMER_EMR_EMC2_SHIFT)
+#define TIMER_EMR_EMC3_SHIFT 10
+#define TIMER_EMR_EMC3_MASK (0x3 << TIMER_EMR_EMC3_SHIFT)
+
+#define TIMER_EMR_EMC_NOTHING 0x0
+#define TIMER_EMR_EMC_CLEAR 0x1
+#define TIMER_EMR_EMC_SET 0x2
+#define TIMER_EMR_EMC_TOGGLE 0x3
+
+/* --- TIMERx_CTCR values -------------------------------------------------- */
+
+#define TIMER_CTCR_MODE_TIMER (0x0 << 0)
+#define TIMER_CTCR_MODE_COUNTER_RISING (0x1 << 0)
+#define TIMER_CTCR_MODE_COUNTER_FALLING (0x2 << 0)
+#define TIMER_CTCR_MODE_COUNTER_BOTH (0x3 << 0)
+#define TIMER_CTCR_MODE_MASK (0x3 << 0)
+
+#define TIMER_CTCR_CINSEL_CAPN_0 (0x0 << 2)
+#define TIMER_CTCR_CINSEL_CAPN_1 (0x1 << 2)
+#define TIMER_CTCR_CINSEL_CAPN_2 (0x2 << 2)
+#define TIMER_CTCR_CINSEL_CAPN_3 (0x3 << 2)
+#define TIMER_CTCR_CINSEL_MASK (0x3 << 2)
+
+/* --- TIMER function prototypes ------------------------------------------- */
+
+BEGIN_DECLS
+
+void timer_reset(uint32_t timer_peripheral);
+void timer_enable_counter(uint32_t timer_peripheral);
+void timer_disable_counter(uint32_t timer_peripheral);
+uint32_t timer_get_counter(uint32_t timer_peripheral);
+void timer_set_counter(uint32_t timer_peripheral, uint32_t count);
+uint32_t timer_get_prescaler(uint32_t timer_peripheral);
+void timer_set_prescaler(uint32_t timer_peripheral, uint32_t prescaler);
+void timer_set_mode(uint32_t timer_peripheral, uint32_t mode);
+void timer_set_count_input(uint32_t timer_peripheral, uint32_t input);
+
+END_DECLS
+
+/**@}*/
+
+#endif
diff --git a/libopencm3/include/libopencm3/lpc43xx/uart.h b/libopencm3/include/libopencm3/lpc43xx/uart.h
new file mode 100644
index 0000000..28830e3
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc43xx/uart.h
@@ -0,0 +1,438 @@
+/*
+* This file is part of the libopencm3 project.
+*
+* Copyright (C) 2012 Benjamin Vernoux
+*
+* This library is free software: you can redistribute it and/or modify
+* it under the terms of the GNU Lesser General Public License as published by
+* the Free Software Foundation, either version 3 of the License, or
+* (at your option) any later version.
+*
+* This library is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU Lesser General Public License for more details.
+*
+* You should have received a copy of the GNU Lesser General Public License
+* along with this library. If not, see .
+*/
+
+#ifndef LPC43XX_UART_H
+#define LPC43XX_UART_H
+
+#include
+#include
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* UART port base addresses (for convenience) */
+#define UART0 USART0_BASE /* APB0 */
+#define UART1 UART1_BASE /* APB0 */
+#define UART2 USART2_BASE /* APB2 */
+#define UART3 USART3_BASE /* APB2 */
+
+/* --- UART registers ------------------------------------------------------- */
+
+/* Receiver Buffer Register (DLAB=0) Read Only */
+#define UART_RBR(port) MMIO32(port + 0x000) /* 8bits */
+
+/* Transmitter Holding Register (DLAB=0) Write Only */
+#define UART_THR(port) MMIO32(port + 0x000) /* 8bits */
+
+/* Divisor Latch LSB Register (DLAB=1) */
+#define UART_DLL(port) MMIO32(port + 0x000) /* 8bits */
+
+/* Divisor Latch MSB Register (DLAB=1) */
+#define UART_DLM(port) MMIO32(port + 0x004) /* 8bits */
+
+/* Interrupt Enable Register (DLAB=0) */
+#define UART_IER(port) MMIO32(port + 0x004)
+
+/* Interrupt ID Register Read Only */
+#define UART_IIR(port) MMIO32(port + 0x008)
+
+/* FIFO Control Register Write Only */
+#define UART_FCR(port) MMIO32(port + 0x008)
+
+/* Line Control Register */
+#define UART_LCR(port) MMIO32(port + 0x00C)
+
+/* MCR only for UART1 */
+
+/* Line Status Register */
+#define UART_LSR(port) MMIO32(port + 0x014)
+
+/* Auto Baud Control Register */
+#define UART_ACR(port) MMIO32(port + 0x020)
+
+/* IrDA Control Register only for UART0/2/3 */
+#define UART_ICR(port) MMIO32(port + 0x024)
+
+/* Fractional Divider Register */
+#define UART_FDR(port) MMIO32(port + 0x028)
+
+/* Oversampling Register only for UART0/2/3 */
+#define UART_OSR(port) MMIO32(port + 0x02C)
+
+/* Half-Duplex enable Register only for UART0/2/3 */
+#define UART_HDEN(port) MMIO32(port + 0x040)
+
+/* Smart card Interface Register Only for UART0/2/3 */
+#define UART_SCICTRL(port) MMIO32(port + 0x048)
+
+/* RS-485/EIA-485 Control Register */
+#define UART_RS485CTRL(port) MMIO32(port + 0x04C)
+
+/* RS-485/EIA-485 Address Match Register */
+#define UART_RS485ADRMATCH(port) MMIO32(port + 0x050)
+
+/* RS-485/EIA-485 Direction Control Delay Register */
+#define UART_RS485DLY(port) MMIO32(port + 0x054)
+
+/* Synchronous Mode Control Register only for UART0/2/3 */
+#define UART_SYNCCTRL(port) MMIO32(port + 0x058)
+
+/* Transmit Enable Register */
+#define UART_TER(port) MMIO32(port + 0x05C)
+
+/* --------------------- BIT DEFINITIONS ----------------------------------- */
+/***********************************************************************
+* Macro defines for Macro defines for UARTn Receiver Buffer Register
+**********************************************************************/
+/* UART Received Buffer mask bit (8 bits) */
+#define UART_RBR_MASKBIT ((uint8_t)0xFF)
+
+/***********************************************************************
+* Macro defines for Macro defines for UARTn Transmit Holding Register
+**********************************************************************/
+/* UART Transmit Holding mask bit (8 bits) */
+#define UART_THR_MASKBIT ((uint8_t)0xFF)
+
+/***********************************************************************
+* Macro defines for Macro defines for UARTn Divisor Latch LSB register
+**********************************************************************/
+/* Macro for loading least significant halfs of divisors */
+#define UART_LOAD_DLL(div) ((div) & 0xFF)
+
+/* Divisor latch LSB bit mask */
+#define UART_DLL_MASKBIT ((uint8_t)0xFF)
+
+/***********************************************************************
+* Macro defines for Macro defines for UARTn Divisor Latch MSB register
+**********************************************************************/
+/* Divisor latch MSB bit mask */
+#define UART_DLM_MASKBIT ((uint8_t)0xFF)
+
+/* Macro for loading most significant halfs of divisors */
+#define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF)
+
+/***********************************************************************
+* Macro defines for Macro defines for UART interrupt enable register
+**********************************************************************/
+/* RBR Interrupt enable*/
+#define UART_IER_RBRINT_EN (1 << 0)
+/* THR Interrupt enable*/
+#define UART_IER_THREINT_EN (1 << 1)
+/* RX line status interrupt enable*/
+#define UART_IER_RLSINT_EN (1 << 2)
+/* Modem status interrupt enable */
+#define UART1_IER_MSINT_EN (1 << 3)
+/* CTS1 signal transition interrupt enable */
+#define UART1_IER_CTSINT_EN (1 << 7)
+/* Enables the end of auto-baud interrupt */
+#define UART_IER_ABEOINT_EN (1 << 8)
+/* Enables the auto-baud time-out interrupt */
+#define UART_IER_ABTOINT_EN (1 << 9)
+/* UART interrupt enable register bit mask */
+#define UART_IER_BITMASK ((uint32_t)(0x307))
+/* UART1 interrupt enable register bit mask */
+#define UART1_IER_BITMASK ((uint32_t)(0x38F))
+
+/**********************************************************************
+* Macro defines for Macro defines for UART interrupt identification register
+**********************************************************************/
+
+/* Interrupt Status - Active low */
+#define UART_IIR_INTSTAT_PEND (1 << 0)
+/* Interrupt identification: Modem interrupt*/
+#define UART1_IIR_INTID_MODEM (0 << 1)
+/* Interrupt identification: THRE interrupt*/
+#define UART_IIR_INTID_THRE (1 << 1)
+/* Interrupt identification: Receive data available*/
+#define UART_IIR_INTID_RDA (2 << 1)
+/* Interrupt identification: Receive line status*/
+#define UART_IIR_INTID_RLS (3 << 1)
+/* Interrupt identification: Character time-out indicator*/
+#define UART_IIR_INTID_CTI (6 << 1)
+/* Interrupt identification: Interrupt ID mask */
+#define UART_IIR_INTID_MASK (7 << 1)
+/* These bits are equivalent to UnFCR[0] */
+#define UART_IIR_FIFO_EN (3 << 6)
+/* End of auto-baud interrupt */
+#define UART_IIR_ABEO_INT (1 << 8)
+/* Auto-baud time-out interrupt */
+#define UART_IIR_ABTO_INT (1 << 9)
+/* UART interrupt identification register bit mask */
+#define UART_IIR_BITMASK ((uint32_t)(0x3CF))
+
+/**********************************************************************
+* Macro defines for Macro defines for UART FIFO control register
+**********************************************************************/
+/* UART FIFO enable */
+#define UART_FCR_FIFO_EN (1 << 0)
+/* UART FIFO RX reset */
+#define UART_FCR_RX_RS (1 << 1)
+/* UART FIFO TX reset */
+#define UART_FCR_TX_RS (1 << 2)
+/* UART DMA mode selection */
+#define UART_FCR_DMAMODE_SEL (1 << 3)
+/* UART FIFO trigger level 0: 1 character */
+#define UART_FCR_TRG_LEV0 (0 << 6)
+/* UART FIFO trigger level 1: 4 character */
+#define UART_FCR_TRG_LEV1 (1 << 6)
+/* UART FIFO trigger level 2: 8 character */
+#define UART_FCR_TRG_LEV2 (2 << 6)
+/* UART FIFO trigger level 3: 14 character */
+#define UART_FCR_TRG_LEV3 (3 << 6)
+/* UART FIFO control bit mask */
+#define UART_FCR_BITMASK ((uint8_t)(0xCF))
+#define UART_TX_FIFO_SIZE (16)
+
+/**********************************************************************
+* Macro defines for Macro defines for UART line control register
+**********************************************************************/
+/* UART 5 bit data mode */
+#define UART_LCR_WLEN5 (0 << 0)
+/* UART 6 bit data mode */
+#define UART_LCR_WLEN6 (1 << 0)
+/* UART 7 bit data mode */
+#define UART_LCR_WLEN7 (2 << 0)
+/* UART 8 bit data mode */
+#define UART_LCR_WLEN8 (3 << 0)
+/* UART One Stop Bits */
+#define UART_LCR_ONE_STOPBIT (0 << 2)
+/* UART Two Stop Bits */
+#define UART_LCR_TWO_STOPBIT (1 << 2)
+
+/* UART Parity Disabled / No Parity */
+#define UART_LCR_NO_PARITY (0 << 3)
+/* UART Parity Enable */
+#define UART_LCR_PARITY_EN (1 << 3)
+/* UART Odd Parity Select */
+#define UART_LCR_PARITY_ODD (0 << 4)
+/* UART Even Parity Select */
+#define UART_LCR_PARITY_EVEN (1 << 4)
+/* UART force 1 stick parity */
+#define UART_LCR_PARITY_SP_1 (1 << 5)
+/* UART force 0 stick parity */
+#define UART_LCR_PARITY_SP_0 ((1 << 5) | (1 << 4))
+/* UART Transmission Break enable */
+#define UART_LCR_BREAK_EN (1 << 6)
+/* UART Divisor Latches Access bit enable */
+#define UART_LCR_DLAB_EN (1 << 7)
+/* UART line control bit mask */
+#define UART_LCR_BITMASK ((uint8_t)(0xFF))
+
+/**********************************************************************
+* Macro defines for Macro defines for UART line status register
+**********************************************************************/
+/* Line status register: Receive data ready */
+#define UART_LSR_RDR (1 << 0)
+/* Line status register: Overrun error */
+#define UART_LSR_OE (1 << 1)
+/* Line status register: Parity error */
+#define UART_LSR_PE (1 << 2)
+/* Line status register: Framing error */
+#define UART_LSR_FE (1 << 3)
+/* Line status register: Break interrupt */
+#define UART_LSR_BI (1 << 4)
+/* Line status register: Transmit holding register empty */
+#define UART_LSR_THRE (1 << 5)
+/* Line status register: Transmitter empty */
+#define UART_LSR_TEMT (1 << 6)
+/* Error in RX FIFO */
+#define UART_LSR_RXFE (1 << 7)
+/* UART Line status bit mask */
+#define UART_LSR_BITMASK ((uint8_t)(0xFF))
+#define UART_LSR_ERROR_MASK \
+ (UART_LSR_OE | UART_LSR_PE | UART_LSR_FE | UART_LSR_BI | UART_LSR_RXFE)
+
+/**********************************************************************
+* Macro defines for Macro defines for UART Scratch Pad Register
+**********************************************************************/
+
+/* UART Scratch Pad bit mask */
+#define UART_SCR_BIMASK ((uint8_t)(0xFF))
+
+/***********************************************************************
+* Macro defines for Macro defines for UART Auto baudrate control register
+**********************************************************************/
+
+/* UART Auto-baud start */
+#define UART_ACR_START (1 << 0)
+/* UART Auto baudrate Mode 1 */
+#define UART_ACR_MODE (1 << 1)
+/* UART Auto baudrate restart */
+#define UART_ACR_AUTO_RESTART (1 << 2)
+/* UART End of auto-baud interrupt clear */
+#define UART_ACR_ABEOINT_CLR (1 << 8)
+/* UART Auto-baud time-out interrupt clear */
+#define UART_ACR_ABTOINT_CLR (1 << 9)
+/* UART Auto Baudrate register bit mask */
+#define UART_ACR_BITMASK ((uint32_t)(0x307))
+
+/*********************************************************************
+* Macro defines for Macro defines for UART IrDA control register
+**********************************************************************/
+/* IrDA mode enable */
+#define UART_ICR_IRDAEN (1 << 0)
+/* IrDA serial input inverted */
+#define UART_ICR_IRDAINV (1 << 1)
+/* IrDA fixed pulse width mode */
+#define UART_ICR_FIXPULSE_EN (1 << 2)
+/* PulseDiv - Configures the pulse when FixPulseEn = 1 */
+#define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3))
+/* UART IRDA bit mask */
+#define UART_ICR_BITMASK ((uint32_t)(0x3F))
+
+/**********************************************************************
+* Macro defines for Macro defines for UART half duplex register
+**********************************************************************/
+/* enable half-duplex mode*/
+#define UART_HDEN_HDEN (1 << 0)
+
+/**********************************************************************
+* Macro defines for Macro defines for UART smart card interface control register
+**********************************************************************/
+/* enable asynchronous half-duplex smart card interface*/
+#define UART_SCICTRL_SCIEN (1 << 0)
+/* NACK response is inhibited*/
+#define UART_SCICTRL_NACKDIS (1 << 1)
+/* ISO7816-3 protocol T1 is selected*/
+#define UART_SCICTRL_PROTSEL_T1 (1 << 2)
+/* number of retransmission*/
+#define UART_SCICTRL_TXRETRY(n) ((uint32_t)((n&0x07)<<5))
+/* Extra guard time*/
+#define UART_SCICTRL_GUARDTIME(n) ((uint32_t)((n&0xFF)<<8))
+
+/*********************************************************************
+* Macro defines for Macro defines for UART synchronous control register
+**********************************************************************/
+/* enable synchronous mode*/
+#define UART_SYNCCTRL_SYNC (1 << 0)
+/* synchronous master mode*/
+#define UART_SYNCCTRL_CSRC_MASTER (1 << 1)
+/* sample on falling edge*/
+#define UART_SYNCCTRL_FES (1 << 2)
+/* to be defined*/
+#define UART_SYNCCTRL_TSBYPASS (1 << 3)
+/* continuous running clock enable (master mode only) */
+#define UART_SYNCCTRL_CSCEN (1 << 4)
+/* Do not send start/stop bit */
+#define UART_SYNCCTRL_NOSTARTSTOP (1 << 5)
+/* stop continuous clock */
+#define UART_SYNCCTRL_CCCLR (1 << 6)
+
+/*********************************************************************
+* Macro defines for Macro defines for UART Fractional divider register
+**********************************************************************/
+
+/* Baud-rate generation pre-scaler divisor */
+#define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F))
+/* Baud-rate pre-scaler multiplier value */
+#define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0))
+/* UART Fractional Divider register bit mask */
+#define UART_FDR_BITMASK ((uint32_t)(0xFF))
+
+/*********************************************************************
+* Macro defines for Macro defines for UART Tx Enable register
+**********************************************************************/
+
+#define UART_TER_TXEN (1 << 0) /* Transmit enable bit */
+
+/**********************************************************************
+* Macro defines for Macro defines for UART FIFO Level register
+**********************************************************************/
+/* Reflects the current level of the UART receiver FIFO */
+#define UART_FIFOLVL_RX(n) ((uint32_t)(n&0x0F))
+/* Reflects the current level of the UART transmitter FIFO */
+#define UART_FIFOLVL_TX(n) ((uint32_t)((n>>8)&0x0F))
+/* UART FIFO Level Register bit mask */
+#define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F))
+
+/*********************************************************************
+* UART enum
+**********************************************************************/
+
+/*
+* UART Databit type definitions
+*/
+typedef enum {
+ UART_DATABIT_5 = UART_LCR_WLEN5,/* UART 5 bit data mode */
+ UART_DATABIT_6 = UART_LCR_WLEN6,/* UART 6 bit data mode */
+ UART_DATABIT_7 = UART_LCR_WLEN7,/* UART 7 bit data mode */
+ UART_DATABIT_8 = UART_LCR_WLEN8/* UART 8 bit data mode */
+} uart_databit_t;
+
+/*
+* UART Stop bit type definitions
+*/
+typedef enum {
+ /* UART 1 Stop Bits Select */
+ UART_STOPBIT_1 = UART_LCR_ONE_STOPBIT,
+ /* UART 2 Stop Bits Select */
+ UART_STOPBIT_2 = UART_LCR_TWO_STOPBIT
+} uart_stopbit_t;
+
+/*
+* UART Parity type definitions
+*/
+typedef enum {
+ /* No parity */
+ UART_PARITY_NONE = UART_LCR_NO_PARITY,
+ /* Odd parity */
+ UART_PARITY_ODD = (UART_LCR_PARITY_ODD | UART_LCR_PARITY_EN),
+ /* Even parity */
+ UART_PARITY_EVEN = (UART_LCR_PARITY_EVEN | UART_LCR_PARITY_EN),
+ /* Forced 1 stick parity */
+ UART_PARITY_SP_1 = (UART_LCR_PARITY_SP_1 | UART_LCR_PARITY_EN),
+ /* Forced 0 stick parity */
+ UART_PARITY_SP_0 = (UART_LCR_PARITY_SP_0 | UART_LCR_PARITY_EN)
+} uart_parity_t;
+
+typedef enum {
+ UART0_NUM = UART0,
+ UART1_NUM = UART1,
+ UART2_NUM = UART2,
+ UART3_NUM = UART3
+} uart_num_t;
+
+typedef enum {
+ UART_NO_ERROR = 0,
+ UART_TIMEOUT_ERROR = 1
+} uart_error_t;
+
+typedef enum {
+ UART_RX_NO_DATA = 0,
+ UART_RX_DATA_READY = 1,
+ UART_RX_DATA_ERROR = 2
+} uart_rx_data_ready_t;
+
+/* function prototypes */
+
+BEGIN_DECLS
+
+/* Init UART and set PLL1 as clock source (PCLK) */
+void uart_init(uart_num_t uart_num, uart_databit_t data_nb_bits,
+ uart_stopbit_t data_nb_stop, uart_parity_t data_parity,
+ uint16_t uart_divisor, uint8_t uart_divaddval, uint8_t uart_mulval);
+
+uart_rx_data_ready_t uart_rx_data_ready(uart_num_t uart_num);
+uint8_t uart_read(uart_num_t uart_num);
+uint8_t uart_read_timeout(uart_num_t uart_num, uint32_t rx_timeout_nb_cycles,
+ uart_error_t *error);
+void uart_write(uart_num_t uart_num, uint8_t data);
+
+END_DECLS
+
+#endif
diff --git a/libopencm3/include/libopencm3/lpc43xx/usb.h b/libopencm3/include/libopencm3/lpc43xx/usb.h
new file mode 100644
index 0000000..2f1f156
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc43xx/usb.h
@@ -0,0 +1,1337 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Michael Ossmann
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LPC43XX_USB_H
+#define LPC43XX_USB_H
+
+#include
+#include
+
+#define BIT_MASK(base_name) \
+ (((1 << base_name##_WIDTH) - 1) << base_name##_SHIFT)
+#define BIT_ARG(base_name, x) ((x) << base_name##_SHIFT)
+
+/* USB device data structures */
+
+/* "The software must ensure that no interface data structure reachable
+ * by the Device controller crosses a 4kB-page boundary."
+ */
+
+/* --- Endpoint Transfer Descriptor (dTD) ---------------------------------- */
+
+typedef struct usb_transfer_descriptor_t usb_transfer_descriptor_t;
+struct usb_transfer_descriptor_t {
+ volatile usb_transfer_descriptor_t *next_dtd_pointer;
+ volatile uint32_t total_bytes;
+ volatile uint32_t buffer_pointer_page[5];
+ volatile uint32_t _reserved;
+};
+
+#define USB_TD_NEXT_DTD_POINTER_TERMINATE_SHIFT (0)
+#define USB_TD_NEXT_DTD_POINTER_TERMINATE \
+ ((volatile usb_transfer_descriptor_t *) \
+ (1 << USB_TD_NEXT_DTD_POINTER_TERMINATE_SHIFT))
+
+#define USB_TD_DTD_TOKEN_TOTAL_BYTES_SHIFT (16)
+#define USB_TD_DTD_TOKEN_TOTAL_BYTES_WIDTH (15)
+#define USB_TD_DTD_TOKEN_TOTAL_BYTES_MASK BIT_MASK(USB_TD_DTD_TOKEN_TOTAL_BYTES)
+#define USB_TD_DTD_TOKEN_TOTAL_BYTES(x) BIT_ARG(USB_TD_DTD_TOKEN_TOTAL_BYTES, x)
+
+#define USB_TD_DTD_TOKEN_IOC_SHIFT (15)
+#define USB_TD_DTD_TOKEN_IOC (1 << USB_TD_DTD_TOKEN_IOC_SHIFT)
+
+#define USB_TD_DTD_TOKEN_MULTO_SHIFT (10)
+#define USB_TD_DTD_TOKEN_MULTO_WIDTH (2)
+#define USB_TD_DTD_TOKEN_MULTO_MASK BIT_MASK(USB_TD_DTD_TOKEN_MULTO)
+#define USB_TD_DTD_TOKEN_MULTO(x) BIT_ARG(USB_TD_DTD_TOKEN_MULTO, x)
+
+#define USB_TD_DTD_TOKEN_STATUS_ACTIVE_SHIFT (7)
+#define USB_TD_DTD_TOKEN_STATUS_ACTIVE \
+ (1 << USB_TD_DTD_TOKEN_STATUS_ACTIVE_SHIFT)
+
+#define USB_TD_DTD_TOKEN_STATUS_HALTED_SHIFT (6)
+#define USB_TD_DTD_TOKEN_STATUS_HALTED \
+ (1 << USB_TD_DTD_TOKEN_STATUS_HALTED_SHIFT)
+
+#define USB_TD_DTD_TOKEN_STATUS_BUFFER_ERROR_SHIFT (5)
+#define USB_TD_DTD_TOKEN_STATUS_BUFFER_ERROR \
+ (1 << USB_TD_DTD_TOKEN_STATUS_BUFFER_ERROR_SHIFT)
+
+#define USB_TD_DTD_TOKEN_STATUS_TRANSACTION_ERROR_SHIFT (3)
+#define USB_TD_DTD_TOKEN_STATUS_TRANSACTION_ERROR \
+ (1 << USB_TD_DTD_TOKEN_STATUS_TRANSACTION_ERROR_SHIFT)
+
+/* --- Endpoint Queue Head (dQH) ------------------------------------------- */
+
+/* - must be aligned on 64-byte boundaries. */
+typedef struct {
+ volatile uint32_t capabilities;
+ volatile usb_transfer_descriptor_t *current_dtd_pointer;
+ volatile usb_transfer_descriptor_t *next_dtd_pointer;
+ volatile uint32_t total_bytes;
+ volatile uint32_t buffer_pointer_page[5];
+ volatile uint32_t _reserved_0;
+ volatile uint8_t setup[8];
+ volatile uint32_t _reserved_1[4];
+} usb_queue_head_t;
+
+#define USB_QH_CAPABILITIES_IOS_SHIFT (15)
+#define USB_QH_CAPABILITIES_IOS (1 << USB_QH_CAPABILITIES_IOS_SHIFT)
+
+#define USB_QH_CAPABILITIES_MPL_SHIFT (16)
+#define USB_QH_CAPABILITIES_MPL_WIDTH (11)
+#define USB_QH_CAPABILITIES_MPL_MASK BIT_MASK(USB_QH_CAPABILITIES_MPL)
+#define USB_QH_CAPABILITIES_MPL(x) BIT_ARG(USB_QH_CAPABILITIES_MPL, x)
+
+#define USB_QH_CAPABILITIES_ZLT_SHIFT (29)
+#define USB_QH_CAPABILITIES_ZLT (1 << USB_QH_CAPABILITIES_ZLT_SHIFT)
+
+#define USB_QH_CAPABILITIES_MULT_SHIFT (30)
+#define USB_QH_CAPABILITIES_MULT_WIDTH (2)
+#define USB_QH_CAPABILITIES_MULT_MASK BIT_MASK(USB_QH_CAPABILITIES_MULT)
+#define USB_QH_CAPABILITIES_MULT(x) BIT_ARG(USB_QH_CAPABILITIES_MULT, x)
+
+/* --- USB0 registers ------------------------------------------------------ */
+
+/* Device/host capability registers */
+
+/* Capability register length */
+#define USB0_CAPLENGTH MMIO32(USB0_BASE + 0x100)
+
+/* Host controller structural parameters */
+#define USB0_HCSPARAMS MMIO32(USB0_BASE + 0x104)
+
+/* Host controller capability parameters */
+#define USB0_HCCPARAMS MMIO32(USB0_BASE + 0x108)
+
+/* Device interface version number */
+#define USB0_DCIVERSION MMIO32(USB0_BASE + 0x120)
+
+/* Device controller capability parameters */
+#define USB0_DCCPARAMS MMIO32(USB0_BASE + 0x124)
+
+
+/* Device/host operational registers */
+
+/* USB command (device mode) */
+#define USB0_USBCMD_D MMIO32(USB0_BASE + 0x140)
+
+/* USB command (host mode) */
+#define USB0_USBCMD_H MMIO32(USB0_BASE + 0x140)
+
+/* USB status (device mode) */
+#define USB0_USBSTS_D MMIO32(USB0_BASE + 0x144)
+
+/* USB status (host mode) */
+#define USB0_USBSTS_H MMIO32(USB0_BASE + 0x144)
+
+/* USB interrupt enable (device mode) */
+#define USB0_USBINTR_D MMIO32(USB0_BASE + 0x148)
+
+/* USB interrupt enable (host mode) */
+#define USB0_USBINTR_H MMIO32(USB0_BASE + 0x148)
+
+/* USB frame index (device mode) */
+#define USB0_FRINDEX_D MMIO32(USB0_BASE + 0x14C)
+
+/* USB frame index (host mode) */
+#define USB0_FRINDEX_H MMIO32(USB0_BASE + 0x14C)
+
+/* USB device address (device mode) */
+#define USB0_DEVICEADDR MMIO32(USB0_BASE + 0x154)
+
+/* Frame list base address (host mode) */
+#define USB0_PERIODICLISTBASE MMIO32(USB0_BASE + 0x154)
+
+/* Address of endpoint list in memory */
+#define USB0_ENDPOINTLISTADDR MMIO32(USB0_BASE + 0x158)
+
+/* Asynchronous list address */
+#define USB0_ASYNCLISTADDR MMIO32(USB0_BASE + 0x158)
+
+/* Asynchronous buffer status for embedded TT (host mode) */
+#define USB0_TTCTRL MMIO32(USB0_BASE + 0x15C)
+
+/* Programmable burst size */
+#define USB0_BURSTSIZE MMIO32(USB0_BASE + 0x160)
+
+/* Host transmit pre-buffer packet tuning (host mode) */
+#define USB0_TXFILLTUNING MMIO32(USB0_BASE + 0x164)
+
+/* Length of virtual frame */
+#define USB0_BINTERVAL MMIO32(USB0_BASE + 0x174)
+
+/* Endpoint NAK (device mode) */
+#define USB0_ENDPTNAK MMIO32(USB0_BASE + 0x178)
+
+/* Endpoint NAK Enable (device mode) */
+#define USB0_ENDPTNAKEN MMIO32(USB0_BASE + 0x17C)
+
+/* Port 1 status/control (device mode) */
+#define USB0_PORTSC1_D MMIO32(USB0_BASE + 0x184)
+
+/* Port 1 status/control (host mode) */
+#define USB0_PORTSC1_H MMIO32(USB0_BASE + 0x184)
+
+/* OTG status and control */
+#define USB0_OTGSC MMIO32(USB0_BASE + 0x1A4)
+
+/* USB device mode (device mode) */
+#define USB0_USBMODE_D MMIO32(USB0_BASE + 0x1A8)
+
+/* USB device mode (host mode) */
+#define USB0_USBMODE_H MMIO32(USB0_BASE + 0x1A8)
+
+
+/* Device endpoint registers */
+
+/* Endpoint setup status */
+#define USB0_ENDPTSETUPSTAT MMIO32(USB0_BASE + 0x1AC)
+
+/* Endpoint initialization */
+#define USB0_ENDPTPRIME MMIO32(USB0_BASE + 0x1B0)
+
+/* Endpoint de-initialization */
+#define USB0_ENDPTFLUSH MMIO32(USB0_BASE + 0x1B4)
+
+/* Endpoint status */
+#define USB0_ENDPTSTAT MMIO32(USB0_BASE + 0x1B8)
+
+/* Endpoint complete */
+#define USB0_ENDPTCOMPLETE MMIO32(USB0_BASE + 0x1BC)
+
+/* Endpoint control */
+#define USB0_ENDPTCTRL(logical_ep) MMIO32(USB0_BASE + 0x1C0 + \
+ (logical_ep * 4))
+
+/* Endpoint control 0 */
+#define USB0_ENDPTCTRL0 USB0_ENDPTCTRL(0)
+
+/* Endpoint control 1 */
+#define USB0_ENDPTCTRL1 USB0_ENDPTCTRL(1)
+
+/* Endpoint control 2 */
+#define USB0_ENDPTCTRL2 USB0_ENDPTCTRL(2)
+
+/* Endpoint control 3 */
+#define USB0_ENDPTCTRL3 USB0_ENDPTCTRL(3)
+
+/* Endpoint control 4 */
+#define USB0_ENDPTCTRL4 USB0_ENDPTCTRL(4)
+
+/* Endpoint control 5 */
+#define USB0_ENDPTCTRL5 USB0_ENDPTCTRL(5)
+
+/* --- USB0_CAPLENGTH values ------------------------------------ */
+
+/* CAPLENGTH: Indicates offset to add to the register base address at the
+ beginning of the Operational Register */
+#define USB0_CAPLENGTH_CAPLENGTH_SHIFT (0)
+#define USB0_CAPLENGTH_CAPLENGTH_MASK (0xff << USB0_CAPLENGTH_CAPLENGTH_SHIFT)
+#define USB0_CAPLENGTH_CAPLENGTH(x) ((x) << USB0_CAPLENGTH_CAPLENGTH_SHIFT)
+
+/* HCIVERSION: BCD encoding of the EHCI revision number supported by this host
+ controller */
+#define USB0_CAPLENGTH_HCIVERSION_SHIFT (8)
+#define USB0_CAPLENGTH_HCIVERSION_MASK \
+ (0xffff << USB0_CAPLENGTH_HCIVERSION_SHIFT)
+#define USB0_CAPLENGTH_HCIVERSION(x) ((x) << USB0_CAPLENGTH_HCIVERSION_SHIFT)
+
+/* --- USB0_HCSPARAMS values ------------------------------------ */
+
+/* N_PORTS: Number of downstream ports */
+#define USB0_HCSPARAMS_N_PORTS_SHIFT (0)
+#define USB0_HCSPARAMS_N_PORTS_MASK (0xf << USB0_HCSPARAMS_N_PORTS_SHIFT)
+#define USB0_HCSPARAMS_N_PORTS(x) ((x) << USB0_HCSPARAMS_N_PORTS_SHIFT)
+
+/* PPC: Port Power Control */
+#define USB0_HCSPARAMS_PPC_SHIFT (4)
+#define USB0_HCSPARAMS_PPC (1 << USB0_HCSPARAMS_PPC_SHIFT)
+
+/* N_PCC: Number of Ports per Companion Controller */
+#define USB0_HCSPARAMS_N_PCC_SHIFT (8)
+#define USB0_HCSPARAMS_N_PCC_MASK (0xf << USB0_HCSPARAMS_N_PCC_SHIFT)
+#define USB0_HCSPARAMS_N_PCC(x) ((x) << USB0_HCSPARAMS_N_PCC_SHIFT)
+
+/* N_CC: Number of Companion Controller */
+#define USB0_HCSPARAMS_N_CC_SHIFT (12)
+#define USB0_HCSPARAMS_N_CC_MASK (0xf << USB0_HCSPARAMS_N_CC_SHIFT)
+#define USB0_HCSPARAMS_N_CC(x) ((x) << USB0_HCSPARAMS_N_CC_SHIFT)
+
+/* PI: Port indicators */
+#define USB0_HCSPARAMS_PI_SHIFT (16)
+#define USB0_HCSPARAMS_PI (1 << USB0_HCSPARAMS_PI_SHIFT)
+
+/* N_PTT: Number of Ports per Transaction Translator */
+#define USB0_HCSPARAMS_N_PTT_SHIFT (20)
+#define USB0_HCSPARAMS_N_PTT_MASK (0xf << USB0_HCSPARAMS_N_PTT_SHIFT)
+#define USB0_HCSPARAMS_N_PTT(x) ((x) << USB0_HCSPARAMS_N_PTT_SHIFT)
+
+/* N_TT: Number of Transaction Translators */
+#define USB0_HCSPARAMS_N_TT_SHIFT (24)
+#define USB0_HCSPARAMS_N_TT_MASK (0xf << USB0_HCSPARAMS_N_TT_SHIFT)
+#define USB0_HCSPARAMS_N_TT(x) ((x) << USB0_HCSPARAMS_N_TT_SHIFT)
+
+/* --- USB0_HCCPARAMS values ------------------------------------ */
+
+/* ADC: 64-bit Addressing Capability */
+#define USB0_HCCPARAMS_ADC_SHIFT (0)
+#define USB0_HCCPARAMS_ADC (1 << USB0_HCCPARAMS_ADC_SHIFT)
+
+/* PFL: Programmable Frame List Flag */
+#define USB0_HCCPARAMS_PFL_SHIFT (1)
+#define USB0_HCCPARAMS_PFL (1 << USB0_HCCPARAMS_PFL_SHIFT)
+
+/* ASP: Asynchronous Schedule Park Capability */
+#define USB0_HCCPARAMS_ASP_SHIFT (2)
+#define USB0_HCCPARAMS_ASP (1 << USB0_HCCPARAMS_ASP_SHIFT)
+
+/* IST: Isochronous Scheduling Threshold */
+#define USB0_HCCPARAMS_IST_SHIFT (4)
+#define USB0_HCCPARAMS_IST_MASK (0xf << USB0_HCCPARAMS_IST_SHIFT)
+#define USB0_HCCPARAMS_IST(x) ((x) << USB0_HCCPARAMS_IST_SHIFT)
+
+/* EECP: EHCI Extended Capabilities Pointer */
+#define USB0_HCCPARAMS_EECP_SHIFT (8)
+#define USB0_HCCPARAMS_EECP_MASK (0xf << USB0_HCCPARAMS_EECP_SHIFT)
+#define USB0_HCCPARAMS_EECP(x) ((x) << USB0_HCCPARAMS_EECP_SHIFT)
+
+/* --- USB0_DCCPARAMS values ------------------------------------ */
+
+/* DEN: Device Endpoint Number */
+#define USB0_DCCPARAMS_DEN_SHIFT (0)
+#define USB0_DCCPARAMS_DEN_MASK (0x1f << USB0_DCCPARAMS_DEN_SHIFT)
+#define USB0_DCCPARAMS_DEN(x) ((x) << USB0_DCCPARAMS_DEN_SHIFT)
+
+/* DC: Device Capable */
+#define USB0_DCCPARAMS_DC_SHIFT (7)
+#define USB0_DCCPARAMS_DC (1 << USB0_DCCPARAMS_DC_SHIFT)
+
+/* HC: Host Capable */
+#define USB0_DCCPARAMS_HC_SHIFT (8)
+#define USB0_DCCPARAMS_HC (1 << USB0_DCCPARAMS_HC_SHIFT)
+
+/* --- USB0_USBCMD_D values ------------------------------------- */
+
+/* RS: Run/Stop */
+#define USB0_USBCMD_D_RS_SHIFT (0)
+#define USB0_USBCMD_D_RS (1 << USB0_USBCMD_D_RS_SHIFT)
+
+/* RST: Controller reset */
+#define USB0_USBCMD_D_RST_SHIFT (1)
+#define USB0_USBCMD_D_RST (1 << USB0_USBCMD_D_RST_SHIFT)
+
+/* SUTW: Setup trip wire */
+#define USB0_USBCMD_D_SUTW_SHIFT (13)
+#define USB0_USBCMD_D_SUTW (1 << USB0_USBCMD_D_SUTW_SHIFT)
+
+/* ATDTW: Add dTD trip wire */
+#define USB0_USBCMD_D_ATDTW_SHIFT (14)
+#define USB0_USBCMD_D_ATDTW (1 << USB0_USBCMD_D_ATDTW_SHIFT)
+
+/* ITC: Interrupt threshold control */
+#define USB0_USBCMD_D_ITC_SHIFT (16)
+#define USB0_USBCMD_D_ITC_MASK (0xff << USB0_USBCMD_D_ITC_SHIFT)
+#define USB0_USBCMD_D_ITC(x) ((x) << USB0_USBCMD_D_ITC_SHIFT)
+
+/* --- USB0_USBCMD_H values ------------------------------------- */
+
+/* RS: Run/Stop */
+#define USB0_USBCMD_H_RS_SHIFT (0)
+#define USB0_USBCMD_H_RS (1 << USB0_USBCMD_H_RS_SHIFT)
+
+/* RST: Controller reset */
+#define USB0_USBCMD_H_RST_SHIFT (1)
+#define USB0_USBCMD_H_RST (1 << USB0_USBCMD_H_RST_SHIFT)
+
+/* FS0: Bit 0 of the Frame List Size bits */
+#define USB0_USBCMD_H_FS0_SHIFT (2)
+#define USB0_USBCMD_H_FS0 (1 << USB0_USBCMD_H_FS0_SHIFT)
+
+/* FS1: Bit 1 of the Frame List Size bits */
+#define USB0_USBCMD_H_FS1_SHIFT (3)
+#define USB0_USBCMD_H_FS1 (1 << USB0_USBCMD_H_FS1_SHIFT)
+
+/* PSE: This bit controls whether the host controller skips processing the
+periodic schedule */
+#define USB0_USBCMD_H_PSE_SHIFT (4)
+#define USB0_USBCMD_H_PSE (1 << USB0_USBCMD_H_PSE_SHIFT)
+
+/* ASE: This bit controls whether the host controller skips processing the
+asynchronous schedule */
+#define USB0_USBCMD_H_ASE_SHIFT (5)
+#define USB0_USBCMD_H_ASE (1 << USB0_USBCMD_H_ASE_SHIFT)
+
+/* IAA: This bit is used as a doorbell by software to tell the host controller
+to issue an interrupt the next time it advances asynchronous schedule */
+#define USB0_USBCMD_H_IAA_SHIFT (6)
+#define USB0_USBCMD_H_IAA (1 << USB0_USBCMD_H_IAA_SHIFT)
+
+/* ASP1_0: Asynchronous schedule park mode */
+#define USB0_USBCMD_H_ASP1_0_SHIFT (8)
+#define USB0_USBCMD_H_ASP1_0_MASK (0x3 << USB0_USBCMD_H_ASP1_0_SHIFT)
+#define USB0_USBCMD_H_ASP1_0(x) ((x) << USB0_USBCMD_H_ASP1_0_SHIFT)
+
+/* ASPE: Asynchronous Schedule Park Mode Enable */
+#define USB0_USBCMD_H_ASPE_SHIFT (11)
+#define USB0_USBCMD_H_ASPE (1 << USB0_USBCMD_H_ASPE_SHIFT)
+
+/* FS2: Bit 2 of the Frame List Size bits */
+#define USB0_USBCMD_H_FS2_SHIFT (15)
+#define USB0_USBCMD_H_FS2 (1 << USB0_USBCMD_H_FS2_SHIFT)
+
+/* ITC: Interrupt threshold control */
+#define USB0_USBCMD_H_ITC_SHIFT (16)
+#define USB0_USBCMD_H_ITC_MASK (0xff << USB0_USBCMD_H_ITC_SHIFT)
+#define USB0_USBCMD_H_ITC(x) ((x) << USB0_USBCMD_H_ITC_SHIFT)
+
+/* --- USB0_USBSTS_D values ------------------------------------- */
+
+/* UI: USB interrupt */
+#define USB0_USBSTS_D_UI_SHIFT (0)
+#define USB0_USBSTS_D_UI (1 << USB0_USBSTS_D_UI_SHIFT)
+
+/* UEI: USB error interrupt */
+#define USB0_USBSTS_D_UEI_SHIFT (1)
+#define USB0_USBSTS_D_UEI (1 << USB0_USBSTS_D_UEI_SHIFT)
+
+/* PCI: Port change detect */
+#define USB0_USBSTS_D_PCI_SHIFT (2)
+#define USB0_USBSTS_D_PCI (1 << USB0_USBSTS_D_PCI_SHIFT)
+
+/* URI: USB reset received */
+#define USB0_USBSTS_D_URI_SHIFT (6)
+#define USB0_USBSTS_D_URI (1 << USB0_USBSTS_D_URI_SHIFT)
+
+/* SRI: SOF received */
+#define USB0_USBSTS_D_SRI_SHIFT (7)
+#define USB0_USBSTS_D_SRI (1 << USB0_USBSTS_D_SRI_SHIFT)
+
+/* SLI: DCSuspend */
+#define USB0_USBSTS_D_SLI_SHIFT (8)
+#define USB0_USBSTS_D_SLI (1 << USB0_USBSTS_D_SLI_SHIFT)
+
+/* NAKI: NAK interrupt bit */
+#define USB0_USBSTS_D_NAKI_SHIFT (16)
+#define USB0_USBSTS_D_NAKI (1 << USB0_USBSTS_D_NAKI_SHIFT)
+
+/* --- USB0_USBSTS_H values ------------------------------------- */
+
+/* UI: USB interrupt */
+#define USB0_USBSTS_H_UI_SHIFT (0)
+#define USB0_USBSTS_H_UI (1 << USB0_USBSTS_H_UI_SHIFT)
+
+/* UEI: USB error interrupt */
+#define USB0_USBSTS_H_UEI_SHIFT (1)
+#define USB0_USBSTS_H_UEI (1 << USB0_USBSTS_H_UEI_SHIFT)
+
+/* PCI: Port change detect */
+#define USB0_USBSTS_H_PCI_SHIFT (2)
+#define USB0_USBSTS_H_PCI (1 << USB0_USBSTS_H_PCI_SHIFT)
+
+/* FRI: Frame list roll-over */
+#define USB0_USBSTS_H_FRI_SHIFT (3)
+#define USB0_USBSTS_H_FRI (1 << USB0_USBSTS_H_FRI_SHIFT)
+
+/* AAI: Interrupt on async advance */
+#define USB0_USBSTS_H_AAI_SHIFT (5)
+#define USB0_USBSTS_H_AAI (1 << USB0_USBSTS_H_AAI_SHIFT)
+
+/* SRI: SOF received */
+#define USB0_USBSTS_H_SRI_SHIFT (7)
+#define USB0_USBSTS_H_SRI (1 << USB0_USBSTS_H_SRI_SHIFT)
+
+/* HCH: HCHalted */
+#define USB0_USBSTS_H_HCH_SHIFT (12)
+#define USB0_USBSTS_H_HCH (1 << USB0_USBSTS_H_HCH_SHIFT)
+
+/* RCL: Reclamation */
+#define USB0_USBSTS_H_RCL_SHIFT (13)
+#define USB0_USBSTS_H_RCL (1 << USB0_USBSTS_H_RCL_SHIFT)
+
+/* PS: Periodic schedule status */
+#define USB0_USBSTS_H_PS_SHIFT (14)
+#define USB0_USBSTS_H_PS (1 << USB0_USBSTS_H_PS_SHIFT)
+
+/* AS: Asynchronous schedule status */
+#define USB0_USBSTS_H_AS_SHIFT (15)
+#define USB0_USBSTS_H_AS (1 << USB0_USBSTS_H_AS_SHIFT)
+
+/* UAI: USB host asynchronous interrupt (USBHSTASYNCINT) */
+#define USB0_USBSTS_H_UAI_SHIFT (18)
+#define USB0_USBSTS_H_UAI (1 << USB0_USBSTS_H_UAI_SHIFT)
+
+/* UPI: USB host periodic interrupt (USBHSTPERINT) */
+#define USB0_USBSTS_H_UPI_SHIFT (19)
+#define USB0_USBSTS_H_UPI (1 << USB0_USBSTS_H_UPI_SHIFT)
+
+/* --- USB0_USBINTR_D values ------------------------------------ */
+
+/* UE: USB interrupt enable */
+#define USB0_USBINTR_D_UE_SHIFT (0)
+#define USB0_USBINTR_D_UE (1 << USB0_USBINTR_D_UE_SHIFT)
+
+/* UEE: USB error interrupt enable */
+#define USB0_USBINTR_D_UEE_SHIFT (1)
+#define USB0_USBINTR_D_UEE (1 << USB0_USBINTR_D_UEE_SHIFT)
+
+/* PCE: Port change detect enable */
+#define USB0_USBINTR_D_PCE_SHIFT (2)
+#define USB0_USBINTR_D_PCE (1 << USB0_USBINTR_D_PCE_SHIFT)
+
+/* URE: USB reset enable */
+#define USB0_USBINTR_D_URE_SHIFT (6)
+#define USB0_USBINTR_D_URE (1 << USB0_USBINTR_D_URE_SHIFT)
+
+/* SRE: SOF received enable */
+#define USB0_USBINTR_D_SRE_SHIFT (7)
+#define USB0_USBINTR_D_SRE (1 << USB0_USBINTR_D_SRE_SHIFT)
+
+/* SLE: Sleep enable */
+#define USB0_USBINTR_D_SLE_SHIFT (8)
+#define USB0_USBINTR_D_SLE (1 << USB0_USBINTR_D_SLE_SHIFT)
+
+/* NAKE: NAK interrupt enable */
+#define USB0_USBINTR_D_NAKE_SHIFT (16)
+#define USB0_USBINTR_D_NAKE (1 << USB0_USBINTR_D_NAKE_SHIFT)
+
+/* --- USB0_USBINTR_H values ------------------------------------ */
+
+/* UE: USB interrupt enable */
+#define USB0_USBINTR_H_UE_SHIFT (0)
+#define USB0_USBINTR_H_UE (1 << USB0_USBINTR_H_UE_SHIFT)
+
+/* UEE: USB error interrupt enable */
+#define USB0_USBINTR_H_UEE_SHIFT (1)
+#define USB0_USBINTR_H_UEE (1 << USB0_USBINTR_H_UEE_SHIFT)
+
+/* PCE: Port change detect enable */
+#define USB0_USBINTR_H_PCE_SHIFT (2)
+#define USB0_USBINTR_H_PCE (1 << USB0_USBINTR_H_PCE_SHIFT)
+
+/* FRE: Frame list rollover enable */
+#define USB0_USBINTR_H_FRE_SHIFT (3)
+#define USB0_USBINTR_H_FRE (1 << USB0_USBINTR_H_FRE_SHIFT)
+
+/* AAE: Interrupt on asynchronous advance enable */
+#define USB0_USBINTR_H_AAE_SHIFT (5)
+#define USB0_USBINTR_H_AAE (1 << USB0_USBINTR_H_AAE_SHIFT)
+
+/* SRE: SOF received enable */
+#define USB0_USBINTR_H_SRE_SHIFT (7)
+#define USB0_USBINTR_H_SRE (1 << USB0_USBINTR_H_SRE_SHIFT)
+
+/* UAIE: USB host asynchronous interrupt enable */
+#define USB0_USBINTR_H_UAIE_SHIFT (18)
+#define USB0_USBINTR_H_UAIE (1 << USB0_USBINTR_H_UAIE_SHIFT)
+
+/* UPIA: USB host periodic interrupt enable */
+#define USB0_USBINTR_H_UPIA_SHIFT (19)
+#define USB0_USBINTR_H_UPIA (1 << USB0_USBINTR_H_UPIA_SHIFT)
+
+/* --- USB0_FRINDEX_D values ------------------------------------ */
+
+/* FRINDEX2_0: Current micro frame number */
+#define USB0_FRINDEX_D_FRINDEX2_0_SHIFT (0)
+#define USB0_FRINDEX_D_FRINDEX2_0_MASK (0x7 << USB0_FRINDEX_D_FRINDEX2_0_SHIFT)
+#define USB0_FRINDEX_D_FRINDEX2_0(x) ((x) << USB0_FRINDEX_D_FRINDEX2_0_SHIFT)
+
+/* FRINDEX13_3: Current frame number of the last frame transmitted */
+#define USB0_FRINDEX_D_FRINDEX13_3_SHIFT (3)
+#define USB0_FRINDEX_D_FRINDEX13_3_MASK \
+ (0x7ff << USB0_FRINDEX_D_FRINDEX13_3_SHIFT)
+#define USB0_FRINDEX_D_FRINDEX13_3(x) ((x) << USB0_FRINDEX_D_FRINDEX13_3_SHIFT)
+
+/* --- USB0_FRINDEX_H values ------------------------------------ */
+
+/* FRINDEX2_0: Current micro frame number */
+#define USB0_FRINDEX_H_FRINDEX2_0_SHIFT (0)
+#define USB0_FRINDEX_H_FRINDEX2_0_MASK (0x7 << USB0_FRINDEX_H_FRINDEX2_0_SHIFT)
+#define USB0_FRINDEX_H_FRINDEX2_0(x) ((x) << USB0_FRINDEX_H_FRINDEX2_0_SHIFT)
+
+/* FRINDEX12_3: Frame list current index */
+#define USB0_FRINDEX_H_FRINDEX12_3_SHIFT (3)
+#define USB0_FRINDEX_H_FRINDEX12_3_MASK \
+ (0x3ff << USB0_FRINDEX_H_FRINDEX12_3_SHIFT)
+#define USB0_FRINDEX_H_FRINDEX12_3(x) ((x) << USB0_FRINDEX_H_FRINDEX12_3_SHIFT)
+
+/* --- USB0_DEVICEADDR values ----------------------------------- */
+
+/* USBADRA: Device address advance */
+#define USB0_DEVICEADDR_USBADRA_SHIFT (24)
+#define USB0_DEVICEADDR_USBADRA (1 << USB0_DEVICEADDR_USBADRA_SHIFT)
+
+/* USBADR: USB device address */
+#define USB0_DEVICEADDR_USBADR_SHIFT (25)
+#define USB0_DEVICEADDR_USBADR_MASK (0x7f << USB0_DEVICEADDR_USBADR_SHIFT)
+#define USB0_DEVICEADDR_USBADR(x) ((x) << USB0_DEVICEADDR_USBADR_SHIFT)
+
+/* --- USB0_PERIODICLISTBASE values ----------------------------- */
+
+/* PERBASE31_12: Base Address (Low) */
+#define USB0_PERIODICLISTBASE_PERBASE31_12_SHIFT (12)
+#define USB0_PERIODICLISTBASE_PERBASE31_12_MASK \
+ (0xfffff << USB0_PERIODICLISTBASE_PERBASE31_12_SHIFT)
+#define USB0_PERIODICLISTBASE_PERBASE31_12(x) \
+ ((x) << USB0_PERIODICLISTBASE_PERBASE31_12_SHIFT)
+
+/* --- USB0_ENDPOINTLISTADDR values ----------------------------- */
+
+/* EPBASE31_11: Endpoint list pointer (low) */
+#define USB0_ENDPOINTLISTADDR_EPBASE31_11_SHIFT (11)
+#define USB0_ENDPOINTLISTADDR_EPBASE31_11_MASK \
+ (0x1fffff << USB0_ENDPOINTLISTADDR_EPBASE31_11_SHIFT)
+#define USB0_ENDPOINTLISTADDR_EPBASE31_11(x) \
+ ((x) << USB0_ENDPOINTLISTADDR_EPBASE31_11_SHIFT)
+
+/* --- USB0_ASYNCLISTADDR values -------------------------------- */
+
+/* ASYBASE31_5: Link pointer (Low) LPL */
+#define USB0_ASYNCLISTADDR_ASYBASE31_5_SHIFT (5)
+#define USB0_ASYNCLISTADDR_ASYBASE31_5_MASK \
+ (0x7ffffff << USB0_ASYNCLISTADDR_ASYBASE31_5_SHIFT)
+#define USB0_ASYNCLISTADDR_ASYBASE31_5(x) \
+ ((x) << USB0_ASYNCLISTADDR_ASYBASE31_5_SHIFT)
+
+/* --- USB0_TTCTRL values --------------------------------------- */
+
+/* TTHA: Hub address when FS or LS device are connected directly */
+#define USB0_TTCTRL_TTHA_SHIFT (24)
+#define USB0_TTCTRL_TTHA_MASK (0x7f << USB0_TTCTRL_TTHA_SHIFT)
+#define USB0_TTCTRL_TTHA(x) ((x) << USB0_TTCTRL_TTHA_SHIFT)
+
+/* --- USB0_BURSTSIZE values ------------------------------------ */
+
+/* RXPBURST: Programmable RX burst length */
+#define USB0_BURSTSIZE_RXPBURST_SHIFT (0)
+#define USB0_BURSTSIZE_RXPBURST_MASK (0xff << USB0_BURSTSIZE_RXPBURST_SHIFT)
+#define USB0_BURSTSIZE_RXPBURST(x) ((x) << USB0_BURSTSIZE_RXPBURST_SHIFT)
+
+/* TXPBURST: Programmable TX burst length */
+#define USB0_BURSTSIZE_TXPBURST_SHIFT (8)
+#define USB0_BURSTSIZE_TXPBURST_MASK (0xff << USB0_BURSTSIZE_TXPBURST_SHIFT)
+#define USB0_BURSTSIZE_TXPBURST(x) ((x) << USB0_BURSTSIZE_TXPBURST_SHIFT)
+
+/* --- USB0_TXFILLTUNING values --------------------------------- */
+
+/* TXSCHOH: FIFO burst threshold */
+#define USB0_TXFILLTUNING_TXSCHOH_SHIFT (0)
+#define USB0_TXFILLTUNING_TXSCHOH_MASK (0xff << USB0_TXFILLTUNING_TXSCHOH_SHIFT)
+#define USB0_TXFILLTUNING_TXSCHOH(x) ((x) << USB0_TXFILLTUNING_TXSCHOH_SHIFT)
+
+/* TXSCHEATLTH: Scheduler health counter */
+#define USB0_TXFILLTUNING_TXSCHEATLTH_SHIFT (8)
+#define USB0_TXFILLTUNING_TXSCHEATLTH_MASK \
+ (0x1f << USB0_TXFILLTUNING_TXSCHEATLTH_SHIFT)
+#define USB0_TXFILLTUNING_TXSCHEATLTH(x) \
+ ((x) << USB0_TXFILLTUNING_TXSCHEATLTH_SHIFT)
+
+/* TXFIFOTHRES: Scheduler overhead */
+#define USB0_TXFILLTUNING_TXFIFOTHRES_SHIFT (16)
+#define USB0_TXFILLTUNING_TXFIFOTHRES_MASK \
+ (0x3f << USB0_TXFILLTUNING_TXFIFOTHRES_SHIFT)
+#define USB0_TXFILLTUNING_TXFIFOTHRES(x) \
+ ((x) << USB0_TXFILLTUNING_TXFIFOTHRES_SHIFT)
+
+/* --- USB0_BINTERVAL values ------------------------------------ */
+
+/* BINT: bInterval value */
+#define USB0_BINTERVAL_BINT_SHIFT (0)
+#define USB0_BINTERVAL_BINT_MASK (0xf << USB0_BINTERVAL_BINT_SHIFT)
+#define USB0_BINTERVAL_BINT(x) ((x) << USB0_BINTERVAL_BINT_SHIFT)
+
+/* --- USB0_ENDPTNAK values ------------------------------------- */
+
+/* EPRN: Rx endpoint NAK */
+#define USB0_ENDPTNAK_EPRN_SHIFT (0)
+#define USB0_ENDPTNAK_EPRN_MASK (0x3f << USB0_ENDPTNAK_EPRN_SHIFT)
+#define USB0_ENDPTNAK_EPRN(x) ((x) << USB0_ENDPTNAK_EPRN_SHIFT)
+
+/* EPTN: Tx endpoint NAK */
+#define USB0_ENDPTNAK_EPTN_SHIFT (16)
+#define USB0_ENDPTNAK_EPTN_MASK (0x3f << USB0_ENDPTNAK_EPTN_SHIFT)
+#define USB0_ENDPTNAK_EPTN(x) ((x) << USB0_ENDPTNAK_EPTN_SHIFT)
+
+/* --- USB0_ENDPTNAKEN values ----------------------------------- */
+
+/* EPRNE: Rx endpoint NAK enable */
+#define USB0_ENDPTNAKEN_EPRNE_SHIFT (0)
+#define USB0_ENDPTNAKEN_EPRNE_MASK (0x3f << USB0_ENDPTNAKEN_EPRNE_SHIFT)
+#define USB0_ENDPTNAKEN_EPRNE(x) ((x) << USB0_ENDPTNAKEN_EPRNE_SHIFT)
+
+/* EPTNE: Tx endpoint NAK */
+#define USB0_ENDPTNAKEN_EPTNE_SHIFT (16)
+#define USB0_ENDPTNAKEN_EPTNE_MASK (0x3f << USB0_ENDPTNAKEN_EPTNE_SHIFT)
+#define USB0_ENDPTNAKEN_EPTNE(x) ((x) << USB0_ENDPTNAKEN_EPTNE_SHIFT)
+
+/* --- USB0_PORTSC1_D values ------------------------------------ */
+
+/* CCS: Current connect status */
+#define USB0_PORTSC1_D_CCS_SHIFT (0)
+#define USB0_PORTSC1_D_CCS (1 << USB0_PORTSC1_D_CCS_SHIFT)
+
+/* PE: Port enable */
+#define USB0_PORTSC1_D_PE_SHIFT (2)
+#define USB0_PORTSC1_D_PE (1 << USB0_PORTSC1_D_PE_SHIFT)
+
+/* PEC: Port enable/disable change */
+#define USB0_PORTSC1_D_PEC_SHIFT (3)
+#define USB0_PORTSC1_D_PEC (1 << USB0_PORTSC1_D_PEC_SHIFT)
+
+/* FPR: Force port resume */
+#define USB0_PORTSC1_D_FPR_SHIFT (6)
+#define USB0_PORTSC1_D_FPR (1 << USB0_PORTSC1_D_FPR_SHIFT)
+
+/* SUSP: Suspend */
+#define USB0_PORTSC1_D_SUSP_SHIFT (7)
+#define USB0_PORTSC1_D_SUSP (1 << USB0_PORTSC1_D_SUSP_SHIFT)
+
+/* PR: Port reset */
+#define USB0_PORTSC1_D_PR_SHIFT (8)
+#define USB0_PORTSC1_D_PR (1 << USB0_PORTSC1_D_PR_SHIFT)
+
+/* HSP: High-speed status */
+#define USB0_PORTSC1_D_HSP_SHIFT (9)
+#define USB0_PORTSC1_D_HSP (1 << USB0_PORTSC1_D_HSP_SHIFT)
+
+/* PIC1_0: Port indicator control */
+#define USB0_PORTSC1_D_PIC1_0_SHIFT (14)
+#define USB0_PORTSC1_D_PIC1_0_MASK (0x3 << USB0_PORTSC1_D_PIC1_0_SHIFT)
+#define USB0_PORTSC1_D_PIC1_0(x) ((x) << USB0_PORTSC1_D_PIC1_0_SHIFT)
+
+/* PTC3_0: Port test control */
+#define USB0_PORTSC1_D_PTC3_0_SHIFT (16)
+#define USB0_PORTSC1_D_PTC3_0_MASK (0xf << USB0_PORTSC1_D_PTC3_0_SHIFT)
+#define USB0_PORTSC1_D_PTC3_0(x) ((x) << USB0_PORTSC1_D_PTC3_0_SHIFT)
+
+/* PHCD: PHY low power suspend - clock disable (PLPSCD) */
+#define USB0_PORTSC1_D_PHCD_SHIFT (23)
+#define USB0_PORTSC1_D_PHCD (1 << USB0_PORTSC1_D_PHCD_SHIFT)
+
+/* PFSC: Port force full speed connect */
+#define USB0_PORTSC1_D_PFSC_SHIFT (24)
+#define USB0_PORTSC1_D_PFSC (1 << USB0_PORTSC1_D_PFSC_SHIFT)
+
+/* PSPD: Port speed */
+#define USB0_PORTSC1_D_PSPD_SHIFT (26)
+#define USB0_PORTSC1_D_PSPD_MASK (0x3 << USB0_PORTSC1_D_PSPD_SHIFT)
+#define USB0_PORTSC1_D_PSPD(x) ((x) << USB0_PORTSC1_D_PSPD_SHIFT)
+
+/* --- USB0_PORTSC1_H values ------------------------------------ */
+
+/* CCS: Current connect status */
+#define USB0_PORTSC1_H_CCS_SHIFT (0)
+#define USB0_PORTSC1_H_CCS (1 << USB0_PORTSC1_H_CCS_SHIFT)
+
+/* CSC: Connect status change */
+#define USB0_PORTSC1_H_CSC_SHIFT (1)
+#define USB0_PORTSC1_H_CSC (1 << USB0_PORTSC1_H_CSC_SHIFT)
+
+/* PE: Port enable */
+#define USB0_PORTSC1_H_PE_SHIFT (2)
+#define USB0_PORTSC1_H_PE (1 << USB0_PORTSC1_H_PE_SHIFT)
+
+/* PEC: Port disable/enable change */
+#define USB0_PORTSC1_H_PEC_SHIFT (3)
+#define USB0_PORTSC1_H_PEC (1 << USB0_PORTSC1_H_PEC_SHIFT)
+
+/* OCA: Over-current active */
+#define USB0_PORTSC1_H_OCA_SHIFT (4)
+#define USB0_PORTSC1_H_OCA (1 << USB0_PORTSC1_H_OCA_SHIFT)
+
+/* OCC: Over-current change */
+#define USB0_PORTSC1_H_OCC_SHIFT (5)
+#define USB0_PORTSC1_H_OCC (1 << USB0_PORTSC1_H_OCC_SHIFT)
+
+/* FPR: Force port resume */
+#define USB0_PORTSC1_H_FPR_SHIFT (6)
+#define USB0_PORTSC1_H_FPR (1 << USB0_PORTSC1_H_FPR_SHIFT)
+
+/* SUSP: Suspend */
+#define USB0_PORTSC1_H_SUSP_SHIFT (7)
+#define USB0_PORTSC1_H_SUSP (1 << USB0_PORTSC1_H_SUSP_SHIFT)
+
+/* PR: Port reset */
+#define USB0_PORTSC1_H_PR_SHIFT (8)
+#define USB0_PORTSC1_H_PR (1 << USB0_PORTSC1_H_PR_SHIFT)
+
+/* HSP: High-speed status */
+#define USB0_PORTSC1_H_HSP_SHIFT (9)
+#define USB0_PORTSC1_H_HSP (1 << USB0_PORTSC1_H_HSP_SHIFT)
+
+/* LS: Line status */
+#define USB0_PORTSC1_H_LS_SHIFT (10)
+#define USB0_PORTSC1_H_LS_MASK (0x3 << USB0_PORTSC1_H_LS_SHIFT)
+#define USB0_PORTSC1_H_LS(x) ((x) << USB0_PORTSC1_H_LS_SHIFT)
+
+/* PP: Port power control */
+#define USB0_PORTSC1_H_PP_SHIFT (12)
+#define USB0_PORTSC1_H_PP (1 << USB0_PORTSC1_H_PP_SHIFT)
+
+/* PIC1_0: Port indicator control */
+#define USB0_PORTSC1_H_PIC1_0_SHIFT (14)
+#define USB0_PORTSC1_H_PIC1_0_MASK (0x3 << USB0_PORTSC1_H_PIC1_0_SHIFT)
+#define USB0_PORTSC1_H_PIC1_0(x) ((x) << USB0_PORTSC1_H_PIC1_0_SHIFT)
+
+/* PTC3_0: Port test control */
+#define USB0_PORTSC1_H_PTC3_0_SHIFT (16)
+#define USB0_PORTSC1_H_PTC3_0_MASK (0xf << USB0_PORTSC1_H_PTC3_0_SHIFT)
+#define USB0_PORTSC1_H_PTC3_0(x) ((x) << USB0_PORTSC1_H_PTC3_0_SHIFT)
+
+/* WKCN: Wake on connect enable (WKCNNT_E) */
+#define USB0_PORTSC1_H_WKCN_SHIFT (20)
+#define USB0_PORTSC1_H_WKCN (1 << USB0_PORTSC1_H_WKCN_SHIFT)
+
+/* WKDC: Wake on disconnect enable (WKDSCNNT_E) */
+#define USB0_PORTSC1_H_WKDC_SHIFT (21)
+#define USB0_PORTSC1_H_WKDC (1 << USB0_PORTSC1_H_WKDC_SHIFT)
+
+/* WKOC: Wake on over-current enable (WKOC_E) */
+#define USB0_PORTSC1_H_WKOC_SHIFT (22)
+#define USB0_PORTSC1_H_WKOC (1 << USB0_PORTSC1_H_WKOC_SHIFT)
+
+/* PHCD: PHY low power suspend - clock disable (PLPSCD) */
+#define USB0_PORTSC1_H_PHCD_SHIFT (23)
+#define USB0_PORTSC1_H_PHCD (1 << USB0_PORTSC1_H_PHCD_SHIFT)
+
+/* PFSC: Port force full speed connect */
+#define USB0_PORTSC1_H_PFSC_SHIFT (24)
+#define USB0_PORTSC1_H_PFSC (1 << USB0_PORTSC1_H_PFSC_SHIFT)
+
+/* PSPD: Port speed */
+#define USB0_PORTSC1_H_PSPD_SHIFT (26)
+#define USB0_PORTSC1_H_PSPD_MASK (0x3 << USB0_PORTSC1_H_PSPD_SHIFT)
+#define USB0_PORTSC1_H_PSPD(x) ((x) << USB0_PORTSC1_H_PSPD_SHIFT)
+
+/* --- USB0_OTGSC values ---------------------------------------- */
+
+/* VD: VBUS_Discharge */
+#define USB0_OTGSC_VD_SHIFT (0)
+#define USB0_OTGSC_VD (1 << USB0_OTGSC_VD_SHIFT)
+
+/* VC: VBUS_Charge */
+#define USB0_OTGSC_VC_SHIFT (1)
+#define USB0_OTGSC_VC (1 << USB0_OTGSC_VC_SHIFT)
+
+/* HAAR: Hardware assist auto_reset */
+#define USB0_OTGSC_HAAR_SHIFT (2)
+#define USB0_OTGSC_HAAR (1 << USB0_OTGSC_HAAR_SHIFT)
+
+/* OT: OTG termination */
+#define USB0_OTGSC_OT_SHIFT (3)
+#define USB0_OTGSC_OT (1 << USB0_OTGSC_OT_SHIFT)
+
+/* DP: Data pulsing */
+#define USB0_OTGSC_DP_SHIFT (4)
+#define USB0_OTGSC_DP (1 << USB0_OTGSC_DP_SHIFT)
+
+/* IDPU: ID pull-up */
+#define USB0_OTGSC_IDPU_SHIFT (5)
+#define USB0_OTGSC_IDPU (1 << USB0_OTGSC_IDPU_SHIFT)
+
+/* HADP: Hardware assist data pulse */
+#define USB0_OTGSC_HADP_SHIFT (6)
+#define USB0_OTGSC_HADP (1 << USB0_OTGSC_HADP_SHIFT)
+
+/* HABA: Hardware assist B-disconnect to A-connect */
+#define USB0_OTGSC_HABA_SHIFT (7)
+#define USB0_OTGSC_HABA (1 << USB0_OTGSC_HABA_SHIFT)
+
+/* ID: USB ID */
+#define USB0_OTGSC_ID_SHIFT (8)
+#define USB0_OTGSC_ID (1 << USB0_OTGSC_ID_SHIFT)
+
+/* AVV: A-VBUS valid */
+#define USB0_OTGSC_AVV_SHIFT (9)
+#define USB0_OTGSC_AVV (1 << USB0_OTGSC_AVV_SHIFT)
+
+/* ASV: A-session valid */
+#define USB0_OTGSC_ASV_SHIFT (10)
+#define USB0_OTGSC_ASV (1 << USB0_OTGSC_ASV_SHIFT)
+
+/* BSV: B-session valid */
+#define USB0_OTGSC_BSV_SHIFT (11)
+#define USB0_OTGSC_BSV (1 << USB0_OTGSC_BSV_SHIFT)
+
+/* BSE: B-session end */
+#define USB0_OTGSC_BSE_SHIFT (12)
+#define USB0_OTGSC_BSE (1 << USB0_OTGSC_BSE_SHIFT)
+
+/* MS1T: 1 millisecond timer toggle */
+#define USB0_OTGSC_MS1T_SHIFT (13)
+#define USB0_OTGSC_MS1T (1 << USB0_OTGSC_MS1T_SHIFT)
+
+/* DPS: Data bus pulsing status */
+#define USB0_OTGSC_DPS_SHIFT (14)
+#define USB0_OTGSC_DPS (1 << USB0_OTGSC_DPS_SHIFT)
+
+/* IDIS: USB ID interrupt status */
+#define USB0_OTGSC_IDIS_SHIFT (16)
+#define USB0_OTGSC_IDIS (1 << USB0_OTGSC_IDIS_SHIFT)
+
+/* AVVIS: A-VBUS valid interrupt status */
+#define USB0_OTGSC_AVVIS_SHIFT (17)
+#define USB0_OTGSC_AVVIS (1 << USB0_OTGSC_AVVIS_SHIFT)
+
+/* ASVIS: A-Session valid interrupt status */
+#define USB0_OTGSC_ASVIS_SHIFT (18)
+#define USB0_OTGSC_ASVIS (1 << USB0_OTGSC_ASVIS_SHIFT)
+
+/* BSVIS: B-Session valid interrupt status */
+#define USB0_OTGSC_BSVIS_SHIFT (19)
+#define USB0_OTGSC_BSVIS (1 << USB0_OTGSC_BSVIS_SHIFT)
+
+/* BSEIS: B-Session end interrupt status */
+#define USB0_OTGSC_BSEIS_SHIFT (20)
+#define USB0_OTGSC_BSEIS (1 << USB0_OTGSC_BSEIS_SHIFT)
+
+/* MS1S: 1 millisecond timer interrupt status */
+#define USB0_OTGSC_MS1S_SHIFT (21)
+#define USB0_OTGSC_MS1S (1 << USB0_OTGSC_MS1S_SHIFT)
+
+/* DPIS: Data pulse interrupt status */
+#define USB0_OTGSC_DPIS_SHIFT (22)
+#define USB0_OTGSC_DPIS (1 << USB0_OTGSC_DPIS_SHIFT)
+
+/* IDIE: USB ID interrupt enable */
+#define USB0_OTGSC_IDIE_SHIFT (24)
+#define USB0_OTGSC_IDIE (1 << USB0_OTGSC_IDIE_SHIFT)
+
+/* AVVIE: A-VBUS valid interrupt enable */
+#define USB0_OTGSC_AVVIE_SHIFT (25)
+#define USB0_OTGSC_AVVIE (1 << USB0_OTGSC_AVVIE_SHIFT)
+
+/* ASVIE: A-session valid interrupt enable */
+#define USB0_OTGSC_ASVIE_SHIFT (26)
+#define USB0_OTGSC_ASVIE (1 << USB0_OTGSC_ASVIE_SHIFT)
+
+/* BSVIE: B-session valid interrupt enable */
+#define USB0_OTGSC_BSVIE_SHIFT (27)
+#define USB0_OTGSC_BSVIE (1 << USB0_OTGSC_BSVIE_SHIFT)
+
+/* BSEIE: B-session end interrupt enable */
+#define USB0_OTGSC_BSEIE_SHIFT (28)
+#define USB0_OTGSC_BSEIE (1 << USB0_OTGSC_BSEIE_SHIFT)
+
+/* MS1E: 1 millisecond timer interrupt enable */
+#define USB0_OTGSC_MS1E_SHIFT (29)
+#define USB0_OTGSC_MS1E (1 << USB0_OTGSC_MS1E_SHIFT)
+
+/* DPIE: Data pulse interrupt enable */
+#define USB0_OTGSC_DPIE_SHIFT (30)
+#define USB0_OTGSC_DPIE (1 << USB0_OTGSC_DPIE_SHIFT)
+
+/* --- USB0_USBMODE_D values ------------------------------------ */
+
+/* CM1_0: Controller mode */
+#define USB0_USBMODE_D_CM1_0_SHIFT (0)
+#define USB0_USBMODE_D_CM1_0_MASK (0x3 << USB0_USBMODE_D_CM1_0_SHIFT)
+#define USB0_USBMODE_D_CM1_0(x) ((x) << USB0_USBMODE_D_CM1_0_SHIFT)
+
+/* ES: Endian select */
+#define USB0_USBMODE_D_ES_SHIFT (2)
+#define USB0_USBMODE_D_ES (1 << USB0_USBMODE_D_ES_SHIFT)
+
+/* SLOM: Setup Lockout mode */
+#define USB0_USBMODE_D_SLOM_SHIFT (3)
+#define USB0_USBMODE_D_SLOM (1 << USB0_USBMODE_D_SLOM_SHIFT)
+
+/* SDIS: Setup Lockout mode */
+#define USB0_USBMODE_D_SDIS_SHIFT (4)
+#define USB0_USBMODE_D_SDIS (1 << USB0_USBMODE_D_SDIS_SHIFT)
+
+/* --- USB0_USBMODE_H values ------------------------------------ */
+
+/* CM: Controller mode */
+#define USB0_USBMODE_H_CM_SHIFT (0)
+#define USB0_USBMODE_H_CM_MASK (0x3 << USB0_USBMODE_H_CM_SHIFT)
+#define USB0_USBMODE_H_CM(x) ((x) << USB0_USBMODE_H_CM_SHIFT)
+
+/* ES: Endian select */
+#define USB0_USBMODE_H_ES_SHIFT (2)
+#define USB0_USBMODE_H_ES (1 << USB0_USBMODE_H_ES_SHIFT)
+
+/* SDIS: Stream disable mode */
+#define USB0_USBMODE_H_SDIS_SHIFT (4)
+#define USB0_USBMODE_H_SDIS (1 << USB0_USBMODE_H_SDIS_SHIFT)
+
+/* VBPS: VBUS power select */
+#define USB0_USBMODE_H_VBPS_SHIFT (5)
+#define USB0_USBMODE_H_VBPS (1 << USB0_USBMODE_H_VBPS_SHIFT)
+
+/* --- USB0_ENDPTSETUPSTAT values ------------------------------- */
+
+/* ENDPSETUPSTAT: Setup endpoint status for logical endpoints 0 to 5 */
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0)
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK \
+ (0x3f << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)
+#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) \
+ ((x) << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)
+
+/* --- USB0_ENDPTPRIME values ----------------------------------- */
+
+/* PERB: Prime endpoint receive buffer for physical OUT endpoints 5 to 0 */
+#define USB0_ENDPTPRIME_PERB_SHIFT (0)
+#define USB0_ENDPTPRIME_PERB_MASK (0x3f << USB0_ENDPTPRIME_PERB_SHIFT)
+#define USB0_ENDPTPRIME_PERB(x) ((x) << USB0_ENDPTPRIME_PERB_SHIFT)
+
+/* PETB: Prime endpoint transmit buffer for physical IN endpoints 5 to 0 */
+#define USB0_ENDPTPRIME_PETB_SHIFT (16)
+#define USB0_ENDPTPRIME_PETB_MASK (0x3f << USB0_ENDPTPRIME_PETB_SHIFT)
+#define USB0_ENDPTPRIME_PETB(x) ((x) << USB0_ENDPTPRIME_PETB_SHIFT)
+
+/* --- USB0_ENDPTFLUSH values ----------------------------------- */
+
+/* FERB: Flush endpoint receive buffer for physical OUT endpoints 5 to 0 */
+#define USB0_ENDPTFLUSH_FERB_SHIFT (0)
+#define USB0_ENDPTFLUSH_FERB_MASK (0x3f << USB0_ENDPTFLUSH_FERB_SHIFT)
+#define USB0_ENDPTFLUSH_FERB(x) ((x) << USB0_ENDPTFLUSH_FERB_SHIFT)
+
+/* FETB: Flush endpoint transmit buffer for physical IN endpoints 5 to 0 */
+#define USB0_ENDPTFLUSH_FETB_SHIFT (16)
+#define USB0_ENDPTFLUSH_FETB_MASK (0x3f << USB0_ENDPTFLUSH_FETB_SHIFT)
+#define USB0_ENDPTFLUSH_FETB(x) ((x) << USB0_ENDPTFLUSH_FETB_SHIFT)
+
+/* --- USB0_ENDPTSTAT values ------------------------------------ */
+
+/* ERBR: Endpoint receive buffer ready for physical OUT endpoints 5 to 0 */
+#define USB0_ENDPTSTAT_ERBR_SHIFT (0)
+#define USB0_ENDPTSTAT_ERBR_MASK (0x3f << USB0_ENDPTSTAT_ERBR_SHIFT)
+#define USB0_ENDPTSTAT_ERBR(x) ((x) << USB0_ENDPTSTAT_ERBR_SHIFT)
+
+/* ETBR: Endpoint transmit buffer ready for physical IN endpoints 3 to 0 */
+#define USB0_ENDPTSTAT_ETBR_SHIFT (16)
+#define USB0_ENDPTSTAT_ETBR_MASK (0x3f << USB0_ENDPTSTAT_ETBR_SHIFT)
+#define USB0_ENDPTSTAT_ETBR(x) ((x) << USB0_ENDPTSTAT_ETBR_SHIFT)
+
+/* --- USB0_ENDPTCOMPLETE values -------------------------------- */
+
+/* ERCE: Endpoint receive complete event for physical OUT endpoints 5 to 0 */
+#define USB0_ENDPTCOMPLETE_ERCE_SHIFT (0)
+#define USB0_ENDPTCOMPLETE_ERCE_MASK (0x3f << USB0_ENDPTCOMPLETE_ERCE_SHIFT)
+#define USB0_ENDPTCOMPLETE_ERCE(x) ((x) << USB0_ENDPTCOMPLETE_ERCE_SHIFT)
+
+/* ETCE: Endpoint transmit complete event for physical IN endpoints 5 to 0 */
+#define USB0_ENDPTCOMPLETE_ETCE_SHIFT (16)
+#define USB0_ENDPTCOMPLETE_ETCE_MASK (0x3f << USB0_ENDPTCOMPLETE_ETCE_SHIFT)
+#define USB0_ENDPTCOMPLETE_ETCE(x) ((x) << USB0_ENDPTCOMPLETE_ETCE_SHIFT)
+
+/* --- USB0_ENDPTCTRL0 values ----------------------------------- */
+
+/* RXS: Rx endpoint stall */
+#define USB0_ENDPTCTRL0_RXS_SHIFT (0)
+#define USB0_ENDPTCTRL0_RXS (1 << USB0_ENDPTCTRL0_RXS_SHIFT)
+
+/* RXT1_0: Endpoint type */
+#define USB0_ENDPTCTRL0_RXT1_0_SHIFT (2)
+#define USB0_ENDPTCTRL0_RXT1_0_MASK (0x3 << USB0_ENDPTCTRL0_RXT1_0_SHIFT)
+#define USB0_ENDPTCTRL0_RXT1_0(x) ((x) << USB0_ENDPTCTRL0_RXT1_0_SHIFT)
+
+/* RXE: Rx endpoint enable */
+#define USB0_ENDPTCTRL0_RXE_SHIFT (7)
+#define USB0_ENDPTCTRL0_RXE (1 << USB0_ENDPTCTRL0_RXE_SHIFT)
+
+/* TXS: Tx endpoint stall */
+#define USB0_ENDPTCTRL0_TXS_SHIFT (16)
+#define USB0_ENDPTCTRL0_TXS (1 << USB0_ENDPTCTRL0_TXS_SHIFT)
+
+/* TXT1_0: Endpoint type */
+#define USB0_ENDPTCTRL0_TXT1_0_SHIFT (18)
+#define USB0_ENDPTCTRL0_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL0_TXT1_0_SHIFT)
+#define USB0_ENDPTCTRL0_TXT1_0(x) ((x) << USB0_ENDPTCTRL0_TXT1_0_SHIFT)
+
+/* TXE: Tx endpoint enable */
+#define USB0_ENDPTCTRL0_TXE_SHIFT (23)
+#define USB0_ENDPTCTRL0_TXE (1 << USB0_ENDPTCTRL0_TXE_SHIFT)
+
+/* --- USB0_ENDPTCTRL1 values ----------------------------------- */
+
+/* RXS: Rx endpoint stall */
+#define USB0_ENDPTCTRL1_RXS_SHIFT (0)
+#define USB0_ENDPTCTRL1_RXS (1 << USB0_ENDPTCTRL1_RXS_SHIFT)
+
+/* RXT: Endpoint type */
+#define USB0_ENDPTCTRL1_RXT_SHIFT (2)
+#define USB0_ENDPTCTRL1_RXT_MASK (0x3 << USB0_ENDPTCTRL1_RXT_SHIFT)
+#define USB0_ENDPTCTRL1_RXT(x) ((x) << USB0_ENDPTCTRL1_RXT_SHIFT)
+
+/* RXI: Rx data toggle inhibit */
+#define USB0_ENDPTCTRL1_RXI_SHIFT (5)
+#define USB0_ENDPTCTRL1_RXI (1 << USB0_ENDPTCTRL1_RXI_SHIFT)
+
+/* RXR: Rx data toggle reset */
+#define USB0_ENDPTCTRL1_RXR_SHIFT (6)
+#define USB0_ENDPTCTRL1_RXR (1 << USB0_ENDPTCTRL1_RXR_SHIFT)
+
+/* RXE: Rx endpoint enable */
+#define USB0_ENDPTCTRL1_RXE_SHIFT (7)
+#define USB0_ENDPTCTRL1_RXE (1 << USB0_ENDPTCTRL1_RXE_SHIFT)
+
+/* TXS: Tx endpoint stall */
+#define USB0_ENDPTCTRL1_TXS_SHIFT (16)
+#define USB0_ENDPTCTRL1_TXS (1 << USB0_ENDPTCTRL1_TXS_SHIFT)
+
+/* TXT1_0: Tx Endpoint type */
+#define USB0_ENDPTCTRL1_TXT1_0_SHIFT (18)
+#define USB0_ENDPTCTRL1_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL1_TXT1_0_SHIFT)
+#define USB0_ENDPTCTRL1_TXT1_0(x) ((x) << USB0_ENDPTCTRL1_TXT1_0_SHIFT)
+
+/* TXI: Tx data toggle inhibit */
+#define USB0_ENDPTCTRL1_TXI_SHIFT (21)
+#define USB0_ENDPTCTRL1_TXI (1 << USB0_ENDPTCTRL1_TXI_SHIFT)
+
+/* TXR: Tx data toggle reset */
+#define USB0_ENDPTCTRL1_TXR_SHIFT (22)
+#define USB0_ENDPTCTRL1_TXR (1 << USB0_ENDPTCTRL1_TXR_SHIFT)
+
+/* TXE: Tx endpoint enable */
+#define USB0_ENDPTCTRL1_TXE_SHIFT (23)
+#define USB0_ENDPTCTRL1_TXE (1 << USB0_ENDPTCTRL1_TXE_SHIFT)
+
+/* --- USB0_ENDPTCTRL2 values ----------------------------------- */
+
+/* RXS: Rx endpoint stall */
+#define USB0_ENDPTCTRL2_RXS_SHIFT (0)
+#define USB0_ENDPTCTRL2_RXS (1 << USB0_ENDPTCTRL2_RXS_SHIFT)
+
+/* RXT: Endpoint type */
+#define USB0_ENDPTCTRL2_RXT_SHIFT (2)
+#define USB0_ENDPTCTRL2_RXT_MASK (0x3 << USB0_ENDPTCTRL2_RXT_SHIFT)
+#define USB0_ENDPTCTRL2_RXT(x) ((x) << USB0_ENDPTCTRL2_RXT_SHIFT)
+
+/* RXI: Rx data toggle inhibit */
+#define USB0_ENDPTCTRL2_RXI_SHIFT (5)
+#define USB0_ENDPTCTRL2_RXI (1 << USB0_ENDPTCTRL2_RXI_SHIFT)
+
+/* RXR: Rx data toggle reset */
+#define USB0_ENDPTCTRL2_RXR_SHIFT (6)
+#define USB0_ENDPTCTRL2_RXR (1 << USB0_ENDPTCTRL2_RXR_SHIFT)
+
+/* RXE: Rx endpoint enable */
+#define USB0_ENDPTCTRL2_RXE_SHIFT (7)
+#define USB0_ENDPTCTRL2_RXE (1 << USB0_ENDPTCTRL2_RXE_SHIFT)
+
+/* TXS: Tx endpoint stall */
+#define USB0_ENDPTCTRL2_TXS_SHIFT (16)
+#define USB0_ENDPTCTRL2_TXS (1 << USB0_ENDPTCTRL2_TXS_SHIFT)
+
+/* TXT1_0: Tx Endpoint type */
+#define USB0_ENDPTCTRL2_TXT1_0_SHIFT (18)
+#define USB0_ENDPTCTRL2_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL2_TXT1_0_SHIFT)
+#define USB0_ENDPTCTRL2_TXT1_0(x) ((x) << USB0_ENDPTCTRL2_TXT1_0_SHIFT)
+
+/* TXI: Tx data toggle inhibit */
+#define USB0_ENDPTCTRL2_TXI_SHIFT (21)
+#define USB0_ENDPTCTRL2_TXI (1 << USB0_ENDPTCTRL2_TXI_SHIFT)
+
+/* TXR: Tx data toggle reset */
+#define USB0_ENDPTCTRL2_TXR_SHIFT (22)
+#define USB0_ENDPTCTRL2_TXR (1 << USB0_ENDPTCTRL2_TXR_SHIFT)
+
+/* TXE: Tx endpoint enable */
+#define USB0_ENDPTCTRL2_TXE_SHIFT (23)
+#define USB0_ENDPTCTRL2_TXE (1 << USB0_ENDPTCTRL2_TXE_SHIFT)
+
+/* --- USB0_ENDPTCTRL3 values ----------------------------------- */
+
+/* RXS: Rx endpoint stall */
+#define USB0_ENDPTCTRL3_RXS_SHIFT (0)
+#define USB0_ENDPTCTRL3_RXS (1 << USB0_ENDPTCTRL3_RXS_SHIFT)
+
+/* RXT: Endpoint type */
+#define USB0_ENDPTCTRL3_RXT_SHIFT (2)
+#define USB0_ENDPTCTRL3_RXT_MASK (0x3 << USB0_ENDPTCTRL3_RXT_SHIFT)
+#define USB0_ENDPTCTRL3_RXT(x) ((x) << USB0_ENDPTCTRL3_RXT_SHIFT)
+
+/* RXI: Rx data toggle inhibit */
+#define USB0_ENDPTCTRL3_RXI_SHIFT (5)
+#define USB0_ENDPTCTRL3_RXI (1 << USB0_ENDPTCTRL3_RXI_SHIFT)
+
+/* RXR: Rx data toggle reset */
+#define USB0_ENDPTCTRL3_RXR_SHIFT (6)
+#define USB0_ENDPTCTRL3_RXR (1 << USB0_ENDPTCTRL3_RXR_SHIFT)
+
+/* RXE: Rx endpoint enable */
+#define USB0_ENDPTCTRL3_RXE_SHIFT (7)
+#define USB0_ENDPTCTRL3_RXE (1 << USB0_ENDPTCTRL3_RXE_SHIFT)
+
+/* TXS: Tx endpoint stall */
+#define USB0_ENDPTCTRL3_TXS_SHIFT (16)
+#define USB0_ENDPTCTRL3_TXS (1 << USB0_ENDPTCTRL3_TXS_SHIFT)
+
+/* TXT1_0: Tx Endpoint type */
+#define USB0_ENDPTCTRL3_TXT1_0_SHIFT (18)
+#define USB0_ENDPTCTRL3_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL3_TXT1_0_SHIFT)
+#define USB0_ENDPTCTRL3_TXT1_0(x) ((x) << USB0_ENDPTCTRL3_TXT1_0_SHIFT)
+
+/* TXI: Tx data toggle inhibit */
+#define USB0_ENDPTCTRL3_TXI_SHIFT (21)
+#define USB0_ENDPTCTRL3_TXI (1 << USB0_ENDPTCTRL3_TXI_SHIFT)
+
+/* TXR: Tx data toggle reset */
+#define USB0_ENDPTCTRL3_TXR_SHIFT (22)
+#define USB0_ENDPTCTRL3_TXR (1 << USB0_ENDPTCTRL3_TXR_SHIFT)
+
+/* TXE: Tx endpoint enable */
+#define USB0_ENDPTCTRL3_TXE_SHIFT (23)
+#define USB0_ENDPTCTRL3_TXE (1 << USB0_ENDPTCTRL3_TXE_SHIFT)
+
+/* --- USB0_ENDPTCTRL4 values ----------------------------------- */
+
+/* RXS: Rx endpoint stall */
+#define USB0_ENDPTCTRL4_RXS_SHIFT (0)
+#define USB0_ENDPTCTRL4_RXS (1 << USB0_ENDPTCTRL4_RXS_SHIFT)
+
+/* RXT: Endpoint type */
+#define USB0_ENDPTCTRL4_RXT_SHIFT (2)
+#define USB0_ENDPTCTRL4_RXT_MASK (0x3 << USB0_ENDPTCTRL4_RXT_SHIFT)
+#define USB0_ENDPTCTRL4_RXT(x) ((x) << USB0_ENDPTCTRL4_RXT_SHIFT)
+
+/* RXI: Rx data toggle inhibit */
+#define USB0_ENDPTCTRL4_RXI_SHIFT (5)
+#define USB0_ENDPTCTRL4_RXI (1 << USB0_ENDPTCTRL4_RXI_SHIFT)
+
+/* RXR: Rx data toggle reset */
+#define USB0_ENDPTCTRL4_RXR_SHIFT (6)
+#define USB0_ENDPTCTRL4_RXR (1 << USB0_ENDPTCTRL4_RXR_SHIFT)
+
+/* RXE: Rx endpoint enable */
+#define USB0_ENDPTCTRL4_RXE_SHIFT (7)
+#define USB0_ENDPTCTRL4_RXE (1 << USB0_ENDPTCTRL4_RXE_SHIFT)
+
+/* TXS: Tx endpoint stall */
+#define USB0_ENDPTCTRL4_TXS_SHIFT (16)
+#define USB0_ENDPTCTRL4_TXS (1 << USB0_ENDPTCTRL4_TXS_SHIFT)
+
+/* TXT1_0: Tx Endpoint type */
+#define USB0_ENDPTCTRL4_TXT1_0_SHIFT (18)
+#define USB0_ENDPTCTRL4_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL4_TXT1_0_SHIFT)
+#define USB0_ENDPTCTRL4_TXT1_0(x) ((x) << USB0_ENDPTCTRL4_TXT1_0_SHIFT)
+
+/* TXI: Tx data toggle inhibit */
+#define USB0_ENDPTCTRL4_TXI_SHIFT (21)
+#define USB0_ENDPTCTRL4_TXI (1 << USB0_ENDPTCTRL4_TXI_SHIFT)
+
+/* TXR: Tx data toggle reset */
+#define USB0_ENDPTCTRL4_TXR_SHIFT (22)
+#define USB0_ENDPTCTRL4_TXR (1 << USB0_ENDPTCTRL4_TXR_SHIFT)
+
+/* TXE: Tx endpoint enable */
+#define USB0_ENDPTCTRL4_TXE_SHIFT (23)
+#define USB0_ENDPTCTRL4_TXE (1 << USB0_ENDPTCTRL4_TXE_SHIFT)
+
+/* --- USB0_ENDPTCTRL5 values ----------------------------------- */
+
+/* RXS: Rx endpoint stall */
+#define USB0_ENDPTCTRL5_RXS_SHIFT (0)
+#define USB0_ENDPTCTRL5_RXS (1 << USB0_ENDPTCTRL5_RXS_SHIFT)
+
+/* RXT: Endpoint type */
+#define USB0_ENDPTCTRL5_RXT_SHIFT (2)
+#define USB0_ENDPTCTRL5_RXT_MASK (0x3 << USB0_ENDPTCTRL5_RXT_SHIFT)
+#define USB0_ENDPTCTRL5_RXT(x) ((x) << USB0_ENDPTCTRL5_RXT_SHIFT)
+
+/* RXI: Rx data toggle inhibit */
+#define USB0_ENDPTCTRL5_RXI_SHIFT (5)
+#define USB0_ENDPTCTRL5_RXI (1 << USB0_ENDPTCTRL5_RXI_SHIFT)
+
+/* RXR: Rx data toggle reset */
+#define USB0_ENDPTCTRL5_RXR_SHIFT (6)
+#define USB0_ENDPTCTRL5_RXR (1 << USB0_ENDPTCTRL5_RXR_SHIFT)
+
+/* RXE: Rx endpoint enable */
+#define USB0_ENDPTCTRL5_RXE_SHIFT (7)
+#define USB0_ENDPTCTRL5_RXE (1 << USB0_ENDPTCTRL5_RXE_SHIFT)
+
+/* TXS: Tx endpoint stall */
+#define USB0_ENDPTCTRL5_TXS_SHIFT (16)
+#define USB0_ENDPTCTRL5_TXS (1 << USB0_ENDPTCTRL5_TXS_SHIFT)
+
+/* TXT1_0: Tx Endpoint type */
+#define USB0_ENDPTCTRL5_TXT1_0_SHIFT (18)
+#define USB0_ENDPTCTRL5_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL5_TXT1_0_SHIFT)
+#define USB0_ENDPTCTRL5_TXT1_0(x) ((x) << USB0_ENDPTCTRL5_TXT1_0_SHIFT)
+
+/* TXI: Tx data toggle inhibit */
+#define USB0_ENDPTCTRL5_TXI_SHIFT (21)
+#define USB0_ENDPTCTRL5_TXI (1 << USB0_ENDPTCTRL5_TXI_SHIFT)
+
+/* TXR: Tx data toggle reset */
+#define USB0_ENDPTCTRL5_TXR_SHIFT (22)
+#define USB0_ENDPTCTRL5_TXR (1 << USB0_ENDPTCTRL5_TXR_SHIFT)
+
+/* TXE: Tx endpoint enable */
+#define USB0_ENDPTCTRL5_TXE_SHIFT (23)
+#define USB0_ENDPTCTRL5_TXE (1 << USB0_ENDPTCTRL5_TXE_SHIFT)
+
+/* -------------------------------------------------------------- */
+
+
+/* --- USB0_ENDPTCTRL common values ----------------------------- */
+
+/* RXS: Rx endpoint stall */
+#define USB0_ENDPTCTRL_RXS_SHIFT (0)
+#define USB0_ENDPTCTRL_RXS (1 << USB0_ENDPTCTRL_RXS_SHIFT)
+
+/* RXT: Endpoint type */
+#define USB0_ENDPTCTRL_RXT_SHIFT (2)
+#define USB0_ENDPTCTRL_RXT_MASK (0x3 << USB0_ENDPTCTRL_RXT_SHIFT)
+#define USB0_ENDPTCTRL_RXT(x) ((x) << USB0_ENDPTCTRL_RXT_SHIFT)
+
+/* RXI: Rx data toggle inhibit */
+#define USB0_ENDPTCTRL_RXI_SHIFT (5)
+#define USB0_ENDPTCTRL_RXI (1 << USB0_ENDPTCTRL_RXI_SHIFT)
+
+/* RXR: Rx data toggle reset */
+#define USB0_ENDPTCTRL_RXR_SHIFT (6)
+#define USB0_ENDPTCTRL_RXR (1 << USB0_ENDPTCTRL_RXR_SHIFT)
+
+/* RXE: Rx endpoint enable */
+#define USB0_ENDPTCTRL_RXE_SHIFT (7)
+#define USB0_ENDPTCTRL_RXE (1 << USB0_ENDPTCTRL_RXE_SHIFT)
+
+/* TXS: Tx endpoint stall */
+#define USB0_ENDPTCTRL_TXS_SHIFT (16)
+#define USB0_ENDPTCTRL_TXS (1 << USB0_ENDPTCTRL_TXS_SHIFT)
+
+/* TXT1_0: Tx Endpoint type */
+#define USB0_ENDPTCTRL_TXT1_0_SHIFT (18)
+#define USB0_ENDPTCTRL_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL_TXT1_0_SHIFT)
+#define USB0_ENDPTCTRL_TXT1_0(x) ((x) << USB0_ENDPTCTRL_TXT1_0_SHIFT)
+
+/* TXI: Tx data toggle inhibit */
+#define USB0_ENDPTCTRL_TXI_SHIFT (21)
+#define USB0_ENDPTCTRL_TXI (1 << USB0_ENDPTCTRL_TXI_SHIFT)
+
+/* TXR: Tx data toggle reset */
+#define USB0_ENDPTCTRL_TXR_SHIFT (22)
+#define USB0_ENDPTCTRL_TXR (1 << USB0_ENDPTCTRL_TXR_SHIFT)
+
+/* TXE: Tx endpoint enable */
+#define USB0_ENDPTCTRL_TXE_SHIFT (23)
+#define USB0_ENDPTCTRL_TXE (1 << USB0_ENDPTCTRL_TXE_SHIFT)
+
+
+
+
+
+/* --- USB1 registers ------------------------------------------------------ */
+/* TODO */
+
+#endif
diff --git a/libopencm3/include/libopencm3/lpc43xx/wwdt.h b/libopencm3/include/libopencm3/lpc43xx/wwdt.h
new file mode 100644
index 0000000..30ff6a7
--- /dev/null
+++ b/libopencm3/include/libopencm3/lpc43xx/wwdt.h
@@ -0,0 +1,65 @@
+/** @defgroup wwdt_defines Windowed Watchdog Timer
+
+@brief Defined Constants and Types for the LPC43xx Windowed Watchdog
+Timer
+
+@ingroup LPC43xx_defines
+
+@version 1.0.0
+
+@author @htmlonly © @endhtmlonly 2012 Michael Ossmann
+
+@date 10 March 2013
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Michael Ossmann
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef LPC43XX_WWDT_H
+#define LPC43XX_WWDT_H
+
+/**@{*/
+
+#include
+#include
+
+/* --- Windowed Watchdog Timer (WWDT) registers ---------------------------- */
+
+/* Watchdog mode register */
+#define WWDT_MOD MMIO32(WWDT_BASE + 0x000)
+
+/* Watchdog timer constant register */
+#define WWDT_TC MMIO32(WWDT_BASE + 0x004)
+
+/* Watchdog feed sequence register */
+#define WWDT_FEED MMIO32(WWDT_BASE + 0x008)
+
+/* Watchdog timer value register */
+#define WWDT_TV MMIO32(WWDT_BASE + 0x00C)
+
+/* Watchdog warning interrupt register */
+#define WWDT_WARNINT MMIO32(WWDT_BASE + 0x014)
+
+/* Watchdog timer window register */
+#define WWDT_WINDOW MMIO32(WWDT_BASE + 0x018)
+
+/**@}*/
+
+#endif
diff --git a/libopencm3/include/libopencm3/sam/3a/irq.json b/libopencm3/include/libopencm3/sam/3a/irq.json
new file mode 100644
index 0000000..c3d8c10
--- /dev/null
+++ b/libopencm3/include/libopencm3/sam/3a/irq.json
@@ -0,0 +1,52 @@
+{
+ "irqs": [
+ "supc",
+ "rstc",
+ "rtc",
+ "rtt",
+ "wdt",
+ "pmc",
+ "eefc0",
+ "eefc1",
+ "uart",
+ "smc_sdramc",
+ "sdramc",
+ "pioa",
+ "piob",
+ "pioc",
+ "piod",
+ "pioe",
+ "piof",
+ "usart0",
+ "usart1",
+ "usart2",
+ "usart3",
+ "hsmci",
+ "twi0",
+ "twi1",
+ "spi0",
+ "spi1",
+ "ssc",
+ "tc0",
+ "tc1",
+ "tc2",
+ "tc3",
+ "tc4",
+ "tc5",
+ "tc6",
+ "tc7",
+ "tc8",
+ "pwm",
+ "adc",
+ "dacc",
+ "dmac",
+ "uotghs",
+ "trng",
+ "reserved0",
+ "can0",
+ "can1"
+ ],
+ "partname_humanreadable": "Atmel SAM3A series",
+ "partname_doxygen": "SAM3A",
+ "includeguard": "LIBOPENCM3_SAM3A_NVIC_H"
+}
\ No newline at end of file
diff --git a/libopencm3/include/libopencm3/sam/3a/memorymap.h b/libopencm3/include/libopencm3/sam/3a/memorymap.h
new file mode 100644
index 0000000..90d97c6
--- /dev/null
+++ b/libopencm3/include/libopencm3/sam/3a/memorymap.h
@@ -0,0 +1,77 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Gareth McMullin
+ * Copyright (C) 2014 Felix Held
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef SAM3A_MEMORYMAP_H
+#define SAM3A_MEMORYMAP_H
+
+#include
+
+/* --- SAM3A peripheral space -------------------------------------------- */
+#define HSMCI_BASE (0x40000000U)
+#define SSC_BASE (0x40004000U)
+#define SPI0_BASE (0x40008000U)
+#define SPI1_BASE (0x4000C000U)
+#define TC0_BASE (0x40080000U)
+#define TC1_BASE (0x40080040U)
+#define TC2_BASE (0x40080080U)
+#define TC3_BASE (0x40084000U)
+#define TC4_BASE (0x40084040U)
+#define TC5_BASE (0x40084080U)
+#define TC6_BASE (0x40088000U)
+#define TC7_BASE (0x40088040U)
+#define TC8_BASE (0x40088080U)
+#define TWI0_BASE (0x4008C000U)
+#define TWI1_BASE (0x40090000U)
+#define PWM_BASE (0x40094000U)
+#define USART0_BASE (0x40098000U)
+#define USART1_BASE (0x4009C000U)
+#define USART2_BASE (0x400A0000U)
+#define USART3_BASE (0x400A4000U)
+#define UOTGHS_BASE (0x400AC000U)
+#define CAN0_BASE (0x400B4000U)
+#define CAN1_BASE (0x400B8000U)
+#define TRNG_BASE (0x400BC000U)
+#define ADC_BASE (0x400C0000U)
+#define DMAC_BASE (0x400C4000U)
+#define DACC_BASE (0x400C8000U)
+
+/* --- SAM3A system controller space ------------------------------------- */
+#define SMC_BASE (0x400E0000U)
+#define SDRAM_BASE (0x400E0200U)
+#define MATRIX_BASE (0x400E0400U)
+#define PMC_BASE (0x400E0600U)
+#define UART_BASE (0x400E0800U)
+#define CHIPID_BASE (0x400E0940U)
+#define EEFC0_BASE (0x400E0A00U)
+#define EEFC1_BASE (0x400E0C00U)
+#define PIOA_BASE (0x400E0E00U)
+#define PIOB_BASE (0x400E1000U)
+#define PIOC_BASE (0x400E1200U)
+#define PIOD_BASE (0x400E1400U)
+#define PIOE_BASE (0x400E1600U)
+#define PIOF_BASE (0x400E1800U)
+#define RSTC_BASE (0x400E1A00U)
+#define SUPC_BASE (0x400E1A10U)
+#define RTT_BASE (0x400E1A30U)
+#define WDT_BASE (0x400E1A50U)
+#define RTC_BASE (0x400E1A60U)
+#define GPBR_BASE (0x400E1A90U)
+
+#endif
diff --git a/libopencm3/include/libopencm3/sam/3n/irq.json b/libopencm3/include/libopencm3/sam/3n/irq.json
new file mode 100644
index 0000000..9d1d39e
--- /dev/null
+++ b/libopencm3/include/libopencm3/sam/3n/irq.json
@@ -0,0 +1,39 @@
+{
+ "irqs": [
+ "supc",
+ "rstc",
+ "rtc",
+ "rtt",
+ "wdt",
+ "pmc",
+ "eefc",
+ "reserved0",
+ "uart0",
+ "uart1",
+ "reserved1",
+ "pioa",
+ "piob",
+ "pioc",
+ "usart0",
+ "usart1",
+ "reserved2",
+ "reserved3",
+ "reserved4",
+ "twi0",
+ "twi1",
+ "spi",
+ "reserved5",
+ "tc0",
+ "tc1",
+ "tc2",
+ "tc3",
+ "tc4",
+ "tc5",
+ "adc",
+ "dacc",
+ "pwm"
+ ],
+ "partname_humanreadable": "Atmel SAM3N series",
+ "partname_doxygen": "SAM3N",
+ "includeguard": "LIBOPENCM3_SAM3N_NVIC_H"
+}
\ No newline at end of file
diff --git a/libopencm3/include/libopencm3/sam/3n/memorymap.h b/libopencm3/include/libopencm3/sam/3n/memorymap.h
new file mode 100644
index 0000000..34c193f
--- /dev/null
+++ b/libopencm3/include/libopencm3/sam/3n/memorymap.h
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Gareth McMullin
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef SAM3N_MEMORYMAP_H
+#define SAM3N_MEMORYMAP_H
+
+#include
+
+/* --- SAM3N peripheral space -------------------------------------------- */
+
+#define SPI_BASE (0x40008000U)
+#define TC0_BASE (0x40010000U)
+#define TC1_BASE (0x40010040U)
+#define TC2_BASE (0x40010080U)
+#define TC3_BASE (0x40014000U)
+#define TC4_BASE (0x40014040U)
+#define TC5_BASE (0x40014080U)
+#define TWI0_BASE (0x40018000U)
+#define TWI1_BASE (0x4001C000U)
+#define PWM_BASE (0x40020000U)
+#define USART0_BASE (0x40024000U)
+#define USART1_BASE (0x40028000U)
+#define ADC_BASE (0x40038000U)
+#define DACC_BASE (0x4003C000U)
+
+/* --- SAM3N system controller space ------------------------------------- */
+#define SMC_BASE (0x400E0000U)
+#define MATRIX_BASE (0x400E0200U)
+#define PMC_BASE (0x400E0400U)
+#define UART0_BASE (0x400E0600U)
+#define CHIPID_BASE (0x400E0740U)
+#define UART1_BASE (0x400E0800U)
+#define EEFC_BASE (0x400E0A00U)
+#define PIOA_BASE (0x400E0E00U)
+#define PIOB_BASE (0x400E1000U)
+#define PIOC_BASE (0x400E1200U)
+#define RSTC_BASE (0x400E1400U)
+#define SUPC_BASE (0x400E1410U)
+#define RTT_BASE (0x400E1430U)
+#define WDT_BASE (0x400E1450U)
+#define RTC_BASE (0x400E1460U)
+#define GPBR_BASE (0x400E1490U)
+
+#endif
diff --git a/libopencm3/include/libopencm3/sam/3s/irq.json b/libopencm3/include/libopencm3/sam/3s/irq.json
new file mode 100644
index 0000000..ddf76f6
--- /dev/null
+++ b/libopencm3/include/libopencm3/sam/3s/irq.json
@@ -0,0 +1,42 @@
+{
+ "irqs": [
+ "supc",
+ "rstc",
+ "rtc",
+ "rtt",
+ "wdt",
+ "pmc",
+ "eefc",
+ "reserved0",
+ "uart0",
+ "uart1",
+ "smc",
+ "pioa",
+ "piob",
+ "pioc",
+ "usart0",
+ "usart1",
+ "usart2",
+ "reserved1",
+ "hsmci",
+ "twi0",
+ "twi1",
+ "spi",
+ "ssc",
+ "tc0",
+ "tc1",
+ "tc2",
+ "tc3",
+ "tc4",
+ "tc5",
+ "adc",
+ "dacc",
+ "pwm",
+ "crccu",
+ "acc",
+ "udp"
+ ],
+ "partname_humanreadable": "Atmel SAM3S series",
+ "partname_doxygen": "SAM3S",
+ "includeguard": "LIBOPENCM3_SAM3S_NVIC_H"
+}
\ No newline at end of file
diff --git a/libopencm3/include/libopencm3/sam/3s/memorymap.h b/libopencm3/include/libopencm3/sam/3s/memorymap.h
new file mode 100644
index 0000000..0ce7200
--- /dev/null
+++ b/libopencm3/include/libopencm3/sam/3s/memorymap.h
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Gareth McMullin
+ * Copyright (C) 2014 Felix Held
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef SAM3S_MEMORYMAP_H
+#define SAM3S_MEMORYMAP_H
+
+#include
+
+/* --- SAM3S peripheral space -------------------------------------------- */
+#define HSMCI_BASE (0x40000000U)
+#define SSC_BASE (0x40004000U)
+#define SPI_BASE (0x40008000U)
+#define TC0_BASE (0x40010000U)
+#define TC1_BASE (0x40010040U)
+#define TC2_BASE (0x40010080U)
+#define TC3_BASE (0x40014000U)
+#define TC4_BASE (0x40014040U)
+#define TC5_BASE (0x40014080U)
+#define TWI0_BASE (0x40018000U)
+#define TWI1_BASE (0x4001C000U)
+#define PWM_BASE (0x40020000U)
+#define USART0_BASE (0x40024000U)
+#define USART1_BASE (0x40028000U)
+#define USART2_BASE (0x4002C000U)
+#define UDP_BASE (0x40034000U)
+#define ADC_BASE (0x40038000U)
+#define DACC_BASE (0x4003C000U)
+#define ACC_BASE (0x40040000U)
+#define CRCCU_BASE (0x40044000U)
+
+/* --- SAM3S system controller space ------------------------------------- */
+#define SMC_BASE (0x400E0000U)
+#define MATRIX_BASE (0x400E0200U)
+#define PMC_BASE (0x400E0400U)
+#define UART0_BASE (0x400E0600U)
+#define CHIPID_BASE (0x400E0740U)
+#define UART1_BASE (0x400E0800U)
+#define EEFC_BASE (0x400E0A00U)
+#define PIOA_BASE (0x400E0E00U)
+#define PIOB_BASE (0x400E1000U)
+#define PIOC_BASE (0x400E1200U)
+#define RSTC_BASE (0x400E1400U)
+#define SUPC_BASE (0x400E1410U)
+#define RTT_BASE (0x400E1430U)
+#define WDT_BASE (0x400E1450U)
+#define RTC_BASE (0x400E1460U)
+#define GPBR_BASE (0x400E1490U)
+
+#endif
diff --git a/libopencm3/include/libopencm3/sam/3u/irq.json b/libopencm3/include/libopencm3/sam/3u/irq.json
new file mode 100644
index 0000000..c52f183
--- /dev/null
+++ b/libopencm3/include/libopencm3/sam/3u/irq.json
@@ -0,0 +1,37 @@
+{
+ "irqs": [
+ "supc",
+ "rstc",
+ "rtc",
+ "rtt",
+ "wdt",
+ "pmc",
+ "eefc0",
+ "eefc1",
+ "uart",
+ "smc",
+ "pioa",
+ "piob",
+ "pioc",
+ "usart0",
+ "usart1",
+ "usart2",
+ "usart3",
+ "hsmci",
+ "twi0",
+ "twi1",
+ "spi",
+ "ssc",
+ "tc0",
+ "tc1",
+ "tc2",
+ "pwm",
+ "adc12b",
+ "adc",
+ "dmac",
+ "udphs"
+ ],
+ "partname_humanreadable": "Atmel SAM3U series",
+ "partname_doxygen": "SAM3U",
+ "includeguard": "LIBOPENCM3_SAM3U_NVIC_H"
+}
\ No newline at end of file
diff --git a/libopencm3/include/libopencm3/sam/3u/memorymap.h b/libopencm3/include/libopencm3/sam/3u/memorymap.h
new file mode 100644
index 0000000..edd2f29
--- /dev/null
+++ b/libopencm3/include/libopencm3/sam/3u/memorymap.h
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Gareth McMullin
+ * Copyright (C) 2014 Felix Held
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef SAM3U_MEMORYMAP_H
+#define SAM3U_MEMORYMAP_H
+
+#include
+
+/* --- SAM3U peripheral space -------------------------------------------- */
+#define HSMCI_BASE (0x40000000U)
+#define SSC_BASE (0x40004000U)
+#define SPI_BASE (0x40008000U)
+#define TC0_BASE (0x40080000U)
+#define TC1_BASE (0x40080040U)
+#define TC2_BASE (0x40080080U)
+#define TWI0_BASE (0x40084000U)
+#define TWI1_BASE (0x40088000U)
+#define PWM_BASE (0x4008C000U)
+#define USART0_BASE (0x40090000U)
+#define USART1_BASE (0x40094000U)
+#define USART2_BASE (0x40098000U)
+#define USART3_BASE (0x4009C000U)
+#define UDPHS_BASE (0x400A4000U)
+#define ADC12B_BASE (0x400A8000U)
+#define ADC_BASE (0x400AC000U)
+#define DMAC_BASE (0x400B0000U)
+
+/* --- SAM3U system controller space ------------------------------------- */
+#define SMC_BASE (0x400E0000U)
+#define MATRIX_BASE (0x400E0200U)
+#define PMC_BASE (0x400E0400U)
+#define UART_BASE (0x400E0600U)
+#define CHIPID_BASE (0x400E0740U)
+#define EEFC0_BASE (0x400E0800U)
+#define EEFC1_BASE (0x400E0A00U)
+#define PIOA_BASE (0x400E0C00U)
+#define PIOB_BASE (0x400E0E00U)
+#define PIOC_BASE (0x400E1000U)
+#define RSTC_BASE (0x400E1200U)
+#define SUPC_BASE (0x400E1210U)
+#define RTT_BASE (0x400E1230U)
+#define WDT_BASE (0x400E1250U)
+#define RTC_BASE (0x400E1260U)
+#define GPBR_BASE (0x400E1290U)
+
+#endif
diff --git a/libopencm3/include/libopencm3/sam/3x/irq.json b/libopencm3/include/libopencm3/sam/3x/irq.json
new file mode 100644
index 0000000..c53d63c
--- /dev/null
+++ b/libopencm3/include/libopencm3/sam/3x/irq.json
@@ -0,0 +1,52 @@
+{
+ "irqs": [
+ "supc",
+ "rstc",
+ "rtc",
+ "rtt",
+ "wdt",
+ "pmc",
+ "eefc0",
+ "eefc1",
+ "uart",
+ "smc_sdramc",
+ "sdramc",
+ "pioa",
+ "piob",
+ "pioc",
+ "piod",
+ "pioe",
+ "piof",
+ "usart0",
+ "usart1",
+ "usart2",
+ "usart3",
+ "hsmci",
+ "twi0",
+ "twi1",
+ "spi0",
+ "spi1",
+ "ssc",
+ "tc0",
+ "tc1",
+ "tc2",
+ "tc3",
+ "tc4",
+ "tc5",
+ "tc6",
+ "tc7",
+ "tc8",
+ "pwm",
+ "adc",
+ "dacc",
+ "dmac",
+ "uotghs",
+ "trng",
+ "emac",
+ "can0",
+ "can1"
+ ],
+ "partname_humanreadable": "Atmel SAM3X series",
+ "partname_doxygen": "SAM3X",
+ "includeguard": "LIBOPENCM3_SAM3X_NVIC_H"
+}
\ No newline at end of file
diff --git a/libopencm3/include/libopencm3/sam/3x/memorymap.h b/libopencm3/include/libopencm3/sam/3x/memorymap.h
new file mode 100644
index 0000000..dea04bb
--- /dev/null
+++ b/libopencm3/include/libopencm3/sam/3x/memorymap.h
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Gareth McMullin
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef SAM3X_MEMORYMAP_H
+#define SAM3X_MEMORYMAP_H
+
+#include
+
+/* --- SAM3X peripheral space -------------------------------------------- */
+
+#define HSMCI_BASE (0x40000000U)
+#define SSC_BASE (0x40004000U)
+#define SPI0_BASE (0x40008000U)
+#define SPI1_BASE (0x4000C000U)
+#define TC0_BASE (0x40080000U)
+#define TC1_BASE (0x40080040U)
+#define TC2_BASE (0x40080080U)
+#define TC3_BASE (0x40084000U)
+#define TC4_BASE (0x40084040U)
+#define TC5_BASE (0x40084080U)
+#define TC6_BASE (0x40088000U)
+#define TC7_BASE (0x40088040U)
+#define TC8_BASE (0x40088080U)
+#define TWI0_BASE (0x4008C000U)
+#define TWI1_BASE (0x40090000U)
+#define PWM_BASE (0x40094000U)
+#define USART0_BASE (0x40098000U)
+#define USART1_BASE (0x4009C000U)
+#define USART2_BASE (0x400A0000U)
+#define USART3_BASE (0x400A4000U)
+#define UOTGHS_BASE (0x400AC000U)
+#define EMAC_BASE (0x400B0000U)
+#define CAN0_BASE (0x400B4000U)
+#define CAN1_BASE (0x400B8000U)
+#define TRNG_BASE (0x400BC000U)
+#define ADC_BASE (0x400C0000U)
+#define DMAC_BASE (0x400C4000U)
+#define DACC_BASE (0x400C8000U)
+
+/* --- SAM3X system controller space ------------------------------------- */
+#define SMC_BASE (0x400E0000U)
+#define SDRAM_BASE (0x400E0200U)
+#define MATRIX_BASE (0x400E0400U)
+#define PMC_BASE (0x400E0600U)
+#define UART_BASE (0x400E0800U)
+#define CHIPID_BASE (0x400E0940U)
+#define EEFC0_BASE (0x400E0A00U)
+#define EEFC1_BASE (0x400E0C00U)
+#define PIOA_BASE (0x400E0E00U)
+#define PIOB_BASE (0x400E1000U)
+#define PIOC_BASE (0x400E1200U)
+#define PIOD_BASE (0x400E1400U)
+#define PIOE_BASE (0x400E1600U)
+#define PIOF_BASE (0x400E1800U)
+#define RSTC_BASE (0x400E1A00U)
+#define SUPC_BASE (0x400E1A10U)
+#define RTT_BASE (0x400E1A30U)
+#define WDT_BASE (0x400E1A50U)
+#define RTC_BASE (0x400E1A60U)
+#define GPBR_BASE (0x400E1A90U)
+
+#endif
diff --git a/libopencm3/include/libopencm3/sam/eefc.h b/libopencm3/include/libopencm3/sam/eefc.h
new file mode 100644
index 0000000..eb6d4d0
--- /dev/null
+++ b/libopencm3/include/libopencm3/sam/eefc.h
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2013 Gareth McMullin
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library. If not, see .
+ */
+
+#ifndef SAM3X_EEFC_H
+#define SAM3X_EEFC_H
+
+#include
+#include
+
+/* --- Convenience macros ------------------------------------------------ */
+#define EEFC EEFC_BASE
+#define EEFC0 EEFC0_BASE
+#define EEFC1 EEFC1_BASE
+
+/* --- Enhanced Embedded Flash Controller (EEFC) registers --------------- */
+#define EEFC_FMR(port) MMIO32((port) + 0x00)
+#define EEFC_FCR(port) MMIO32((port) + 0x04)
+#define EEFC_FSR(port) MMIO32((port) + 0x08)
+#define EEFC_FRR(port) MMIO32((port) + 0x0C)
+/* 0x0010 - Reserved */
+
+
+/* EEFC Flash Mode Register (EEFC_FMR) */
+/* Bit [31:25] - Reserved */
+#define EEFC_FMR_FAM (0x01 << 24)
+/* Bit [23:12] - Reserved */
+#define EEFC_FMR_FWS_MASK (0x0F << 8)
+/* Bit [7:1] - Reserved */
+#define EEFC_FMR_FRDY (0x01 << 0)
+
+/* EEFC Flash Command Register (EEFC_FCR) */
+#define EEFC_FCR_FKEY (0x5A << 24)
+#define EEFC_FCR_FARG_MASK (0xFFFF << 8)
+#define EEFC_FCR_FCMD_MASK (0xFF << 0)
+#define EEFC_FCR_FCMD_GETD (0x00 << 0)
+#define EEFC_FCR_FCMD_WP (0x01 << 0)
+#define EEFC_FCR_FCMD_WPL (0x02 << 0)
+#define EEFC_FCR_FCMD_EWP (0x03 << 0)
+#define EEFC_FCR_FCMD_EWPL (0x04 << 0)
+#define EEFC_FCR_FCMD_EA (0x05 << 0)
+#define EEFC_FCR_FCMD_SLB (0x08 << 0)
+#define EEFC_FCR_FCMD_CLB (0x09 << 0)
+#define EEFC_FCR_FCMD_GLB (0x0A << 0)
+#define EEFC_FCR_FCMD_SGPB (0x0B << 0)
+#define EEFC_FCR_FCMD_CGPB (0x0C << 0)
+#define EEFC_FCR_FCMD_GGPB (0x0D << 0)
+#define EEFC_FCR_FCMD_STUI (0x0E << 0)
+#define EEFC_FCR_FCMD_SPUI (0x0F << 0)
+
+/* EEFC Flash Status Register (EEFC_FSR) */
+/* Bit [31:3] - Reserved */
+#define EEFC_FSR_FLOCKE (0x01 << 2)
+#define EEFC_FSR_FCMDE (0x01 << 1)
+#define EEFC_FSR_FRDY (0x01 << 0)
+
+static inline void eefc_set_latency(uint8_t wait)
+{
+#if defined(SAM3A) || defined(SAM3U) || defined(SAM3X)
+ EEFC_FMR(EEFC0) = (EEFC_FMR(EEFC0) & ~EEFC_FMR_FWS_MASK) | (wait << 8);
+ EEFC_FMR(EEFC1) = (EEFC_FMR(EEFC1) & ~EEFC_FMR_FWS_MASK) | (wait << 8);
+#elif defined(SAM3N) || defined(SAM3S)
+ EEFC_FMR(EEFC) = (EEFC_FMR(EEFC) & ~EEFC_FMR_FWS_MASK) | (wait << 8);
+#endif
+}
+
+#endif
+
diff --git a/libopencm3/include/libopencm3/sam/gpio.h b/libopencm3/include/libopencm3/sam/gpio.h
new file mode 100644
index 0000000..20fd9ad
--- /dev/null
+++ b/libopencm3/include/libopencm3/sam/gpio.h
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2013 Gareth McMullin