From 1dc7d758f96dd2b9bd7b03f01ca032d68b696cf0 Mon Sep 17 00:00:00 2001
From: root <root@lab2.panaceas.james.local>
Date: Sun, 2 Nov 2014 10:14:39 +0000
Subject: fish

---
 libopencm3/scripts/data/lpc43xx/ritimer.yaml | 51 ++++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)
 create mode 100644 libopencm3/scripts/data/lpc43xx/ritimer.yaml

(limited to 'libopencm3/scripts/data/lpc43xx/ritimer.yaml')

diff --git a/libopencm3/scripts/data/lpc43xx/ritimer.yaml b/libopencm3/scripts/data/lpc43xx/ritimer.yaml
new file mode 100644
index 0000000..9c4da5c
--- /dev/null
+++ b/libopencm3/scripts/data/lpc43xx/ritimer.yaml
@@ -0,0 +1,51 @@
+!!omap
+- RITIMER_COMPVAL:
+    fields: !!omap
+    - RICOMP:
+        access: rw
+        description: Compare register
+        lsb: 0
+        reset_value: '0xFFFFFFFF'
+        width: 32
+- RITIMER_MASK:
+    fields: !!omap
+    - RIMASK:
+        access: rw
+        description: Mask register
+        lsb: 0
+        reset_value: '0'
+        width: 32
+- RITIMER_CTRL:
+    fields: !!omap
+    - RITINT:
+        access: rw
+        description: Interrupt flag
+        lsb: 0
+        reset_value: '0'
+        width: 1
+    - RITENCLR:
+        access: rw
+        description: Timer enable clear
+        lsb: 1
+        reset_value: '0'
+        width: 1
+    - RITENBR:
+        access: rw
+        description: Timer enable for debug
+        lsb: 2
+        reset_value: '1'
+        width: 1
+    - RITEN:
+        access: rw
+        description: Timer enable
+        lsb: 3
+        reset_value: '1'
+        width: 1
+- RITIMER_COUNTER:
+    fields: !!omap
+    - RICOUNTER:
+        access: rw
+        description: 32-bit up counter
+        lsb: 0
+        reset_value: '0'
+        width: 32
-- 
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