From 1dc7d758f96dd2b9bd7b03f01ca032d68b696cf0 Mon Sep 17 00:00:00 2001 From: root Date: Sun, 2 Nov 2014 10:14:39 +0000 Subject: fish --- libopencm3/include/libopencm3/stm32/l1/pwr.h | 111 +++++++++++++++++++++++++++ 1 file changed, 111 insertions(+) create mode 100644 libopencm3/include/libopencm3/stm32/l1/pwr.h (limited to 'libopencm3/include/libopencm3/stm32/l1/pwr.h') diff --git a/libopencm3/include/libopencm3/stm32/l1/pwr.h b/libopencm3/include/libopencm3/stm32/l1/pwr.h new file mode 100644 index 0000000..ddcdc07 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/l1/pwr.h @@ -0,0 +1,111 @@ +/** @defgroup pwr_defines PWR Defines + +@brief Defined Constants and Types for the STM32L1xx Power Control + +@ingroup STM32L1xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2011 Stephen Caudle +@author @htmlonly © @endhtmlonly 2012 Karl Palsson + +@date 1 July 2012 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Stephen Caudle + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_PWR_H +#define LIBOPENCM3_PWR_H + +#include + +/* + * This file extends the common STM32 version with definitions only + * applicable to the STM32L1 series of devices. + */ + +/* --- PWR_CR values ------------------------------------------------------- */ + +/* Bits [31:15]: Reserved */ + +/* LPRUN: Low power run mode */ +#define PWR_CR_LPRUN (1 << 14) + +/* VOS[12:11]: Regulator voltage scaling output selection */ +#define PWR_CR_VOS_LSB 11 +/** @defgroup pwr_vos Voltage Scaling Output level selection +@ingroup pwr_defines + +@{*/ +#define PWR_CR_VOS_RANGE1 (0x1 << PWR_CR_VOS_LSB) +#define PWR_CR_VOS_RANGE2 (0x2 << PWR_CR_VOS_LSB) +#define PWR_CR_VOS_RANGE3 (0x3 << PWR_CR_VOS_LSB) +/**@}*/ +#define PWR_CR_VOS_MASK (0x3 << PWR_CR_VOS_LSB) + +/* FWU: Fast wakeup */ +#define PWR_CR_FWU (1 << 10) + +/* ULP: Ultralow power mode */ +#define PWR_CR_ULP (1 << 9) + +/* LPSDSR: Low-power deepsleep/sleep/low power run */ +#define PWR_CR_LPSDSR (1 << 0) /* masks common PWR_CR_LPDS */ + +/* --- PWR_CSR values ------------------------------------------------------- */ + +/* Bits [31:11]: Reserved */ +/* EWUP3: Enable WKUP3 pin */ +#define PWR_CSR_EWUP3 (1 << 10) + +/* EWUP2: Enable WKUP2 pin */ +#define PWR_CSR_EWUP2 (1 << 9) + +/* EWUP1: Enable WKUP1 pin */ +#define PWR_CSR_EWUP1 PWR_CSR_EWUP + +/* REGLPF : Regulator LP flag */ +#define PWR_CSR_REGLPF (1 << 5) + +/* VOSF: Voltage Scaling select flag */ +#define PWR_CSR_VOSF (1 << 4) + +/* VREFINTRDYF: Internal voltage reference (VREFINT) ready flag */ +#define PWR_CSR_VREFINTRDYF (1 << 3) + + + +/* --- Function prototypes ------------------------------------------------- */ + +typedef enum { + RANGE1, + RANGE2, + RANGE3, +} vos_scale_t; + +BEGIN_DECLS + +void pwr_set_vos_scale(vos_scale_t scale); + +END_DECLS + +#endif -- cgit v1.2.3