From 849369d6c66d3054688672f97d31fceb8e8230fb Mon Sep 17 00:00:00 2001 From: root Date: Fri, 25 Dec 2015 04:40:36 +0000 Subject: initial_commit --- arch/arm/plat-orion/irq.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 arch/arm/plat-orion/irq.c (limited to 'arch/arm/plat-orion/irq.c') diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c new file mode 100644 index 00000000..2d5b9c1e --- /dev/null +++ b/arch/arm/plat-orion/irq.c @@ -0,0 +1,34 @@ +/* + * arch/arm/plat-orion/irq.c + * + * Marvell Orion SoC IRQ handling. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include + +void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) +{ + struct irq_chip_generic *gc; + struct irq_chip_type *ct; + + /* + * Mask all interrupts initially. + */ + writel(0, maskaddr); + + gc = irq_alloc_generic_chip("orion_irq", 1, irq_start, maskaddr, + handle_level_irq); + ct = gc->chip_types; + ct->chip.irq_mask = irq_gc_mask_clr_bit; + ct->chip.irq_unmask = irq_gc_mask_set_bit; + irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE, + IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); +} -- cgit v1.2.3