From 849369d6c66d3054688672f97d31fceb8e8230fb Mon Sep 17 00:00:00 2001 From: root Date: Fri, 25 Dec 2015 04:40:36 +0000 Subject: initial_commit --- arch/arm/mach-mx6/src-reg.h | 51 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 arch/arm/mach-mx6/src-reg.h (limited to 'arch/arm/mach-mx6/src-reg.h') diff --git a/arch/arm/mach-mx6/src-reg.h b/arch/arm/mach-mx6/src-reg.h new file mode 100644 index 00000000..dc13e431 --- /dev/null +++ b/arch/arm/mach-mx6/src-reg.h @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/* + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.30 + * Template revision: 1.3 + */ +#ifndef _SRC_REGISTER_HEADER_ +#define _SRC_REGISTER_HEADER_ + +#define SRC_SCR_OFFSET 0x000 +#define SRC_SBMR_OFFSET 0x004 +#define SRC_SRSR_OFFSET 0x008 +#define SRC_SAIAR_OFFSET 0x00c +#define SRC_SAIRAR_OFFSET 0x010 +#define SRC_SISR_OFFSET 0x014 +#define SRC_SIMR_OFFSET 0x018 +#define SRC_SBMR2_OFFSET 0x01c +#define SRC_GPR1_OFFSET 0x020 +#define SRC_GPR2_OFFSET 0x024 +#define SRC_GPR3_OFFSET 0x028 +#define SRC_GPR4_OFFSET 0x02c +#define SRC_GPR5_OFFSET 0x030 +#define SRC_GPR6_OFFSET 0x034 +#define SRC_GPR7_OFFSET 0x038 +#define SRC_GPR8_OFFSET 0x03c +#define SRC_GPR9_OFFSET 0x040 +#define SRC_GPR10_OFFSET 0x044 + +#define BP_SRC_SCR_CORE0_RST 13 +#define BP_SRC_SCR_CORES_DBG_RST 21 +#define BP_SRC_SCR_CORE1_ENABLE 22 + +#endif -- cgit v1.2.3