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path:
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/
tests
/
sim
/
dff.v
blob: ce792b59a0c4461d51202a836069c0bc206abb11 (
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)
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module
dff
(
input
d
,
clk
,
output
reg
q
);
always
@(
posedge
clk
)
q
<=
d
;
endmodule