/* * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf * Copyright (C) 2018 Clifford Wolf * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ #include "kernel/register.h" #include "kernel/celltypes.h" #include "kernel/rtlil.h" #include "kernel/log.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN struct SynthEcp5Pass : public ScriptPass { SynthEcp5Pass() : ScriptPass("synth_ecp5", "synthesis for ECP5 FPGAs") { } void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log(" synth_ecp5 [options]\n"); log("\n"); log("This command runs synthesis for ECP5 FPGAs.\n"); log("\n"); log(" -top \n"); log(" use the specified module as top module\n"); log("\n"); log(" -blif \n"); log(" write the design to the specified BLIF file. writing of an output file\n"); log(" is omitted if this parameter is not specified.\n"); log("\n"); log(" -edif \n"); log(" write the design to the specified EDIF file. writing of an output file\n"); log(" is omitted if this parameter is not specified.\n"); log("\n"); log(" -json \n"); log(" write the design to the specified JSON file. writing of an output file\n"); log(" is omitted if this parameter is not specified.\n"); log("\n"); log(" -run :\n"); log(" only run the commands between the labels (see below). an empty\n"); log(" from label is synonymous to 'begin', and empty to label is\n"); log(" synonymous to the end of the command list.\n"); log("\n"); log(" -noflatten\n"); log(" do not flatten design before synthesis\n"); log("\n"); log(" -retime\n"); log(" run 'abc' with -dff option\n"); log("\n"); log(" -noccu2\n"); log(" do not use CCU2 cells in output netlist\n"); log("\n"); log(" -nodffe\n"); log(" do not use flipflops with CE in output netlist\n"); log("\n"); log(" -nobram\n"); log(" do not use BRAM cells in output netlist\n"); log("\n"); log(" -nodram\n"); log(" do not use distributed RAM cells in output netlist\n"); log("\n"); log(" -nomux\n"); log(" do not use PFU muxes to implement LUTs larger than LUT4s\n"); log("\n"); log(" -abc2\n"); log(" run two passes of 'abc' for slightly improved logic density\n"); log("\n"); log(" -vpr\n"); log(" generate an output netlist (and BLIF file) suitable for VPR\n"); log(" (this feature is experimental and incomplete)\n"); log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); log("\n"); } string top_opt, blif_file, edif_file, json_file; bool noccu2, nodffe, nobram, nodram, nomux, flatten, retime, abc2, vpr; void clear_flags() YS_OVERRIDE { top_opt = "-auto-top"; blif_file = ""; edif_file = ""; json_file = ""; noccu2 = false; nodffe = false; nobram = false; nodram = fa

// test_simulation_nor_1_test.v
module f1_test(input [1:0] in, output out);
assign out = ~(in[0] | in[1]);
endmodule

// test_simulation_nor_2_test.v
module f2_test(input [2:0] in, output out);
assign out = ~(in[0] | in[1] | in[2]);
endmodule

// test_simulation_nor_3_test.v
module f3_test(input [3:0] in, output out);
assign out = ~(in[0] | in[1] | in[2] | in[3]);
endmodule

// test_simulation_nor_4_test.v
module f4_test(input [3:0] in, output out);
nor mynor(out, in[0], in[1], in[2], in[3]);
endmodule