-- PSL - NFA definition -- Copyright (C) 2002-2016 Tristan Gingold -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see . with Tables; with PSL.Types; use PSL.Types; package body PSL.NFAs is -- Record that describes an NFA. type NFA_Node is record -- Chain of States. First_State : NFA_State; Last_State : NFA_State; -- Start and final state. Start : NFA_State; Final : NFA_State; Active : NFA_State; -- If true there is an epsilon transition between the start and -- the final state. Epsilon : Boolean; end record; -- Record that describe a node. type NFA_State_Node is record -- States may be numbered. Label : Int32; -- Edges. First_Src : NFA_Edge; First_Dst : NFA_Edge; -- State links. Next_State : NFA_State; Prev_State : NFA_State; -- User fields. User_Link : NFA_State; User_Flag : Boolean; end record; -- Record that describe an edge between SRC and DEST. type NFA_Edge_Node is record Dest : NFA_State; Src : NFA_State; Expr : Node; -- Links. Next_Src : NFA_Edge; Next_Dst : NFA_Edge; end record; -- Table of NFA. package Nfat is new Tables (Table_Component_Type => NFA_Node, Table_Index_Type => NFA, Table_Low_Bound => 1, Table_Initial => 128); -- List of free nodes. Free_Nfas : NFA := No_NFA; -- Table of States. package Statet is new Tables (Table_Component_Type => NFA_State_Node, Table_Index_Type => NFA_State, Table_Low_Bound => 1, Table_Initial => 128); -- List of free states. Free_States : NFA_State := No_State; -- Table of edges. package Transt is new Tables (Table_Component_Type => NFA_Edge_Node, Table_Index_Type => NFA_Edge, Table_Low_Bound => 1, Table_Initial => 128); -- List of free edges. Free_Edges : NFA_Edge := No_Edge; function Get_First_State (N : NFA) return NFA_State is begin return Nfat.Table (N).First_State; end Get_First_State; function Get_Last_State (N : NFA) return NFA_State is begin return Nfat.Table (N).Last_State; end Get_Last_State; procedure Set_First_State (N : NFA; S : NFA_State) is begin Nfat.Table (N).First_State := S; end Set_First_State; procedure Set_Last_State (N : NFA; S : NFA_State) is begin Nfat.Table (N).Last_State := S; end Set_Last_State; function Get_Next_State (S : NFA_State) return NFA_State is begin return Statet.Table (S).Next_State; end Get_Next_State; procedure Set_Next_State (S : NFA_State; N : NFA_State) is begin Statet.Table (S).Next_State := N; end Set_Next_State; function Get_Prev_State (S : NFA_State) return NFA_State is begin return Statet.Table (S).Prev_State; end Get_Prev_State; procedure Set_Prev_State (S : NFA_State; N : NFA_State) is begin Statet.Table (S).Prev_State := N; end Set_Prev_State; function Get_State_Label (S : NFA_State) return Int32 is begin return Statet.Table (S).Label; end Get_State_Label; procedure Set_State_Label (S : NFA_State; Label : Int32) is begin Statet.Table (S).Label := Label; end Set_State_Label; function Get_Epsilon_NFA (N : NFA) return Boolean is begin return Nfat.Table (N).Epsilon; end Get_Epsilon_NFA; procedure Set_Epsilon_NFA (N : NFA; Flag : Boolean) is begin Nfat.Table (N).Epsilon := Flag; end Set_Epsilon_NFA; function Add_State (N : NFA) return NFA_State is Res : NFA_State; Last : NFA_State; begin -- Get a new state. if Free_States = No_State then Statet.Increment_Last; Res := Statet.Last; else Res := Free_States; Free_States := Get_Next_State (Res); end if; -- Put it in N. Last := Get_Last_State (N); Statet.Table (Res) := (Label => 0, First_Src => No_Edge, First_Dst => No_Edge, Next_State => No_State, Prev_State => Last, User_Link => No_State, User_Flag => False); if Last = No_State then Nfat.Table (N).First_State := Res; else Statet.Table (Last).Next_State := Res; end if; Nfat.Table (N).Last_State := Res; return Res; end Add_State; procedure Delete_Detached_State (S : NFA_State) is begin -- Put it in front of the free_states list. Set_Next_State (S, Free_States); Free_States := S; end Delete_Detached_State; function Create_NFA return NFA is Res : NFA; begin -- Allocate a node. if Free_Nfas = No_NFA then Nfat.Increment_Last; Res := Nfat.Last; else Res := Free_Nfas; Free_Nfas := NFA (Get_First_State (Res)); end if; -- Fill it. Nfat.Table (Res) := (First_State => No_State, Last_State => No_State, Start | Final | Active => No_State, Epsilon => False); return Res; end Create_NFA; procedure Set_First_Src_Edge (N : NFA_State; T : NFA_Edge) is begin Statet.Table (N).First_Src := T; end Set_First_Src_Edge; function Get_First_Src_Edge (N : NFA_State) return NFA_Edge is begin return Statet.Table (N).First_Src; end Get_First_Src_Edge; procedure Set_First_Dest_Edge (N : NFA_State; T : NFA_Edge) is begin Statet.Table (N).First_Dst := T; end Set_First_Dest_Edge; function Get_First_Dest_Edge (N : NFA_State) return NFA_Edge is begin return Statet.Table (N).First_Dst; end Get_First_Dest_Edge; function Get_State_Flag (S : NFA_State) return Boolean is begin return Statet.Table (S).User_Flag; end Get_State_Flag; procedure Set_State_Flag (S : NFA_State; Val : Boolean) is begin Statet.Table (S).User_Flag := Val; end Set_State_Flag; function Get_State_User_Link (S : NFA_State) return NFA_State is begin return Statet.Table (S).User_Link; end Get_State_User_Link; procedure Set_State_User_Link (S : NFA_State; Link : NFA_State) is begin Statet.Table (S).User_Link := Link; end Set_State_User_Link; function Add_Edge (Src : NFA_State; Dest : NFA_State; Expr : Node) return NFA_Edge is Res : NFA_Edge; begin -- Allocate a note. if Free_Edges /= No_Edge then Res := Free_Edges; Free_Edges := Get_Next_Dest_Edge (Res); else Transt.Increment_Last; Res := Transt.Last; end if; -- Initialize it. Transt.Table (Res) := (Dest => Dest, Src => Src, Expr => Expr, Next_Src => Get_First_Src_Edge (Src), Next_Dst => Get_First_Dest_Edge (Dest)); Set_First_Src_Edge (Src, Res); Set_First_Dest_Edge (Dest, Res); return Res; end Add_Edge; procedure Add_Edge (Src : NFA_State; Dest : NFA_State; Expr : Node) is Res : NFA_Edge; pragma Unreferenced (Res); begin Res := Add_Edge (Src, Dest, Expr); end Add_Edge; procedure Delete_Empty_NFA (N : NFA) is begin pragma Assert (Get_First_State (N) = No_State); pragma Assert (Get_Last_State (N) = No_State); -- Put it in front of the free_nfas list. Set_First_State (N, NFA_State (Free_Nfas)); Free_Nfas := N; end Delete_Empty_NFA; function Get_Start_State (N : NFA) return NFA_State is begin return Nfat.Table (N).Start; end Get_Start_State; procedure Set_Start_State (N : NFA; S : NFA_State) is begin Nfat.Table (N).Start := S; end Set_Start_State; function Get_Final_State (N : NFA) return NFA_State is begin return Nfat.Table (N).Final; end Get_Final_State; procedure Set_Final_State (N : NFA; S : NFA_State) is begin Nfat.Table (N).Final := S; end Set_Final_State; function Get_Active_State (N : NFA) return NFA_State is begin return Nfat.Table (N).Active; end Get_Active_State; procedure Set_Active_State (N : NFA; S : NFA_State) is begin Nfat.Table (N).Active := S; end Set_Active_State; function Get_Next_Src_Edge (N : NFA_Edge) return NFA_Edge is begin return Transt.Table (N).Next_Src; end Get_Next_Src_Edge; procedure Set_Next_Src_Edge (E : NFA_Edge; N_E : NFA_Edge) is begin Transt.Table (E).Next_Src := N_E; end Set_Next_Src_Edge; function Get_Next_Dest_Edge (N : NFA_Edge) return NFA_Edge is begin return Transt.Table (N).Next_Dst; end Get_Next_Dest_Edge; procedure Set_Next_Dest_Edge (E : NFA_Edge; N_E : NFA_Edge) is begin Transt.Table (E).Next_Dst := N_E; end Set_Next_Dest_Edge; function Get_Edge_Dest (E : NFA_Edge) return NFA_State is begin return Transt.Table (E).Dest; end Get_Edge_Dest; procedure Set_Edge_Dest (E : NFA_Edge; D : NFA_State) is begin Transt.Table (E).Dest := D; end Set_Edge_Dest; function Get_Edge_Src (E : NFA_Edge) return NFA_State is begin return Transt.Table (E).Src; end Get_Edge_Src; procedure Set_Edge_Src (E : NFA_Edge; D : NFA_State) is begin Transt.Table (E).Src := D; end Set_Edge_Src; function Get_Edge_Expr (E : NFA_Edge) return Node is begin return Transt.Table (E).Expr; end Get_Edge_Expr; procedure Set_Edge_Expr (E : NFA_Edge; N : Node) is begin Transt.Table (E).Expr := N; end Set_Edge_Expr; procedure Remove_Unconnected_State (N : NFA; S : NFA_State) is N_S : constant NFA_State := Get_Next_State (S); P_S : constant NFA_State := Get_Prev_State (S); begin pragma Assert (Get_First_Src_Edge (S) = No_Edge); pragma Assert (Get_First_Dest_Edge (S) = No_Edge); if P_S = No_State then Set_First_State (N, N_S); else Set_Next_State (P_S, N_S); end if; if N_S = No_State then Set_Last_State (N, P_S); else Set_Prev_State (N_S, P_S); end if; Delete_Detached_State (S); end Remove_Unconnected_State; procedure Merge_NFA (L, R : NFA) is Last_L : constant NFA_State := Get_Last_State (L); First_R : constant NFA_State := Get_First_State (R); Last_R : constant NFA_State := Get_Last_State (R); begin if First_R = No_State then return; end if; if Last_L = No_State then Set_First_State (L, First_R); else Set_Next_State (Last_L, First_R); Set_Prev_State (First_R, Last_L); end if; Set_Last_State (L, Last_R); Set_First_State (R, No_State); Set_Last_State (R, No_State); Delete_Empty_NFA (R); end Merge_NFA; procedure Redest_Edges (S : NFA_State; Dest : NFA_State) is E, N_E : NFA_Edge; Head : NFA_Edge; begin E := Get_First_Dest_Edge (S); if E = No_Edge then return; end if; Set_First_Dest_Edge (S, No_Edge); Head := Get_First_Dest_Edge (Dest); Set_First_Dest_Edge (Dest, E); loop N_E := Get_Next_Dest_Edge (E); Set_Edge_Dest (E, Dest); exit when N_E = No_Edge; E := N_E; end loop; Set_Next_Dest_Edge (E, Head); end Redest_Edges; procedure Resource_Edges (S : NFA_State; Src : NFA_State) is E, N_E : NFA_Edge; Head : NFA_Edge; begin E := Get_First_Src_Edge (S); if E = No_Edge then return; end if; Set_First_Src_Edge (S, No_Edge); Head := Get_First_Src_Edge (Src); Set_First_Src_Edge (Src, E); loop N_E := Get_Next_Src_Edge (E); Set_Edge_Src (E, Src); exit when N_E = No_Edge; E := N_E; end loop; Set_Next_Src_Edge (E, Head); end Resource_Edges; procedure Disconnect_Edge_Src (N : NFA_State; E : NFA_Edge) is N_E : constant NFA_Edge := Get_Next_Src_Edge (E); Prev, Cur : NFA_Edge; begin Cur := Get_First_Src_Edge (N); if Cur = E then Set_First_Src_Edge (N, N_E); else while Cur /= E loop Prev := Cur; Cur := Get_Next_Src_Edge (Prev); pragma Assert (Cur /= No_Edge); end loop; Set_Next_Src_Edge (Prev, N_E); end if; end Disconnect_Edge_Src; procedure Disconnect_Edge_Dest (N : NFA_State; E : NFA_Edge) is N_E : constant NFA_Edge := Get_Next_Dest_Edge (E); Prev, Cur : NFA_Edge; begin Cur := Get_First_Dest_Edge (N); if Cur = E then Set_First_Dest_Edge (N, N_E); else while Cur /= E loop Prev := Cur; Cur := Get_Next_Dest_Edge (Prev); pragma Assert (Cur /= No_Edge); end loop; Set_Next_Dest_Edge (Prev, N_E); end if; end Disconnect_Edge_Dest; procedure Remove_Edge (E : NFA_Edge) is begin Disconnect_Edge_Src (Get_Edge_Src (E), E); Disconnect_Edge_Dest (Get_Edge_Dest (E), E); -- Put it on the free list. Set_Next_Dest_Edge (E, Free_Edges); Free_Edges := E; end Remove_Edge; procedure Remove_State (N : NFA; S : NFA_State) is E, N_E : NFA_Edge; begin E := Get_First_Dest_Edge (S); while E /= No_Edge loop N_E := Get_Next_Dest_Edge (E); Remove_Edge (E); E := N_E; end loop; E := Get_First_Src_Edge (S); while E /= No_Edge loop N_E := Get_Next_Src_Edge (E); Remove_Edge (E); E := N_E; end loop; Remove_Unconnected_State (N, S); end Remove_State; procedure Labelize_States (N : NFA; Nbr_States : out Natural) is S, Start, Final : NFA_State; begin S := Get_First_State (N); Start := Get_Start_State (N); Final := Get_Final_State (N); pragma Assert (Start /= No_State); Set_State_Label (Start, 0); Nbr_States := 1; while S /= No_State loop if S /= Start and then S /= Final then Set_State_Label (S, Int32 (Nbr_States)); Nbr_States := Nbr_States + 1; end if; S := Get_Next_State (S); end loop; pragma Assert (Final /= No_State); Set_State_Label (Final, Int32 (Nbr_States)); Nbr_States := Nbr_States + 1; end Labelize_States; procedure Labelize_States_Debug (N : NFA) is S : NFA_State; begin S := Get_First_State (N); while S /= No_State loop Set_State_Label (S, Int32 (S)); S := Get_Next_State (S); end loop; end Labelize_States_Debug; end PSL.NFAs; */ .highlight .err { color: #a61717; background-color: #e3d2d2 } /* Error */ .highlight .k { color: #008800; font-weight: bold } /* Keyword */ .highlight .ch { color: #888888 } /* Comment.Hashbang */ .highlight .cm { color: #888888 } /* Comment.Multiline */ .highlight .cp { color: #cc0000; font-weight: bold } /* Comment.Preproc */ .highlight .cpf { color: #888888 } /* Comment.PreprocFile */ .highlight .c1 { color: #888888 } /* Comment.Single */ .highlight .cs { color: #cc0000; font-weight: bold; background-color: #fff0f0 } /* Comment.Special */ .highlight .gd { color: #000000; background-color: #ffdddd } /* Generic.Deleted */ .highlight .ge { font-style: italic } /* Generic.Emph */ .highlight .gr { color: #aa0000 } /* Generic.Error */ .highlight .gh { color: #333333 } /* Generic.Heading */ .highlight .gi { color: #000000; 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font-weight: bold } /* Name.Class */ .highlight .no { color: #003366; font-weight: bold } /* Name.Constant */ .highlight .nd { color: #555555 } /* Name.Decorator */ .highlight .ne { color: #bb0066; font-weight: bold } /* Name.Exception */ .highlight .nf { color: #0066bb; font-weight: bold } /* Name.Function */ .highlight .nl { color: #336699; font-style: italic } /* Name.Label */ .highlight .nn { color: #bb0066; font-weight: bold } /* Name.Namespace */ .highlight .py { color: #336699; font-weight: bold } /* Name.Property */ .highlight .nt { color: #bb0066; font-weight: bold } /* Name.Tag */ .highlight .nv { color: #336699 } /* Name.Variable */ .highlight .ow { color: #008800 } /* Operator.Word */ .highlight .w { color: #bbbbbb } /* Text.Whitespace */ .highlight .mb { color: #0000DD; font-weight: bold } /* Literal.Number.Bin */ .highlight .mf { color: #0000DD; font-weight: bold } /* Literal.Number.Float */ .highlight .mh { color: #0000DD; font-weight: bold } /* Literal.Number.Hex */ .highlight .mi { color: #0000DD; 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/*
 *  yosys -- Yosys Open SYnthesis Suite
 *
 *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
 *
 *  Permission to use, copy, modify, and/or distribute this software for any
 *  purpose with or without fee is hereby granted, provided that the above
 *  copyright notice and this permission notice appear in all copies.
 *
 *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */

// See Xilinx UG953 and UG474 for a description of the cell types below.
// http://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf
// http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug953-vivado-7series-libraries.pdf

module VCC(output P);
  assign P = 1;
endmodule

module GND(output G);
  assign G = 0;
endmodule

module IBUF(output O, input I);
  parameter IOSTANDARD = "default";
  parameter IBUF_LOW_PWR = 0;
  assign O = I;
endmodule

module OBUF(output O, input I);
  parameter IOSTANDARD = "default";
  parameter DRIVE = 12;
  parameter SLEW = "SLOW";
  assign O = I;
endmodule

module BUFG(output O, input I);
  assign O = I;
endmodule

module BUFGCTRL(
    output O,
    input I0, input I1,
    input S0, input S1,
    input CE0, input CE1,
    input IGNORE0, input IGNORE1);

parameter [0:0] INIT_OUT = 1'b0;
parameter PRESELECT_I0 = "FALSE";
parameter PRESELECT_I1 = "FALSE";
parameter [0:0] IS_CE0_INVERTED = 1'b0;
parameter [0:0] IS_CE1_INVERTED = 1'b0;
parameter [0:0] IS_S0_INVERTED = 1'b0;
parameter [0:0] IS_S1_INVERTED = 1'b0;
parameter [0:0] IS_IGNORE0_INVERTED = 1'b0;
parameter [0:0] IS_IGNORE1_INVERTED = 1'b0;

wire I0_internal = ((CE0 ^ IS_CE0_INVERTED) ? I0 : INIT_OUT);
wire I1_internal = ((CE1 ^ IS_CE1_INVERTED) ? I1 : INIT_OUT);
wire S0_true = (S0 ^ IS_S0_INVERTED);
wire S1_true = (S1 ^ IS_S1_INVERTED);

assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT);

endmodule

module BUFHCE(output O, input I, input CE);

parameter [0:0] INIT_OUT = 1'b0;
parameter CE_TYPE = "SYNC";
parameter [0:0] IS_CE_INVERTED = 1'b0;

assign O = ((CE ^ IS_CE_INVERTED) ? I : INIT_OUT);

endmodule

// module OBUFT(output O, input I, T);
//   assign O = T ? 1'bz : I;
// endmodule

// module IOBUF(inout IO, output O, input I, T);
//   assign O = IO, IO = T ? 1'bz : I;
// endmodule

module INV(output O, input I);
  assign O = !I;
endmodule

module LUT1(output O, input I0);
  parameter [1:0] INIT = 0;
  assign O = I0 ? INIT[1] : INIT[0];
endmodule

module LUT2(output O, input I0, I1);
  parameter [3:0] INIT = 0;
  wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
  assign O = I0 ? s1[1] : s1[0];
endmodule

module LUT3(output O, input I0, I1, I2);
  parameter [7:0] INIT = 0;
  wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
  wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
  assign O = I0 ? s1[1] : s1[0];
endmodule

module LUT4(output O, input I0, I1, I2, I3);
  parameter [15:0] INIT = 0;
  wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
  wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
  wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
  assign O = I0 ? s1[1] : s1[0];
endmodule

module LUT5(output O, input I0, I1, I2, I3, I4);
  parameter [31:0] INIT = 0;
  wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0];
  wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
  wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
  wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
  assign O = I0 ? s1[1] : s1[0];
endmodule

module LUT6(output O, input I0, I1, I2, I3, I4, I5);
  parameter [63:0] INIT = 0;
  wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
  wire [15: 0] s4 = I4 ?   s5[31:16] :   s5[15: 0];
  wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
  wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
  wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
  assign O = I0 ? s1[1] : s1[0];
endmodule

module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5);
  parameter [63:0] INIT = 0;
  wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
  wire [15: 0] s4 = I4 ?   s5[31:16] :   s5[15: 0];
  wire [ 7: 0] s3 = I3 ?   s4[15: 8] :   s4[ 7: 0];
  wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
  wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
  assign O6 = I0 ? s1[1] : s1[0];

  wire [15: 0] s5_4 = I4 ? INIT[31:16] : INIT[15: 0];
  wire [ 7: 0] s5_3 = I3 ? s5_4[15: 8] : s5_4[ 7: 0];
  wire [ 3: 0] s5_2 = I2 ? s5_3[ 7: 4] : s5_3[ 3: 0];
  wire [ 1: 0] s5_1 = I1 ? s5_2[ 3: 2] : s5_2[ 1: 0];
  assign O5 = I0 ? s5_1[1] : s5_1[0];
endmodule

module MUXCY(output O, input CI, DI, S);
  assign O = S ? CI : DI;
endmodule

(* abc_box_id = 1, lib_whitebox *)
module MUXF7(output O, input I0, I1, S);
  assign O = S ? I1 : I0;
endmodule

(* abc_box_id = 2, lib_whitebox *)
module MUXF8(output O, input I0, I1, S);
  assign O = S ? I1 : I0;
endmodule

module XORCY(output O, input CI, LI);
  assign O = CI ^ LI;
endmodule

(* abc_box_id = 3, abc_carry, lib_whitebox *)
module CARRY4((* abc_carry_out *) output [3:0] CO, output [3:0] O, (* abc_carry_in *) input CI, input CYINIT, input [3:0] DI, S);
  assign O = S ^ {CO[2:0], CI | CYINIT};
  assign CO[0] = S[0] ? CI | CYINIT : DI[0];
  assign CO[1] = S[1] ? CO[0] : DI[1];
  assign CO[2] = S[2] ? CO[1] : DI[2];
  assign CO[3] = S[3] ? CO[2] : DI[3];
endmodule

`ifdef _EXPLICIT_CARRY

module CARRY0(output CO_CHAIN, CO_FABRIC, O, input CI, CI_INIT, DI, S);
  parameter CYINIT_FABRIC = 0;
  wire CI_COMBINE;
  if(CYINIT_FABRIC) begin
    assign CI_COMBINE = CI_INIT;
  end else begin
    assign CI_COMBINE = CI;
  end
  assign CO_CHAIN = S ? CI_COMBINE : DI;
  assign CO_FABRIC = S ? CI_COMBINE : DI;
  assign O = S ^ CI_COMBINE;
endmodule

module CARRY(output CO_CHAIN, CO_FABRIC, O, input CI, DI, S);
  assign CO_CHAIN = S ? CI : DI;
  assign CO_FABRIC = S ? CI : DI;
  assign O = S ^ CI;
endmodule

`endif

module FDRE (output reg Q, input C, CE, D, R);
  parameter [0:0] INIT = 1'b0;
  parameter [0:0] IS_C_INVERTED = 1'b0;
  parameter [0:0] IS_D_INVERTED = 1'b0;
  parameter [0:0] IS_R_INVERTED = 1'b0;
  initial Q <= INIT;
  generate case (|IS_C_INVERTED)
    1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
    1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
  endcase endgenerate
endmodule

module FDSE (output reg Q, input C, CE, D, S);
  parameter [0:0] INIT = 1'b0;
  parameter [0:0] IS_C_INVERTED = 1'b0;
  parameter [0:0] IS_D_INVERTED = 1'b0;
  parameter [0:0] IS_S_INVERTED = 1'b0;
  initial Q <= INIT;
  generate case (|IS_C_INVERTED)
    1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
    1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
  endcase endgenerate
endmodule

module FDCE (output reg Q, input C, CE, D, CLR);
  parameter [0:0] INIT = 1'b0;
  parameter [0:0] IS_C_INVERTED = 1'b0;
  parameter [0:0] IS_D_INVERTED = 1'b0;
  parameter [0:0] IS_CLR_INVERTED = 1'b0;
  initial Q <= INIT;
  generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
    2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
    2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
    2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
    2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
  endcase endgenerate
endmodule

module FDPE (output reg Q, input C, CE, D, PRE);
  parameter [0:0] INIT = 1'b0;
  parameter [0:0] IS_C_INVERTED = 1'b0;
  parameter [0:0] IS_D_INVERTED = 1'b0;
  parameter [0:0] IS_PRE_INVERTED = 1'b0;
  initial Q <= INIT;
  generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
    2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
    2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
    2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
    2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
  endcase endgenerate
endmodule

module FDRE_1 (output reg Q, input C, CE, D, R);
  parameter [0:0] INIT = 1'b0;
  initial Q <= INIT;
  always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
endmodule

module FDSE_1 (output reg Q, input C, CE, D, S);
  parameter [0:0] INIT = 1'b1;
  initial Q <= INIT;
  always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
endmodule

module FDCE_1 (output reg Q, input C, CE, D, CLR);
  parameter [0:0] INIT = 1'b0;
  initial Q <= INIT;
  always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
endmodule

module FDPE_1 (output reg Q, input C, CE, D, PRE);
  parameter [0:0] INIT = 1'b1;
  initial Q <= INIT;
  always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
endmodule

//(* abc_box_id = 4 /*, lib_whitebox*/ *)
module RAM64X1D (
  output DPO, SPO,
  input  D, WCLK, WE,
  input  A0, A1, A2, A3, A4, A5,
  input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
);
  parameter INIT = 64'h0;
  parameter IS_WCLK_INVERTED = 1'b0;
  wire [5:0] a = {A5, A4, A3, A2, A1, A0};
  wire [5:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
  reg [63:0] mem = INIT;
  assign SPO = mem[a];
  assign DPO = mem[dpra];
  wire clk = WCLK ^ IS_WCLK_INVERTED;
  always @(posedge clk) if (WE) mem[a] <= D;
endmodule

//(* abc_box_id = 5 /*, lib_whitebox*/ *)
module RAM128X1D (
  output       DPO, SPO,
  input        D, WCLK, WE,
  input  [6:0] A, DPRA
);
  parameter INIT = 128'h0;
  parameter IS_WCLK_INVERTED = 1'b0;
  reg [127:0] mem = INIT;
  assign SPO = mem[A];
  assign DPO = mem[DPRA];
  wire clk = WCLK ^ IS_WCLK_INVERTED;
  always @(posedge clk) if (WE) mem[A] <= D;
endmodule

module SRL16E (
  output Q,
  input A0, A1, A2, A3, CE, CLK, D
);
  parameter [15:0] INIT = 16'h0000;
  parameter [0:0] IS_CLK_INVERTED = 1'b0;

  reg [15:0] r = INIT;
  assign Q = r[{A3,A2,A1,A0}];
  generate
    if (IS_CLK_INVERTED) begin
      always @(negedge CLK) if (CE) r <= { r[14:0], D };
    end
    else
        always @(posedge CLK) if (CE) r <= { r[14:0], D };
  endgenerate
endmodule

module SRLC32E (
  output Q,
  output Q31,
  input [4:0] A,
  input CE, CLK, D
);
  parameter [31:0] INIT = 32'h00000000;
  parameter [0:0] IS_CLK_INVERTED = 1'b0;

  reg [31:0] r = INIT;
  assign Q31 = r[31];
  assign Q = r[A];
  generate
    if (IS_CLK_INVERTED) begin
      always @(negedge CLK) if (CE) r <= { r[30:0], D };
    end
    else
      always @(posedge CLK) if (CE) r <= { r[30:0], D };
  endgenerate
endmodule
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-10 16:03:10 +0000