-- Semantic analysis. -- Copyright (C) 2002, 2003, 2004, 2005 Tristan Gingold -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see . with Vhdl.Nodes; use Vhdl.Nodes; with Vhdl.Sem_Expr; use Vhdl.Sem_Expr; package Vhdl.Sem_Assocs is -- Rewrite the association chain by changing the kind of assocation -- corresponding to non-object interfaces. Such an association mustn't be -- handled an like association for object as the actual is not an -- expression. function Extract_Non_Object_Association (Assoc_Chain : Iir; Inter_Chain : Iir) return Iir; -- Analyze actuals of ASSOC_CHAIN. -- Check all named associations are after positionnal one. -- Return TRUE if no error. function Sem_Actual_Of_Association_Chain (Assoc_Chain : Iir) return Boolean; -- Analyze association chain ASSOC_CHAIN with interfaces from -- INTERFACE_CHAIN. -- Return the level of compatibility between the two chains in LEVEL. -- If FINISH is true, then ASSOC_CHAIN may be modifies (individual assoc -- added), and error messages (if any) are displayed. -- MISSING control unassociated interfaces. -- LOC is the association. -- Sem_Actual_Of_Association_Chain must have been called before. type Missing_Type is (Missing_Parameter, Missing_Port, Missing_Generic, Missing_Allowed); procedure Sem_Association_Chain (Interface_Chain : Iir; Assoc_Chain: in out Iir; Finish: Boolean; Missing : Missing_Type; Loc : Iir; Match : out Compatibility_Level); -- Do port Sem_Association_Chain checks for subprograms. procedure Check_Subprogram_Associations (Inter_Chain : Iir; Assoc_Chain : Iir); -- Check for restrictions in LRM93 1.1.1.2 -- Return FALSE in case of error. function Check_Port_Association_Mode_Restrictions (Formal : Iir_Interface_Signal_Declaration; Actual : Iir_Interface_Signal_Declaration; Assoc : Iir) return Boolean; -- Check restrictions of LRM02 12.2.4 procedure Check_Port_Association_Bounds_Restrictions (Formal : Iir; Actual : Iir; Assoc : Iir); -- LRM93 8.6 Procedure Call Statement -- For each formal parameter of a procedure, a procedure call must -- specify exactly one corresponding actual parameter. -- This actual parameter is specified either explicitly, by an -- association element (other than the actual OPEN) in the association -- list, or in the absence of such an association element, by a default -- expression (see Section 4.3.3.2). -- -- LRM93 7.3.3 Function Calls -- For each formal parameter of a function, a function call must -- specify exactly one corresponding actual parameter. -- This actual parameter is specified either explicitly, by an -- association element (other than the actual OPEN) in the association -- list, or in the absence of such an association element, by a default -- expression (see Section 4.3.3.2). -- -- LRM93 1.1.1.2 / LRM08 6.5.6.3 Port clauses -- A port of mode IN may be unconnected or unassociated only if its -- declaration includes a default expression. -- A port of any mode other than IN may be unconnected or unassociated -- as long as its type is not an unconstrained array type. -- -- LRM08 6.5.6.2 Generic clauses -- It is an error if no such actual [instantiated package] is specified -- for a given formal generic package (either because the formal generic -- is unassociated or because the actual is OPEN). -- -- INTER is an interface that is known not to be associated. -- Report an error according to MISSING iff FINISH is true. -- Return True iff not associating INTER is an error. function Sem_Check_Missing_Association (Inter : Iir; Missing : Missing_Type; Finish : Boolean; Loc : Iir) return Boolean; end Vhdl.Sem_Assocs; '#n38'>38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 
// The four D flip-flops (DFFs) in a Cyclone V/10GX Adaptive Logic Module (ALM)
// act as one-bit memory cells that can be placed very flexibly (wherever there's
// an ALM); each flop is represented by a MISTRAL_FF cell.
//
// The flops in these chips are rather flexible in some ways, but in practice
// quite crippled by FPGA standards.
//
// What the flops can do
// ---------------------
// The core flop acts as a single-bit memory that initialises to zero at chip
// reset. It takes in data on the rising edge of CLK if ENA is high,
// and outputs it to Q. The ENA (clock enable) pin can therefore be used to
// capture the input only if a condition is true.
//
// The data itself is zero if SCLR (synchronous clear) is high, else it comes
// from SDATA (synchronous data) if SLOAD (synchronous load) is high, or DATAIN
// if SLOAD is low.
//
// If ACLR (asynchronous clear) is low then Q is forced to zero, regardless of
// the synchronous inputs or CLK edge. This is most often used for an FPGA-wide
// power-on reset.
//
// An asynchronous set that sets Q to one can be emulated by inverting the input
// and output of the flop, resulting in ACLR forcing Q to zero, which then gets
// inverted to produce one. Likewise, logic can operate on the falling edge of
// CLK if CLK is inverted before being passed as an input.
//
// What the flops *can't* do
// -------------------------
// The trickiest part of the above capabilities is the lack of configurable
// initialisation state. For example, it isn't possible to implement a flop with
// asynchronous clear that initialises to one, because the hardware initialises
// to zero. Likewise, you can't emulate a flop with asynchronous set that
// initialises to zero, because the inverters mean the flop initialises to one.
//
// If the input design requires one of these cells (which appears to be rare
// in practice) then synth_intel_alm will fail to synthesize the design where
// other Yosys synthesis scripts might succeed.
//
// This stands in notable contrast to e.g. Xilinx flip-flops, which have
// configurable initialisation state and native synchronous/asynchronous
// set/clear (although not at the same time), which means they can generally
// implement a much wider variety of logic.

// DATAIN: synchronous data input
// CLK: clock input (positive edge)
// ACLR: asynchronous clear (negative-true)
// ENA: clock-enable
// SCLR: synchronous clear
// SLOAD: synchronous load
// SDATA: synchronous load data
//
// Q: data output
//
// Note: the DFFEAS primitive is mostly emulated; it does not reflect what the hardware implements.

(* abc9_box, lib_whitebox *)
module MISTRAL_FF(
    input DATAIN,
    (* clkbuf_sink *) input CLK,
    input ACLR, ENA, SCLR, SLOAD, SDATA,
    output reg Q
);

`ifdef cyclonev
specify
    if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = 731;
    if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = 890;
    if (ENA && !SCLR && SLOAD) (posedge CLK => (Q : SDATA)) = 618;

    $setup(DATAIN, posedge CLK, /* -196 */ 0);
    $setup(ENA, posedge CLK, /* -196 */ 0);
    $setup(SCLR, posedge CLK, /* -196 */ 0);
    $setup(SLOAD, posedge CLK, /* -196 */ 0);
    $setup(SDATA, posedge CLK, /* -196 */ 0);

    if (ACLR === 1'b0) (ACLR => Q) = 282;
endspecify
`endif
`ifdef cyclone10gx
specify
    // TODO (long-term): investigate these numbers.
    // It seems relying on the Quartus Timing Analyzer was not the best idea; it's too fiddly.
    if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = 219;
    if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = 219;
    if (ENA && !SCLR && SLOAD) (posedge CLK => (Q : SDATA)) = 219;

    $setup(DATAIN, posedge CLK, 268);
    $setup(ENA, posedge CLK, 268);
    $setup(SCLR, posedge CLK, 268);
    $setup(SLOAD, posedge CLK, 268);
    $setup(SDATA, posedge CLK, 268);

    if (ACLR === 1'b0) (ACLR => Q) = 0;
endspecify
`endif

initial begin
    // Altera flops initialise to zero.
	Q = 0;
end

always @(posedge CLK, negedge ACLR) begin
    // Asynchronous clear
    if (!ACLR) Q <= 0;
    // Clock-enable
	else if (ENA) begin
        // Synchronous clear
        if (SCLR) Q <= 0;
        // Synchronous load
        else if (SLOAD) Q <= SDATA;
        else Q <= DATAIN;
    end
end

endmodule
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