/* * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2018 Miodrag Milanovic * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ #include "kernel/yosys.h" #include "kernel/sigtools.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN struct AnlogicEqnPass : public Pass { AnlogicEqnPass() : Pass("anlogic_eqn", "Anlogic: Calculate equations for luts") { } void help() YS_OVERRIDE { log("\n"); log(" anlogic_eqn [selection]\n"); log("\n"); log("Calculate equations for luts since bitstream generator depends on it.\n"); log("\n"); } Const init2eqn(Const init, int inputs) { std::string init_bits = init.as_string(); const char* names[] = { "A" , "B", "C", "D", "E", "F" }; std::string eqn; int width = (int)pow(2,inputs); for(int i=0;i args, RTLIL::Design *design) YS_OVERRIDE { log_header(design, "Executing ANLOGIC_EQN pass (calculate equations for luts).\n"); extra_args(args, args.size(), design); int cnt = 0; for (auto module : design->selected_modules()) { for (auto cell : module->selected_cells()) { if (cell->type == "\\AL_MAP_LUT1") { cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),1)); cnt++; } if (cell->type == "\\AL_MAP_LUT2") { cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),2)); cnt++; } if (cell->type == "\\AL_MAP_LUT3") { cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),3)); cnt++; } if (cell->type == "\\AL_MAP_LUT4") { cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),4)); cnt++; } if (cell->type == "\\AL_MAP_LUT5") { cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),5)); cnt++; } if (cell->type == "\\AL_MAP_LUT6") { cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),6)); cnt++; } } } log_header(design, "Updated %d of AL_MAP_LUT* elements with equation.\n", cnt); } } AnlogicEqnPass; PRIVATE_NAMESPACE_END /cgit.cgi/iCE40/yosys/plain/techlibs/ice40/tests/test_bram.v?id=0aad88a2fb23e5481538122e1bd4c0fac9ba5e90'>plain) 
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module bram #(
	parameter ABITS = 8, DBITS = 8,
	parameter INIT_ADDR = 0, INIT_DATA = 0
) (
	input clk,

	input [ABITS-1:0] WR_ADDR,
	input [DBITS-1:0] WR_DATA,
	input WR_EN,

	input [ABITS-1:0] RD_ADDR,
	output reg [DBITS-1:0] RD_DATA
);
	reg [DBITS-1:0] memory [0:2**ABITS-1];

	initial begin
		memory[INIT_ADDR] <= INIT_DATA;
	end

	always @(posedge clk) begin
		if (WR_EN) memory[WR_ADDR] <= WR_DATA;
		RD_DATA <= memory[RD_ADDR];
	end
endmodule
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-11 06:53:30 +0000