-- module GCD where
--
--
-- $wmygcd::*Int# -> *Int# -> *Int#
-- $wmygcd ww ww1 =
-- let wild::GHC.Types.Bool = (GHC.Prim.==# ww ww1) in
-- case wild of :: *Int#
-- GHC.Types.False ->
-- let wild1::GHC.Types.Bool = (GHC.Prim.<# ww ww1) in
-- case wild1 of :: *Int#
-- GHC.Types.False -> ($wmygcd (GHC.Prim.-# ww ww1) ww1)
-- GHC.Types.True -> ($wmygcd ww (GHC.Prim.-# ww1 ww))
-- GHC.Types.True -> ww
--
-- mygcd::GHC.Types.Int -> GHC.Types.Int -> GHC.Types.Int
-- mygcd w w1 =
-- let w2::GHC.Types.Int = w in
-- case w2 of :: GHC.Types.Int
-- GHC.Types.I# ww::*Int# ->
-- let w3::GHC.Types.Int = w1 in
-- case w3 of :: GHC.Types.Int
-- GHC.Types.I# ww1::*Int# ->
-- let ww2::*Int# = ($wmygcd ww ww1) in
-- case ww2 of :: GHC.Types.Int DEFAULT -> (GHC.Types.I# ww2)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.\Prim\.all;
package \GCD\ is
end \GCD\;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.\Prim\.all;
use work.\GCD\.all;
entity \$wmygcd\ is
port (clk : in std_logic;
s1_call : in std_logic;
s1_ret : out std_logic;
s1_ww : in \Int#\;
s1_ww1 : in \Int#\;
res : out \Int#\);
end entity;
architecture rtl of \$wmygcd\ is
signal tail_call : std_logic;
signal tail_ww : \Int#\;
signal tail_ww1 : \Int#\;
signal core_call : std_logic;
signal core_ret : std_logic;
signal core_ww : \Int#\;
signal core_ww1 : \Int#\;
signal s1_act : std_logic;
signal s1_wait : std_logic;
signal s1_saved_ww : \Int#\;
signal s1_saved_ww1 : \Int#\;
begin
process (core_call, core_ww, core_ww1)
variable wild : \GHC.Types.Bool\;
variable wild1 : \GHC.Types.Bool\;
variable ww : \Int#\;
variable ww1 : \Int#\;
begin
ww := core_ww;
ww1 := core_ww1;
wild := \GHC.Prim.==#\(ww, ww1);
if \is_GHC.Types.False\(wild) then
wild1 := \GHC.Prim.<#\(ww, ww1);
if \is_GHC.Types.False\(wild1) then
res <= \$wmygcd\(\GHC.Prim.-#\(ww, ww1), ww1);
elsif \is_GHC.Types.True\(wild1) then
res <= \$wmygcd\(ww, \GHC.Prim.-#\(ww1, ww));
end if;
elsif \is_GHC.Types.True\(wild) then res <= ww;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
core_call <= '0';
if s1_call = '1' then
s1_wait <= '1';
s1_saved_ww <= s1_ww;
s1_saved_ww1 <= s1_ww1;
end if;
if tail_call = '1' then
core_call <= '1';
core_ww <= tail_ww;
core_ww1 <= tail_ww1;
elsif core_ret = '1' or s1_act = '1' then
s1_act <= '0';
if s1_wait = '1' then
core_call <= '1';
s1_act <= '1';
s1_wait <= '0';
core_ww <= s1_saved_ww;
core_ww1 <= s1_saved_ww1;
elsif s1_call = '1' then
core_call <= '1';
s1_act <= '1';
s1_wait <= '0';
core_ww <= s1_ww;
core_ww1 <= s1_ww1;
end if;
end if;
end if;
end process;
s1_ret <= core_ret and s1_act;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.\Prim\.all;
use work.\GCD\.all;
entity mygcd is
port (clk : in std_logic;
s1_call : in std_logic;
s1_ret : out std_logic;
s1_w : in \GHC.Types.Int\;
s1_w1 : in \GHC.Types.Int\;
res : out \GHC.Types.Int\);
end entity;
architecture rtl of mygcd is
signal tail_call : std_logic;
signal tail_w : \GHC.Types.Int\;
signal tail_w1 : \GHC.Types.Int\;
signal core_call : std_logic;
signal core_ret : std_logic;
signal core_w : \GHC.Types.Int\;
signal core_w1 : \GHC.Types.Int\;
signal s1_act : std_logic;
signal s1_wait : std_logic;
signal s1_saved_w : \GHC.Types.Int\;
signal s1_saved_w1 : \GHC.Types.Int\;
begin
process (core_call, core_w, core_w1)
variable w2 : \GHC.Types.Int\;
variable ww : \Int#\;
variable w3 : \GHC.Types.Int\;
variable ww1 : \Int#\;
variable ww2 : \Int#\;
variable w : \GHC.Types.Int\;
variable w1 : \GHC.Types.Int\;
begin
w := core_w;
w1 := core_w1;
w2 := w;
if \is_GHC.Types.I#\(w2) then
\expand_GHC.Types.I#\(w2, ww);
w3 := w1;
if \is_GHC.Types.I#\(w3) then
\expand_GHC.Types.I#\(w3, ww1);
ww2 := \$wmygcd\(ww, ww1);
res <= \GHC.Types.I#\(ww2);
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
core_call <= '0';
if s1_call = '1' then
s1_wait <= '1';
s1_saved_w <= s1_w;
s1_saved_w1 <= s1_w1;
end if;
if tail_call = '1' then
core_call <= '1';
core_w <= tail_w;
core_w1 <= tail_w1;
elsif core_ret = '1' or s1_act = '1' then
s1_act <= '0';
if s1_wait = '1' then
core_call <= '1';
s1_act <= '1';
s1_wait <= '0';
core_w <= s1_saved_w;
core_w1 <= s1_saved_w1;
elsif s1_call = '1' then
core_call <= '1';
s1_act <= '1';
s1_wait <= '0';
core_w <= s1_w;
core_w1 <= s1_w1;
end if;
end if;
end if;
end process;
s1_ret <= core_ret and s1_act;
end architecture;
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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/yosys.h"
#include "kernel/sigtools.h"
#include <stdlib.h>
#include <stdio.h>
#include <bitset>
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
static void run_ice40_braminit(Module *module)
{
for (auto cell : module->selected_cells())
{
uint16_t mem[256];
/* Only consider cells we're interested in */
if (cell->type != ID(SB_RAM40_4K) &&
cell->type != ID(SB_RAM40_4KNR) &&
cell->type != ID(SB_RAM40_4KNW) &&
cell->type != ID(SB_RAM40_4KNRNW))
continue;
if (!cell->hasParam(ID(INIT_FILE)))
continue;
std::string init_file = cell->getParam(ID(INIT_FILE)).decode_string();
cell->unsetParam(ID(INIT_FILE));
if (init_file == "")
continue;
/* Open file */
log("Processing %s : %s\n", RTLIL::id2cstr(cell->name), init_file.c_str());
std::ifstream f;
f.open(init_file.c_str());
if (f.fail()) {
log("Can not open file `%s`.\n", init_file.c_str());
continue;
}
/* Defaults to 0 */
memset(mem, 0x00, sizeof(mem));
/* Process each line */
bool in_comment = false;
int cursor = 0;
while (!f.eof())
{
std::string line, token;
std::getline(f, line);
for (int i = 0; i < GetSize(line); i++)
{
if (in_comment && line.compare(i, 2, "*/") == 0) {
line[i] = ' ';
line[i+1] = ' ';
in_comment = false;
continue;
}
if (!in_comment && line.compare(i, 2, "/*") == 0)
in_comment = true;
if (in_comment)
line[i] = ' ';
}
while (1)
{
bool set_cursor = false;
long value;
token = next_token(line, " \t\r\n");
if (token.empty() || token.compare(0, 2, "//") == 0)
break;
if (token[0] == '@') {
token = token.substr(1);
set_cursor = true;
}
const char *nptr = token.c_str();
char *endptr;
value = strtol(nptr, &endptr, 16);
if (!*nptr || *endptr) {
log("Can not parse %s `%s` for %s.\n",
set_cursor ? "address" : "value",
nptr, token.c_str()
);
continue;
}
if (set_cursor)
cursor = value;
else if (cursor >= 0 && cursor < 256)
mem[cursor++] = value;
else
log("Attempt to initialize non existent address %d\n", cursor);
}
}
/* Set attributes */
const char *hex = "0123456789ABCDEF";
for (int i=0; i<16; i++) {
std::string val = "";
for (int j=15; j>=0; j--)
val += std::bitset<16>(mem[i*16+j]).to_string();
cell->setParam("\\INIT_" + std::string(1, hex[i]), RTLIL::Const::from_string(val));
}
}
}
struct Ice40BRAMInitPass : public Pass {
Ice40BRAMInitPass() : Pass("ice40_braminit", "iCE40: perform SB_RAM40_4K initialization from file") { }
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" ice40_braminit\n");
log("\n");
log("This command processes all SB_RAM40_4K blocks with a non-empty INIT_FILE\n");
log("parameter and converts it into the required INIT_x attributes\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing ICE40_BRAMINIT pass.\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
// if (args[argidx] == "-???") {
// continue;
// }
break;
}
extra_args(args, argidx, design);
for (auto module : design->selected_modules())
run_ice40_braminit(module);
}
} Ice40BRAMInitPass;
PRIVATE_NAMESPACE_END
|