/* * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf * Copyright (C) 2018 Serge Bazanski * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ #include #include "kernel/rtlil.h" #include "kernel/register.h" #include "kernel/sigtools.h" #include "kernel/celltypes.h" #include "kernel/cellaigs.h" #include "kernel/log.h" #include "yosys.pb.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN struct ProtobufDesignSerializer { bool aig_mode_; bool use_selection_; yosys::pb::Design *pb_; Design *design_; Module *module_; SigMap sigmap_; int sigidcounter_; dict sigids_; pool aig_models_; ProtobufDesignSerializer(bool use_selection, bool aig_mode) : aig_mode_(aig_mode), use_selection_(use_selection) { } string get_name(IdString name) { return RTLIL::unescape_id(name); } void serialize_parameters(google::protobuf::Map *out, const dict ¶meters) { for (auto ¶m : parameters) { std::string key = get_name(param.first); yosys::pb::Parameter pb_param; if ((param.second.flags & RTLIL::ConstFlags::CONST_FLAG_STRING) != 0) { pb_param.set_str(param.second.decode_string()); } else if (GetSize(param.second.bits) > 64) { pb_param.set_str(param.second.as_string()); } else { pb_param.set_int_(param.second.as_int()); } (*out)[key] = pb_param; } } void get_bits(yosys::pb::BitVector *out, SigSpec sig) { for (auto bit : sigmap_(sig)) { auto sig = out->add_signal(); // Constant driver. if (bit.wire == nullptr) { if (bit == State::S0) sig->set_constant(sig->CONSTANT_DRIVER_LOW); else if (bit == State::S1) sig->set_constant(sig->CONSTANT_DRIVER_HIGH); else if (bit == State::Sz) sig->set_constant(sig->CONSTANT_DRIVER_Z); else sig->set_constant(sig->CONSTANT_DRIVER_X); continue; } // Signal - give it a unique identifier. if (sigids_.count(bit) == 0) { sigids_[bit] = sigidcounter_++; } sig->set_id(sigids_[bit]); } } void serialize_module(yosys::pb::Module* out, Module *module) { module_ = module; log_assert(module_->design == design_); sigmap_.set(module_); sigids_.clear(); sigidcounter_ = 0; serialize_parameters(out->mutable_attribute(), module_->attributes); for (auto n : module_->ports) { Wire *w = module->wire(n); if (use_selection_ && !module_->selected(w)) continue; yosys::pb::Module::Port pb_port; pb_port.set_direction(w->port_input ? w->port_output ? yosys::pb::DIRECTION_INOUT : yosys::pb::DIRECTION_INPUT : yosys::pb::DIRECTION_OUTPUT); get_bits(pb_port.mutable_bits(), w); (*out->mutable_port())[get_name(n)] = pb_port; } for (auto c : module_->cells()) { if (use_selection_ && !module_->selected(c)) continue; yosys::pb::Module::Cell pb_cell; pb_cell.set_hide_name(c->name[0] == '$'); pb_cell.set_type(get_name(c->type)); if (aig_mode_) { Aig aig(c); if (aig.name.empty()) continue; pb_cell.set_model(aig.name);

module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
	parameter [63:0]INIT = 64'bx;
	input CLK1;

	input [3:0] A1ADDR;
	output [3:0] A1DATA;

	input [3:0] B1ADDR;
	input [3:0] B1DATA;
	input B1EN;

	EG_LOGIC_DRAM16X4 #(
		`include "lutram_init_16x4.vh"
	) _TECHMAP_REPLACE_ (
		.di(B1DATA),
		.waddr(B1ADDR),
		.wclk(CLK1),
		.we(B1EN),
		.raddr(A1ADDR),
		.do(A1DATA)
	);
endmodule