<!DOCTYPE html>
<html lang='en'>
<head>
<title>xen/xen - xen</title>
<meta name='generator' content='cgit v1.2.3'/>
<meta name='robots' content='index, nofollow'/>
<link rel='stylesheet' type='text/css' href='/cgit.css'/>
<link rel='shortcut icon' href='/favicon.ico'/>
<link rel='alternate' title='Atom feed' href='http://git.panaceas.org/cgit.cgi/xen/xen/atom/xen/arch/x86/domain.c?h=master' type='application/atom+xml'/>
<link rel='vcs-git' href='git://git.panaceas.org/xen/xen' title='xen/xen Git repository'/>
<link rel='vcs-git' href='ssh://git@git.panaceas.org/git/xen/xen' title='xen/xen Git repository'/>
</head>
<body>
<div id='cgit'><table id='header'>
<tr>
<td class='logo' rowspan='2'><a href='/cgit.cgi/'><img src='/cgit.png' alt='cgit logo'/></a></td>
<td class='main'><a href='/cgit.cgi/'>index</a> : <a title='xen/xen' href='/cgit.cgi/xen/xen/'>xen/xen</a></td><td class='form'><form method='get'>
<input type='hidden' name='id' value='5ecfc3555d01658e281e1fd177677490ec57a6d9'/><select name='h' onchange='this.form.submit();'>
<option value='master' selected='selected'>master</option>
<option value='stable-4.0'>stable-4.0</option>
<option value='stable-4.1'>stable-4.1</option>
<option value='stable-4.2'>stable-4.2</option>
<option value='stable-4.3'>stable-4.3</option>
<option value='staging'>staging</option>
<option value='staging-4.0'>staging-4.0</option>
<option value='staging-4.1'>staging-4.1</option>
<option value='staging-4.2'>staging-4.2</option>
<option value='staging-4.3'>staging-4.3</option>
</select> <input type='submit' value='switch'/></form></td></tr>
<tr><td class='sub'>xen</td><td class='sub right'>James</td></tr></table>
<table class='tabs'><tr><td>
<a href='/cgit.cgi/xen/xen/about/'>about</a><a href='/cgit.cgi/xen/xen/'>summary</a><a href='/cgit.cgi/xen/xen/refs/?id=5ecfc3555d01658e281e1fd177677490ec57a6d9'>refs</a><a href='/cgit.cgi/xen/xen/log/xen/arch/x86/domain.c'>log</a><a href='/cgit.cgi/xen/xen/tree/xen/arch/x86/domain.c?id=5ecfc3555d01658e281e1fd177677490ec57a6d9'>tree</a><a class='active' href='/cgit.cgi/xen/xen/commit/xen/arch/x86/domain.c?id=5ecfc3555d01658e281e1fd177677490ec57a6d9'>commit</a><a href='/cgit.cgi/xen/xen/diff/xen/arch/x86/domain.c?id=5ecfc3555d01658e281e1fd177677490ec57a6d9'>diff</a><a href='/cgit.cgi/xen/xen/stats/xen/arch/x86/domain.c'>stats</a></td><td class='form'><form class='right' method='get' action='/cgit.cgi/xen/xen/log/xen/arch/x86/domain.c'>
<input type='hidden' name='id' value='5ecfc3555d01658e281e1fd177677490ec57a6d9'/><select name='qt'>
<option value='grep'>log msg</option>
<option value='author'>author</option>
<option value='committer'>committer</option>
<option value='range'>range</option>
</select>
<input class='txt' type='search' size='10' name='q' value=''/>
<input type='submit' value='search'/>
</form>
</td></tr></table>
<div class='path'>path: <a href='/cgit.cgi/xen/xen/commit/?id=5ecfc3555d01658e281e1fd177677490ec57a6d9'>root</a>/<a href='/cgit.cgi/xen/xen/commit/xen?id=5ecfc3555d01658e281e1fd177677490ec57a6d9'>xen</a>/<a href='/cgit.cgi/xen/xen/commit/xen/arch?id=5ecfc3555d01658e281e1fd177677490ec57a6d9'>arch</a>/<a href='/cgit.cgi/xen/xen/commit/xen/arch/x86?id=5ecfc3555d01658e281e1fd177677490ec57a6d9'>x86</a>/<a href='/cgit.cgi/xen/xen/commit/xen/arch/x86/domain.c?id=5ecfc3555d01658e281e1fd177677490ec57a6d9'>domain.c</a></div><div class='content'><div class='cgit-panel'><b>diff options</b><form method='get'><input type='hidden' name='id' value='5ecfc3555d01658e281e1fd177677490ec57a6d9'/><table><tr><td colspan='2'/></tr><tr><td class='label'>context:</td><td class='ctrl'><select name='context' onchange='this.form.submit();'><option value='1'>1</option><option value='2'>2</option><option value='3' selected='selected'>3</option><option value='4'>4</option><option value='5'>5</option><option value='6'>6</option><option value='7'>7</option><option value='8'>8</option><option value='9'>9</option><option value='10'>10</option><option value='15'>15</option><option value='20'>20</option><option value='25'>25</option><option value='30'>30</option><option value='35'>35</option><option value='40'>40</option></select></td></tr><tr><td class='label'>space:</td><td class='ctrl'><select name='ignorews' onchange='this.form.submit();'><option value='0' selected='selected'>include</option><option value='1'>ignore</option></select></td></tr><tr><td class='label'>mode:</td><td class='ctrl'><select name='dt' onchange='this.form.submit();'><option value='0' selected='selected'>unified</option><option value='1'>ssdiff</option><option value='2'>stat only</option></select></td></tr><tr><td/><td class='ctrl'><noscript><input type='submit' value='reload'/></noscript></td></tr></table></form></div><table summary='commit info' class='commit-info'>
<tr><th>author</th><td>Keir Fraser &lt;keir.fraser@citrix.com&gt;</td><td class='right'>2008-06-05 10:34:01 +0100</td></tr>
<tr><th>committer</th><td>Keir Fraser &lt;keir.fraser@citrix.com&gt;</td><td class='right'>2008-06-05 10:34:01 +0100</td></tr>
<tr><th>commit</th><td colspan='2' class='sha1'><a href='/cgit.cgi/xen/xen/commit/xen/arch/x86/domain.c?id=5ecfc3555d01658e281e1fd177677490ec57a6d9'>5ecfc3555d01658e281e1fd177677490ec57a6d9</a> (<a href='/cgit.cgi/xen/xen/patch/xen/arch/x86/domain.c?id=5ecfc3555d01658e281e1fd177677490ec57a6d9'>patch</a>)</td></tr>
<tr><th>tree</th><td colspan='2' class='sha1'><a href='/cgit.cgi/xen/xen/tree/?id=5ecfc3555d01658e281e1fd177677490ec57a6d9'>99e5234900bb77573a197e7030b1ce25e0b2f48e</a> /<a href='/cgit.cgi/xen/xen/tree/xen/arch/x86/domain.c?id=5ecfc3555d01658e281e1fd177677490ec57a6d9'>xen/arch/x86/domain.c</a></td></tr>
<tr><th>parent</th><td colspan='2' class='sha1'><a href='/cgit.cgi/xen/xen/commit/xen/arch/x86/domain.c?id=5ad74c5fb2ecae2a71db9b48bfcbe52637d83981'>5ad74c5fb2ecae2a71db9b48bfcbe52637d83981</a> (<a href='/cgit.cgi/xen/xen/diff/xen/arch/x86/domain.c?id=5ecfc3555d01658e281e1fd177677490ec57a6d9&amp;id2=5ad74c5fb2ecae2a71db9b48bfcbe52637d83981'>diff</a>)</td></tr><tr><th>download</th><td colspan='2' class='sha1'><a href='/cgit.cgi/xen/xen/snapshot/xen-5ecfc3555d01658e281e1fd177677490ec57a6d9.tar.gz'>xen-5ecfc3555d01658e281e1fd177677490ec57a6d9.tar.gz</a><br/><a href='/cgit.cgi/xen/xen/snapshot/xen-5ecfc3555d01658e281e1fd177677490ec57a6d9.tar.bz2'>xen-5ecfc3555d01658e281e1fd177677490ec57a6d9.tar.bz2</a><br/><a href='/cgit.cgi/xen/xen/snapshot/xen-5ecfc3555d01658e281e1fd177677490ec57a6d9.zip'>xen-5ecfc3555d01658e281e1fd177677490ec57a6d9.zip</a><br/></td></tr></table>
<div class='commit-subject'>xen: build fix for NetBSD (test -x usage).</div><div class='commit-msg'>Signed-off-by: Christoph Egger &lt;Christoph.Egger@amd.com&gt;
</div><div class='diffstat-header'><a href='/cgit.cgi/xen/xen/diff/?id=5ecfc3555d01658e281e1fd177677490ec57a6d9'>Diffstat</a> (limited to 'xen/arch/x86/domain.c')</div><table summary='diffstat' class='diffstat'></table><div class='diffstat-summary'>0 files changed, 0 insertions, 0 deletions</div><table summary='diff' class='diff'><tr><td></td></tr></table></div> <!-- class=content -->
<div class='footer'>generated by <a href='https://git.zx2c4.com/cgit/about/'>cgit v1.2.3</a> (<a href='https://git-scm.com/'>git 2.25.1</a>) at 2025-07-23 03:02:41 +0000</div>
</div> <!-- id=cgit -->
</body>
</html>
/a>
<a id='n130' href='#n130'>130</a>
<a id='n131' href='#n131'>131</a>
<a id='n132' href='#n132'>132</a>
<a id='n133' href='#n133'>133</a>
<a id='n134' href='#n134'>134</a>
<a id='n135' href='#n135'>135</a>
<a id='n136' href='#n136'>136</a>
<a id='n137' href='#n137'>137</a>
<a id='n138' href='#n138'>138</a>
<a id='n139' href='#n139'>139</a>
<a id='n140' href='#n140'>140</a>
<a id='n141' href='#n141'>141</a>
<a id='n142' href='#n142'>142</a>
<a id='n143' href='#n143'>143</a>
<a id='n144' href='#n144'>144</a>
<a id='n145' href='#n145'>145</a>
<a id='n146' href='#n146'>146</a>
<a id='n147' href='#n147'>147</a>
<a id='n148' href='#n148'>148</a>
<a id='n149' href='#n149'>149</a>
<a id='n150' href='#n150'>150</a>
<a id='n151' href='#n151'>151</a>
<a id='n152' href='#n152'>152</a>
<a id='n153' href='#n153'>153</a>
<a id='n154' href='#n154'>154</a>
<a id='n155' href='#n155'>155</a>
<a id='n156' href='#n156'>156</a>
<a id='n157' href='#n157'>157</a>
<a id='n158' href='#n158'>158</a>
<a id='n159' href='#n159'>159</a>
<a id='n160' href='#n160'>160</a>
<a id='n161' href='#n161'>161</a>
<a id='n162' href='#n162'>162</a>
<a id='n163' href='#n163'>163</a>
<a id='n164' href='#n164'>164</a>
<a id='n165' href='#n165'>165</a>
<a id='n166' href='#n166'>166</a>
<a id='n167' href='#n167'>167</a>
<a id='n168' href='#n168'>168</a>
<a id='n169' href='#n169'>169</a>
<a id='n170' href='#n170'>170</a>
<a id='n171' href='#n171'>171</a>
<a id='n172' href='#n172'>172</a>
<a id='n173' href='#n173'>173</a>
<a id='n174' href='#n174'>174</a>
<a id='n175' href='#n175'>175</a>
<a id='n176' href='#n176'>176</a>
<a id='n177' href='#n177'>177</a>
<a id='n178' href='#n178'>178</a>
<a id='n179' href='#n179'>179</a>
<a id='n180' href='#n180'>180</a>
<a id='n181' href='#n181'>181</a>
<a id='n182' href='#n182'>182</a>
<a id='n183' href='#n183'>183</a>
<a id='n184' href='#n184'>184</a>
<a id='n185' href='#n185'>185</a>
<a id='n186' href='#n186'>186</a>
<a id='n187' href='#n187'>187</a>
<a id='n188' href='#n188'>188</a>
<a id='n189' href='#n189'>189</a>
<a id='n190' href='#n190'>190</a>
<a id='n191' href='#n191'>191</a>
<a id='n192' href='#n192'>192</a>
<a id='n193' href='#n193'>193</a>
<a id='n194' href='#n194'>194</a>
<a id='n195' href='#n195'>195</a>
<a id='n196' href='#n196'>196</a>
<a id='n197' href='#n197'>197</a>
<a id='n198' href='#n198'>198</a>
<a id='n199' href='#n199'>199</a>
<a id='n200' href='#n200'>200</a>
<a id='n201' href='#n201'>201</a>
<a id='n202' href='#n202'>202</a>
<a id='n203' href='#n203'>203</a>
<a id='n204' href='#n204'>204</a>
<a id='n205' href='#n205'>205</a>
<a id='n206' href='#n206'>206</a>
<a id='n207' href='#n207'>207</a>
<a id='n208' href='#n208'>208</a>
<a id='n209' href='#n209'>209</a>
<a id='n210' href='#n210'>210</a>
<a id='n211' href='#n211'>211</a>
<a id='n212' href='#n212'>212</a>
<a id='n213' href='#n213'>213</a>
<a id='n214' href='#n214'>214</a>
<a id='n215' href='#n215'>215</a>
<a id='n216' href='#n216'>216</a>
<a id='n217' href='#n217'>217</a>
<a id='n218' href='#n218'>218</a>
<a id='n219' href='#n219'>219</a>
<a id='n220' href='#n220'>220</a>
<a id='n221' href='#n221'>221</a>
<a id='n222' href='#n222'>222</a>
<a id='n223' href='#n223'>223</a>
<a id='n224' href='#n224'>224</a>
<a id='n225' href='#n225'>225</a>
<a id='n226' href='#n226'>226</a>
<a id='n227' href='#n227'>227</a>
<a id='n228' href='#n228'>228</a>
<a id='n229' href='#n229'>229</a>
<a id='n230' href='#n230'>230</a>
<a id='n231' href='#n231'>231</a>
<a id='n232' href='#n232'>232</a>
<a id='n233' href='#n233'>233</a>
<a id='n234' href='#n234'>234</a>
<a id='n235' href='#n235'>235</a>
<a id='n236' href='#n236'>236</a>
<a id='n237' href='#n237'>237</a>
<a id='n238' href='#n238'>238</a>
<a id='n239' href='#n239'>239</a>
<a id='n240' href='#n240'>240</a>
<a id='n241' href='#n241'>241</a>
<a id='n242' href='#n242'>242</a>
<a id='n243' href='#n243'>243</a>
<a id='n244' href='#n244'>244</a>
<a id='n245' href='#n245'>245</a>
<a id='n246' href='#n246'>246</a>
<a id='n247' href='#n247'>247</a>
<a id='n248' href='#n248'>248</a>
<a id='n249' href='#n249'>249</a>
<a id='n250' href='#n250'>250</a>
<a id='n251' href='#n251'>251</a>
<a id='n252' href='#n252'>252</a>
<a id='n253' href='#n253'>253</a>
<a id='n254' href='#n254'>254</a>
<a id='n255' href='#n255'>255</a>
<a id='n256' href='#n256'>256</a>
<a id='n257' href='#n257'>257</a>
<a id='n258' href='#n258'>258</a>
<a id='n259' href='#n259'>259</a>
<a id='n260' href='#n260'>260</a>
<a id='n261' href='#n261'>261</a>
<a id='n262' href='#n262'>262</a>
<a id='n263' href='#n263'>263</a>
<a id='n264' href='#n264'>264</a>
<a id='n265' href='#n265'>265</a>
<a id='n266' href='#n266'>266</a>
<a id='n267' href='#n267'>267</a>
<a id='n268' href='#n268'>268</a>
<a id='n269' href='#n269'>269</a>
<a id='n270' href='#n270'>270</a>
<a id='n271' href='#n271'>271</a>
<a id='n272' href='#n272'>272</a>
<a id='n273' href='#n273'>273</a>
<a id='n274' href='#n274'>274</a>
<a id='n275' href='#n275'>275</a>
<a id='n276' href='#n276'>276</a>
<a id='n277' href='#n277'>277</a>
<a id='n278' href='#n278'>278</a>
<a id='n279' href='#n279'>279</a>
<a id='n280' href='#n280'>280</a>
<a id='n281' href='#n281'>281</a>
<a id='n282' href='#n282'>282</a>
<a id='n283' href='#n283'>283</a>
<a id='n284' href='#n284'>284</a>
<a id='n285' href='#n285'>285</a>
<a id='n286' href='#n286'>286</a>
<a id='n287' href='#n287'>287</a>
<a id='n288' href='#n288'>288</a>
<a id='n289' href='#n289'>289</a>
<a id='n290' href='#n290'>290</a>
<a id='n291' href='#n291'>291</a>
<a id='n292' href='#n292'>292</a>
<a id='n293' href='#n293'>293</a>
<a id='n294' href='#n294'>294</a>
<a id='n295' href='#n295'>295</a>
<a id='n296' href='#n296'>296</a>
<a id='n297' href='#n297'>297</a>
<a id='n298' href='#n298'>298</a>
<a id='n299' href='#n299'>299</a>
<a id='n300' href='#n300'>300</a>
<a id='n301' href='#n301'>301</a>
<a id='n302' href='#n302'>302</a>
<a id='n303' href='#n303'>303</a>
<a id='n304' href='#n304'>304</a>
<a id='n305' href='#n305'>305</a>
<a id='n306' href='#n306'>306</a>
<a id='n307' href='#n307'>307</a>
<a id='n308' href='#n308'>308</a>
<a id='n309' href='#n309'>309</a>
<a id='n310' href='#n310'>310</a>
<a id='n311' href='#n311'>311</a>
<a id='n312' href='#n312'>312</a>
<a id='n313' href='#n313'>313</a>
<a id='n314' href='#n314'>314</a>
<a id='n315' href='#n315'>315</a>
<a id='n316' href='#n316'>316</a>
<a id='n317' href='#n317'>317</a>
<a id='n318' href='#n318'>318</a>
<a id='n319' href='#n319'>319</a>
<a id='n320' href='#n320'>320</a>
<a id='n321' href='#n321'>321</a>
<a id='n322' href='#n322'>322</a>
<a id='n323' href='#n323'>323</a>
<a id='n324' href='#n324'>324</a>
<a id='n325' href='#n325'>325</a>
<a id='n326' href='#n326'>326</a>
<a id='n327' href='#n327'>327</a>
<a id='n328' href='#n328'>328</a>
<a id='n329' href='#n329'>329</a>
<a id='n330' href='#n330'>330</a>
<a id='n331' href='#n331'>331</a>
<a id='n332' href='#n332'>332</a>
<a id='n333' href='#n333'>333</a>
<a id='n334' href='#n334'>334</a>
<a id='n335' href='#n335'>335</a>
<a id='n336' href='#n336'>336</a>
<a id='n337' href='#n337'>337</a>
<a id='n338' href='#n338'>338</a>
<a id='n339' href='#n339'>339</a>
<a id='n340' href='#n340'>340</a>
<a id='n341' href='#n341'>341</a>
<a id='n342' href='#n342'>342</a>
<a id='n343' href='#n343'>343</a>
<a id='n344' href='#n344'>344</a>
<a id='n345' href='#n345'>345</a>
<a id='n346' href='#n346'>346</a>
<a id='n347' href='#n347'>347</a>
<a id='n348' href='#n348'>348</a>
<a id='n349' href='#n349'>349</a>
<a id='n350' href='#n350'>350</a>
<a id='n351' href='#n351'>351</a>
<a id='n352' href='#n352'>352</a>
<a id='n353' href='#n353'>353</a>
<a id='n354' href='#n354'>354</a>
<a id='n355' href='#n355'>355</a>
<a id='n356' href='#n356'>356</a>
<a id='n357' href='#n357'>357</a>
<a id='n358' href='#n358'>358</a>
<a id='n359' href='#n359'>359</a>
<a id='n360' href='#n360'>360</a>
<a id='n361' href='#n361'>361</a>
<a id='n362' href='#n362'>362</a>
<a id='n363' href='#n363'>363</a>
<a id='n364' href='#n364'>364</a>
<a id='n365' href='#n365'>365</a>
<a id='n366' href='#n366'>366</a>
<a id='n367' href='#n367'>367</a>
<a id='n368' href='#n368'>368</a>
<a id='n369' href='#n369'>369</a>
<a id='n370' href='#n370'>370</a>
<a id='n371' href='#n371'>371</a>
<a id='n372' href='#n372'>372</a>
<a id='n373' href='#n373'>373</a>
<a id='n374' href='#n374'>374</a>
<a id='n375' href='#n375'>375</a>
<a id='n376' href='#n376'>376</a>
<a id='n377' href='#n377'>377</a>
<a id='n378' href='#n378'>378</a>
<a id='n379' href='#n379'>379</a>
<a id='n380' href='#n380'>380</a>
<a id='n381' href='#n381'>381</a>
<a id='n382' href='#n382'>382</a>
<a id='n383' href='#n383'>383</a>
<a id='n384' href='#n384'>384</a>
<a id='n385' href='#n385'>385</a>
<a id='n386' href='#n386'>386</a>
<a id='n387' href='#n387'>387</a>
<a id='n388' href='#n388'>388</a>
<a id='n389' href='#n389'>389</a>
<a id='n390' href='#n390'>390</a>
<a id='n391' href='#n391'>391</a>
<a id='n392' href='#n392'>392</a>
<a id='n393' href='#n393'>393</a>
<a id='n394' href='#n394'>394</a>
<a id='n395' href='#n395'>395</a>
<a id='n396' href='#n396'>396</a>
<a id='n397' href='#n397'>397</a>
<a id='n398' href='#n398'>398</a>
<a id='n399' href='#n399'>399</a>
<a id='n400' href='#n400'>400</a>
<a id='n401' href='#n401'>401</a>
<a id='n402' href='#n402'>402</a>
<a id='n403' href='#n403'>403</a>
<a id='n404' href='#n404'>404</a>
<a id='n405' href='#n405'>405</a>
<a id='n406' href='#n406'>406</a>
<a id='n407' href='#n407'>407</a>
<a id='n408' href='#n408'>408</a>
<a id='n409' href='#n409'>409</a>
<a id='n410' href='#n410'>410</a>
<a id='n411' href='#n411'>411</a>
<a id='n412' href='#n412'>412</a>
<a id='n413' href='#n413'>413</a>
<a id='n414' href='#n414'>414</a>
<a id='n415' href='#n415'>415</a>
<a id='n416' href='#n416'>416</a>
<a id='n417' href='#n417'>417</a>
<a id='n418' href='#n418'>418</a>
<a id='n419' href='#n419'>419</a>
<a id='n420' href='#n420'>420</a>
<a id='n421' href='#n421'>421</a>
<a id='n422' href='#n422'>422</a>
<a id='n423' href='#n423'>423</a>
<a id='n424' href='#n424'>424</a>
<a id='n425' href='#n425'>425</a>
<a id='n426' href='#n426'>426</a>
<a id='n427' href='#n427'>427</a>
<a id='n428' href='#n428'>428</a>
<a id='n429' href='#n429'>429</a>
<a id='n430' href='#n430'>430</a>
<a id='n431' href='#n431'>431</a>
<a id='n432' href='#n432'>432</a>
<a id='n433' href='#n433'>433</a>
<a id='n434' href='#n434'>434</a>
<a id='n435' href='#n435'>435</a>
<a id='n436' href='#n436'>436</a>
<a id='n437' href='#n437'>437</a>
<a id='n438' href='#n438'>438</a>
<a id='n439' href='#n439'>439</a>
<a id='n440' href='#n440'>440</a>
<a id='n441' href='#n441'>441</a>
<a id='n442' href='#n442'>442</a>
<a id='n443' href='#n443'>443</a>
<a id='n444' href='#n444'>444</a>
<a id='n445' href='#n445'>445</a>
<a id='n446' href='#n446'>446</a>
<a id='n447' href='#n447'>447</a>
<a id='n448' href='#n448'>448</a>
<a id='n449' href='#n449'>449</a>
<a id='n450' href='#n450'>450</a>
<a id='n451' href='#n451'>451</a>
<a id='n452' href='#n452'>452</a>
<a id='n453' href='#n453'>453</a>
<a id='n454' href='#n454'>454</a>
<a id='n455' href='#n455'>455</a>
<a id='n456' href='#n456'>456</a>
<a id='n457' href='#n457'>457</a>
<a id='n458' href='#n458'>458</a>
<a id='n459' href='#n459'>459</a>
<a id='n460' href='#n460'>460</a>
<a id='n461' href='#n461'>461</a>
<a id='n462' href='#n462'>462</a>
<a id='n463' href='#n463'>463</a>
<a id='n464' href='#n464'>464</a>
<a id='n465' href='#n465'>465</a>
<a id='n466' href='#n466'>466</a>
<a id='n467' href='#n467'>467</a>
<a id='n468' href='#n468'>468</a>
<a id='n469' href='#n469'>469</a>
<a id='n470' href='#n470'>470</a>
<a id='n471' href='#n471'>471</a>
<a id='n472' href='#n472'>472</a>
<a id='n473' href='#n473'>473</a>
<a id='n474' href='#n474'>474</a>
<a id='n475' href='#n475'>475</a>
<a id='n476' href='#n476'>476</a>
<a id='n477' href='#n477'>477</a>
<a id='n478' href='#n478'>478</a>
<a id='n479' href='#n479'>479</a>
<a id='n480' href='#n480'>480</a>
<a id='n481' href='#n481'>481</a>
<a id='n482' href='#n482'>482</a>
<a id='n483' href='#n483'>483</a>
<a id='n484' href='#n484'>484</a>
<a id='n485' href='#n485'>485</a>
<a id='n486' href='#n486'>486</a>
<a id='n487' href='#n487'>487</a>
<a id='n488' href='#n488'>488</a>
<a id='n489' href='#n489'>489</a>
<a id='n490' href='#n490'>490</a>
<a id='n491' href='#n491'>491</a>
<a id='n492' href='#n492'>492</a>
<a id='n493' href='#n493'>493</a>
<a id='n494' href='#n494'>494</a>
<a id='n495' href='#n495'>495</a>
<a id='n496' href='#n496'>496</a>
<a id='n497' href='#n497'>497</a>
<a id='n498' href='#n498'>498</a>
<a id='n499' href='#n499'>499</a>
<a id='n500' href='#n500'>500</a>
<a id='n501' href='#n501'>501</a>
<a id='n502' href='#n502'>502</a>
<a id='n503' href='#n503'>503</a>
<a id='n504' href='#n504'>504</a>
<a id='n505' href='#n505'>505</a>
<a id='n506' href='#n506'>506</a>
<a id='n507' href='#n507'>507</a>
<a id='n508' href='#n508'>508</a>
<a id='n509' href='#n509'>509</a>
<a id='n510' href='#n510'>510</a>
<a id='n511' href='#n511'>511</a>
<a id='n512' href='#n512'>512</a>
<a id='n513' href='#n513'>513</a>
<a id='n514' href='#n514'>514</a>
<a id='n515' href='#n515'>515</a>
<a id='n516' href='#n516'>516</a>
<a id='n517' href='#n517'>517</a>
<a id='n518' href='#n518'>518</a>
<a id='n519' href='#n519'>519</a>
<a id='n520' href='#n520'>520</a>
<a id='n521' href='#n521'>521</a>
<a id='n522' href='#n522'>522</a>
<a id='n523' href='#n523'>523</a>
<a id='n524' href='#n524'>524</a>
<a id='n525' href='#n525'>525</a>
<a id='n526' href='#n526'>526</a>
<a id='n527' href='#n527'>527</a>
<a id='n528' href='#n528'>528</a>
<a id='n529' href='#n529'>529</a>
<a id='n530' href='#n530'>530</a>
<a id='n531' href='#n531'>531</a>
<a id='n532' href='#n532'>532</a>
<a id='n533' href='#n533'>533</a>
<a id='n534' href='#n534'>534</a>
<a id='n535' href='#n535'>535</a>
<a id='n536' href='#n536'>536</a>
<a id='n537' href='#n537'>537</a>
<a id='n538' href='#n538'>538</a>
<a id='n539' href='#n539'>539</a>
<a id='n540' href='#n540'>540</a>
<a id='n541' href='#n541'>541</a>
<a id='n542' href='#n542'>542</a>
<a id='n543' href='#n543'>543</a>
<a id='n544' href='#n544'>544</a>
<a id='n545' href='#n545'>545</a>
<a id='n546' href='#n546'>546</a>
<a id='n547' href='#n547'>547</a>
<a id='n548' href='#n548'>548</a>
<a id='n549' href='#n549'>549</a>
<a id='n550' href='#n550'>550</a>
<a id='n551' href='#n551'>551</a>
<a id='n552' href='#n552'>552</a>
<a id='n553' href='#n553'>553</a>
<a id='n554' href='#n554'>554</a>
<a id='n555' href='#n555'>555</a>
<a id='n556' href='#n556'>556</a>
<a id='n557' href='#n557'>557</a>
<a id='n558' href='#n558'>558</a>
<a id='n559' href='#n559'>559</a>
<a id='n560' href='#n560'>560</a>
<a id='n561' href='#n561'>561</a>
<a id='n562' href='#n562'>562</a>
<a id='n563' href='#n563'>563</a>
<a id='n564' href='#n564'>564</a>
<a id='n565' href='#n565'>565</a>
<a id='n566' href='#n566'>566</a>
<a id='n567' href='#n567'>567</a>
<a id='n568' href='#n568'>568</a>
<a id='n569' href='#n569'>569</a>
<a id='n570' href='#n570'>570</a>
<a id='n571' href='#n571'>571</a>
<a id='n572' href='#n572'>572</a>
<a id='n573' href='#n573'>573</a>
<a id='n574' href='#n574'>574</a>
<a id='n575' href='#n575'>575</a>
<a id='n576' href='#n576'>576</a>
<a id='n577' href='#n577'>577</a>
<a id='n578' href='#n578'>578</a>
<a id='n579' href='#n579'>579</a>
<a id='n580' href='#n580'>580</a>
<a id='n581' href='#n581'>581</a>
<a id='n582' href='#n582'>582</a>
<a id='n583' href='#n583'>583</a>
<a id='n584' href='#n584'>584</a>
<a id='n585' href='#n585'>585</a>
<a id='n586' href='#n586'>586</a>
<a id='n587' href='#n587'>587</a>
<a id='n588' href='#n588'>588</a>
<a id='n589' href='#n589'>589</a>
<a id='n590' href='#n590'>590</a>
<a id='n591' href='#n591'>591</a>
<a id='n592' href='#n592'>592</a>
<a id='n593' href='#n593'>593</a>
<a id='n594' href='#n594'>594</a>
<a id='n595' href='#n595'>595</a>
<a id='n596' href='#n596'>596</a>
<a id='n597' href='#n597'>597</a>
<a id='n598' href='#n598'>598</a>
<a id='n599' href='#n599'>599</a>
<a id='n600' href='#n600'>600</a>
<a id='n601' href='#n601'>601</a>
<a id='n602' href='#n602'>602</a>
<a id='n603' href='#n603'>603</a>
<a id='n604' href='#n604'>604</a>
<a id='n605' href='#n605'>605</a>
<a id='n606' href='#n606'>606</a>
<a id='n607' href='#n607'>607</a>
<a id='n608' href='#n608'>608</a>
<a id='n609' href='#n609'>609</a>
<a id='n610' href='#n610'>610</a>
<a id='n611' href='#n611'>611</a>
<a id='n612' href='#n612'>612</a>
<a id='n613' href='#n613'>613</a>
<a id='n614' href='#n614'>614</a>
<a id='n615' href='#n615'>615</a>
<a id='n616' href='#n616'>616</a>
<a id='n617' href='#n617'>617</a>
<a id='n618' href='#n618'>618</a>
<a id='n619' href='#n619'>619</a>
<a id='n620' href='#n620'>620</a>
<a id='n621' href='#n621'>621</a>
<a id='n622' href='#n622'>622</a>
<a id='n623' href='#n623'>623</a>
<a id='n624' href='#n624'>624</a>
<a id='n625' href='#n625'>625</a>
<a id='n626' href='#n626'>626</a>
<a id='n627' href='#n627'>627</a>
<a id='n628' href='#n628'>628</a>
<a id='n629' href='#n629'>629</a>
<a id='n630' href='#n630'>630</a>
<a id='n631' href='#n631'>631</a>
<a id='n632' href='#n632'>632</a>
<a id='n633' href='#n633'>633</a>
<a id='n634' href='#n634'>634</a>
<a id='n635' href='#n635'>635</a>
<a id='n636' href='#n636'>636</a>
<a id='n637' href='#n637'>637</a>
<a id='n638' href='#n638'>638</a>
<a id='n639' href='#n639'>639</a>
<a id='n640' href='#n640'>640</a>
<a id='n641' href='#n641'>641</a>
<a id='n642' href='#n642'>642</a>
<a id='n643' href='#n643'>643</a>
<a id='n644' href='#n644'>644</a>
<a id='n645' href='#n645'>645</a>
<a id='n646' href='#n646'>646</a>
<a id='n647' href='#n647'>647</a>
<a id='n648' href='#n648'>648</a>
<a id='n649' href='#n649'>649</a>
<a id='n650' href='#n650'>650</a>
<a id='n651' href='#n651'>651</a>
<a id='n652' href='#n652'>652</a>
<a id='n653' href='#n653'>653</a>
<a id='n654' href='#n654'>654</a>
<a id='n655' href='#n655'>655</a>
<a id='n656' href='#n656'>656</a>
<a id='n657' href='#n657'>657</a>
<a id='n658' href='#n658'>658</a>
<a id='n659' href='#n659'>659</a>
<a id='n660' href='#n660'>660</a>
<a id='n661' href='#n661'>661</a>
<a id='n662' href='#n662'>662</a>
<a id='n663' href='#n663'>663</a>
<a id='n664' href='#n664'>664</a>
<a id='n665' href='#n665'>665</a>
<a id='n666' href='#n666'>666</a>
<a id='n667' href='#n667'>667</a>
<a id='n668' href='#n668'>668</a>
<a id='n669' href='#n669'>669</a>
<a id='n670' href='#n670'>670</a>
<a id='n671' href='#n671'>671</a>
<a id='n672' href='#n672'>672</a>
<a id='n673' href='#n673'>673</a>
<a id='n674' href='#n674'>674</a>
<a id='n675' href='#n675'>675</a>
<a id='n676' href='#n676'>676</a>
<a id='n677' href='#n677'>677</a>
<a id='n678' href='#n678'>678</a>
<a id='n679' href='#n679'>679</a>
<a id='n680' href='#n680'>680</a>
<a id='n681' href='#n681'>681</a>
<a id='n682' href='#n682'>682</a>
<a id='n683' href='#n683'>683</a>
<a id='n684' href='#n684'>684</a>
<a id='n685' href='#n685'>685</a>
<a id='n686' href='#n686'>686</a>
<a id='n687' href='#n687'>687</a>
<a id='n688' href='#n688'>688</a>
<a id='n689' href='#n689'>689</a>
<a id='n690' href='#n690'>690</a>
<a id='n691' href='#n691'>691</a>
<a id='n692' href='#n692'>692</a>
<a id='n693' href='#n693'>693</a>
<a id='n694' href='#n694'>694</a>
<a id='n695' href='#n695'>695</a>
<a id='n696' href='#n696'>696</a>
<a id='n697' href='#n697'>697</a>
<a id='n698' href='#n698'>698</a>
<a id='n699' href='#n699'>699</a>
<a id='n700' href='#n700'>700</a>
<a id='n701' href='#n701'>701</a>
<a id='n702' href='#n702'>702</a>
<a id='n703' href='#n703'>703</a>
<a id='n704' href='#n704'>704</a>
<a id='n705' href='#n705'>705</a>
<a id='n706' href='#n706'>706</a>
<a id='n707' href='#n707'>707</a>
<a id='n708' href='#n708'>708</a>
<a id='n709' href='#n709'>709</a>
<a id='n710' href='#n710'>710</a>
<a id='n711' href='#n711'>711</a>
<a id='n712' href='#n712'>712</a>
<a id='n713' href='#n713'>713</a>
<a id='n714' href='#n714'>714</a>
<a id='n715' href='#n715'>715</a>
<a id='n716' href='#n716'>716</a>
<a id='n717' href='#n717'>717</a>
<a id='n718' href='#n718'>718</a>
<a id='n719' href='#n719'>719</a>
<a id='n720' href='#n720'>720</a>
<a id='n721' href='#n721'>721</a>
<a id='n722' href='#n722'>722</a>
<a id='n723' href='#n723'>723</a>
<a id='n724' href='#n724'>724</a>
<a id='n725' href='#n725'>725</a>
<a id='n726' href='#n726'>726</a>
<a id='n727' href='#n727'>727</a>
<a id='n728' href='#n728'>728</a>
<a id='n729' href='#n729'>729</a>
<a id='n730' href='#n730'>730</a>
<a id='n731' href='#n731'>731</a>
<a id='n732' href='#n732'>732</a>
<a id='n733' href='#n733'>733</a>
<a id='n734' href='#n734'>734</a>
<a id='n735' href='#n735'>735</a>
<a id='n736' href='#n736'>736</a>
<a id='n737' href='#n737'>737</a>
<a id='n738' href='#n738'>738</a>
<a id='n739' href='#n739'>739</a>
<a id='n740' href='#n740'>740</a>
<a id='n741' href='#n741'>741</a>
<a id='n742' href='#n742'>742</a>
<a id='n743' href='#n743'>743</a>
<a id='n744' href='#n744'>744</a>
<a id='n745' href='#n745'>745</a>
<a id='n746' href='#n746'>746</a>
<a id='n747' href='#n747'>747</a>
<a id='n748' href='#n748'>748</a>
<a id='n749' href='#n749'>749</a>
<a id='n750' href='#n750'>750</a>
<a id='n751' href='#n751'>751</a>
<a id='n752' href='#n752'>752</a>
<a id='n753' href='#n753'>753</a>
<a id='n754' href='#n754'>754</a>
<a id='n755' href='#n755'>755</a>
<a id='n756' href='#n756'>756</a>
<a id='n757' href='#n757'>757</a>
<a id='n758' href='#n758'>758</a>
<a id='n759' href='#n759'>759</a>
<a id='n760' href='#n760'>760</a>
<a id='n761' href='#n761'>761</a>
<a id='n762' href='#n762'>762</a>
<a id='n763' href='#n763'>763</a>
<a id='n764' href='#n764'>764</a>
<a id='n765' href='#n765'>765</a>
<a id='n766' href='#n766'>766</a>
<a id='n767' href='#n767'>767</a>
<a id='n768' href='#n768'>768</a>
<a id='n769' href='#n769'>769</a>
<a id='n770' href='#n770'>770</a>
<a id='n771' href='#n771'>771</a>
<a id='n772' href='#n772'>772</a>
<a id='n773' href='#n773'>773</a>
<a id='n774' href='#n774'>774</a>
<a id='n775' href='#n775'>775</a>
<a id='n776' href='#n776'>776</a>
<a id='n777' href='#n777'>777</a>
<a id='n778' href='#n778'>778</a>
<a id='n779' href='#n779'>779</a>
<a id='n780' href='#n780'>780</a>
<a id='n781' href='#n781'>781</a>
<a id='n782' href='#n782'>782</a>
<a id='n783' href='#n783'>783</a>
<a id='n784' href='#n784'>784</a>
<a id='n785' href='#n785'>785</a>
<a id='n786' href='#n786'>786</a>
<a id='n787' href='#n787'>787</a>
<a id='n788' href='#n788'>788</a>
<a id='n789' href='#n789'>789</a>
<a id='n790' href='#n790'>790</a>
<a id='n791' href='#n791'>791</a>
<a id='n792' href='#n792'>792</a>
<a id='n793' href='#n793'>793</a>
<a id='n794' href='#n794'>794</a>
<a id='n795' href='#n795'>795</a>
<a id='n796' href='#n796'>796</a>
<a id='n797' href='#n797'>797</a>
<a id='n798' href='#n798'>798</a>
<a id='n799' href='#n799'>799</a>
<a id='n800' href='#n800'>800</a>
<a id='n801' href='#n801'>801</a>
<a id='n802' href='#n802'>802</a>
<a id='n803' href='#n803'>803</a>
<a id='n804' href='#n804'>804</a>
<a id='n805' href='#n805'>805</a>
<a id='n806' href='#n806'>806</a>
<a id='n807' href='#n807'>807</a>
<a id='n808' href='#n808'>808</a>
<a id='n809' href='#n809'>809</a>
<a id='n810' href='#n810'>810</a>
<a id='n811' href='#n811'>811</a>
<a id='n812' href='#n812'>812</a>
<a id='n813' href='#n813'>813</a>
<a id='n814' href='#n814'>814</a>
<a id='n815' href='#n815'>815</a>
<a id='n816' href='#n816'>816</a>
<a id='n817' href='#n817'>817</a>
<a id='n818' href='#n818'>818</a>
<a id='n819' href='#n819'>819</a>
<a id='n820' href='#n820'>820</a>
<a id='n821' href='#n821'>821</a>
<a id='n822' href='#n822'>822</a>
<a id='n823' href='#n823'>823</a>
<a id='n824' href='#n824'>824</a>
<a id='n825' href='#n825'>825</a>
<a id='n826' href='#n826'>826</a>
<a id='n827' href='#n827'>827</a>
<a id='n828' href='#n828'>828</a>
<a id='n829' href='#n829'>829</a>
<a id='n830' href='#n830'>830</a>
<a id='n831' href='#n831'>831</a>
<a id='n832' href='#n832'>832</a>
<a id='n833' href='#n833'>833</a>
<a id='n834' href='#n834'>834</a>
<a id='n835' href='#n835'>835</a>
<a id='n836' href='#n836'>836</a>
<a id='n837' href='#n837'>837</a>
<a id='n838' href='#n838'>838</a>
<a id='n839' href='#n839'>839</a>
<a id='n840' href='#n840'>840</a>
<a id='n841' href='#n841'>841</a>
<a id='n842' href='#n842'>842</a>
<a id='n843' href='#n843'>843</a>
<a id='n844' href='#n844'>844</a>
<a id='n845' href='#n845'>845</a>
<a id='n846' href='#n846'>846</a>
<a id='n847' href='#n847'>847</a>
<a id='n848' href='#n848'>848</a>
<a id='n849' href='#n849'>849</a>
<a id='n850' href='#n850'>850</a>
<a id='n851' href='#n851'>851</a>
<a id='n852' href='#n852'>852</a>
<a id='n853' href='#n853'>853</a>
<a id='n854' href='#n854'>854</a>
<a id='n855' href='#n855'>855</a>
<a id='n856' href='#n856'>856</a>
<a id='n857' href='#n857'>857</a>
<a id='n858' href='#n858'>858</a>
<a id='n859' href='#n859'>859</a>
<a id='n860' href='#n860'>860</a>
<a id='n861' href='#n861'>861</a>
<a id='n862' href='#n862'>862</a>
<a id='n863' href='#n863'>863</a>
<a id='n864' href='#n864'>864</a>
<a id='n865' href='#n865'>865</a>
<a id='n866' href='#n866'>866</a>
<a id='n867' href='#n867'>867</a>
<a id='n868' href='#n868'>868</a>
<a id='n869' href='#n869'>869</a>
<a id='n870' href='#n870'>870</a>
<a id='n871' href='#n871'>871</a>
<a id='n872' href='#n872'>872</a>
<a id='n873' href='#n873'>873</a>
<a id='n874' href='#n874'>874</a>
<a id='n875' href='#n875'>875</a>
<a id='n876' href='#n876'>876</a>
<a id='n877' href='#n877'>877</a>
<a id='n878' href='#n878'>878</a>
<a id='n879' href='#n879'>879</a>
<a id='n880' href='#n880'>880</a>
<a id='n881' href='#n881'>881</a>
<a id='n882' href='#n882'>882</a>
<a id='n883' href='#n883'>883</a>
<a id='n884' href='#n884'>884</a>
<a id='n885' href='#n885'>885</a>
<a id='n886' href='#n886'>886</a>
<a id='n887' href='#n887'>887</a>
<a id='n888' href='#n888'>888</a>
<a id='n889' href='#n889'>889</a>
<a id='n890' href='#n890'>890</a>
<a id='n891' href='#n891'>891</a>
<a id='n892' href='#n892'>892</a>
<a id='n893' href='#n893'>893</a>
<a id='n894' href='#n894'>894</a>
<a id='n895' href='#n895'>895</a>
<a id='n896' href='#n896'>896</a>
<a id='n897' href='#n897'>897</a>
<a id='n898' href='#n898'>898</a>
<a id='n899' href='#n899'>899</a>
<a id='n900' href='#n900'>900</a>
<a id='n901' href='#n901'>901</a>
<a id='n902' href='#n902'>902</a>
<a id='n903' href='#n903'>903</a>
<a id='n904' href='#n904'>904</a>
<a id='n905' href='#n905'>905</a>
<a id='n906' href='#n906'>906</a>
<a id='n907' href='#n907'>907</a>
<a id='n908' href='#n908'>908</a>
<a id='n909' href='#n909'>909</a>
<a id='n910' href='#n910'>910</a>
<a id='n911' href='#n911'>911</a>
<a id='n912' href='#n912'>912</a>
<a id='n913' href='#n913'>913</a>
<a id='n914' href='#n914'>914</a>
<a id='n915' href='#n915'>915</a>
<a id='n916' href='#n916'>916</a>
<a id='n917' href='#n917'>917</a>
<a id='n918' href='#n918'>918</a>
<a id='n919' href='#n919'>919</a>
<a id='n920' href='#n920'>920</a>
<a id='n921' href='#n921'>921</a>
<a id='n922' href='#n922'>922</a>
<a id='n923' href='#n923'>923</a>
<a id='n924' href='#n924'>924</a>
<a id='n925' href='#n925'>925</a>
<a id='n926' href='#n926'>926</a>
<a id='n927' href='#n927'>927</a>
<a id='n928' href='#n928'>928</a>
<a id='n929' href='#n929'>929</a>
<a id='n930' href='#n930'>930</a>
<a id='n931' href='#n931'>931</a>
<a id='n932' href='#n932'>932</a>
<a id='n933' href='#n933'>933</a>
<a id='n934' href='#n934'>934</a>
<a id='n935' href='#n935'>935</a>
<a id='n936' href='#n936'>936</a>
<a id='n937' href='#n937'>937</a>
<a id='n938' href='#n938'>938</a>
<a id='n939' href='#n939'>939</a>
<a id='n940' href='#n940'>940</a>
<a id='n941' href='#n941'>941</a>
<a id='n942' href='#n942'>942</a>
<a id='n943' href='#n943'>943</a>
<a id='n944' href='#n944'>944</a>
<a id='n945' href='#n945'>945</a>
<a id='n946' href='#n946'>946</a>
<a id='n947' href='#n947'>947</a>
<a id='n948' href='#n948'>948</a>
<a id='n949' href='#n949'>949</a>
<a id='n950' href='#n950'>950</a>
<a id='n951' href='#n951'>951</a>
<a id='n952' href='#n952'>952</a>
<a id='n953' href='#n953'>953</a>
<a id='n954' href='#n954'>954</a>
<a id='n955' href='#n955'>955</a>
<a id='n956' href='#n956'>956</a>
</pre></td>
<td class='lines'><pre><code><style>pre { line-height: 125%; margin: 0; }
td.linenos pre { color: #000000; background-color: #f0f0f0; padding: 0 5px 0 5px; }
span.linenos { color: #000000; background-color: #f0f0f0; padding: 0 5px 0 5px; }
td.linenos pre.special { color: #000000; background-color: #ffffc0; padding: 0 5px 0 5px; }
span.linenos.special { color: #000000; background-color: #ffffc0; padding: 0 5px 0 5px; }
.highlight .hll { background-color: #ffffcc }
.highlight { background: #ffffff; }
.highlight .c { color: #888888 } /* Comment */
.highlight .err { color: #a61717; background-color: #e3d2d2 } /* Error */
.highlight .k { color: #008800; font-weight: bold } /* Keyword */
.highlight .ch { color: #888888 } /* Comment.Hashbang */
.highlight .cm { color: #888888 } /* Comment.Multiline */
.highlight .cp { color: #cc0000; font-weight: bold } /* Comment.Preproc */
.highlight .cpf { color: #888888 } /* Comment.PreprocFile */
.highlight .c1 { color: #888888 } /* Comment.Single */
.highlight .cs { color: #cc0000; font-weight: bold; background-color: #fff0f0 } /* Comment.Special */
.highlight .gd { color: #000000; background-color: #ffdddd } /* Generic.Deleted */
.highlight .ge { font-style: italic } /* Generic.Emph */
.highlight .gr { color: #aa0000 } /* Generic.Error */
.highlight .gh { color: #333333 } /* Generic.Heading */
.highlight .gi { color: #000000; background-color: #ddffdd } /* Generic.Inserted */
.highlight .go { color: #888888 } /* Generic.Output */
.highlight .gp { color: #555555 } /* Generic.Prompt */
.highlight .gs { font-weight: bold } /* Generic.Strong */
.highlight .gu { color: #666666 } /* Generic.Subheading */
.highlight .gt { color: #aa0000 } /* Generic.Traceback */
.highlight .kc { color: #008800; font-weight: bold } /* Keyword.Constant */
.highlight .kd { color: #008800; font-weight: bold } /* Keyword.Declaration */
.highlight .kn { color: #008800; font-weight: bold } /* Keyword.Namespace */
.highlight .kp { color: #008800 } /* Keyword.Pseudo */
.highlight .kr { color: #008800; font-weight: bold } /* Keyword.Reserved */
.highlight .kt { color: #888888; font-weight: bold } /* Keyword.Type */
.highlight .m { color: #0000DD; font-weight: bold } /* Literal.Number */
.highlight .s { color: #dd2200; background-color: #fff0f0 } /* Literal.String */
.highlight .na { color: #336699 } /* Name.Attribute */
.highlight .nb { color: #003388 } /* Name.Builtin */
.highlight .nc { color: #bb0066; font-weight: bold } /* Name.Class */
.highlight .no { color: #003366; font-weight: bold } /* Name.Constant */
.highlight .nd { color: #555555 } /* Name.Decorator */
.highlight .ne { color: #bb0066; font-weight: bold } /* Name.Exception */
.highlight .nf { color: #0066bb; font-weight: bold } /* Name.Function */
.highlight .nl { color: #336699; font-style: italic } /* Name.Label */
.highlight .nn { color: #bb0066; font-weight: bold } /* Name.Namespace */
.highlight .py { color: #336699; font-weight: bold } /* Name.Property */
.highlight .nt { color: #bb0066; font-weight: bold } /* Name.Tag */
.highlight .nv { color: #336699 } /* Name.Variable */
.highlight .ow { color: #008800 } /* Operator.Word */
.highlight .w { color: #bbbbbb } /* Text.Whitespace */
.highlight .mb { color: #0000DD; font-weight: bold } /* Literal.Number.Bin */
.highlight .mf { color: #0000DD; font-weight: bold } /* Literal.Number.Float */
.highlight .mh { color: #0000DD; font-weight: bold } /* Literal.Number.Hex */
.highlight .mi { color: #0000DD; font-weight: bold } /* Literal.Number.Integer */
.highlight .mo { color: #0000DD; font-weight: bold } /* Literal.Number.Oct */
.highlight .sa { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Affix */
.highlight .sb { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Backtick */
.highlight .sc { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Char */
.highlight .dl { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Delimiter */
.highlight .sd { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Doc */
.highlight .s2 { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Double */
.highlight .se { color: #0044dd; background-color: #fff0f0 } /* Literal.String.Escape */
.highlight .sh { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Heredoc */
.highlight .si { color: #3333bb; background-color: #fff0f0 } /* Literal.String.Interpol */
.highlight .sx { color: #22bb22; background-color: #f0fff0 } /* Literal.String.Other */
.highlight .sr { color: #008800; background-color: #fff0ff } /* Literal.String.Regex */
.highlight .s1 { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Single */
.highlight .ss { color: #aa6600; background-color: #fff0f0 } /* Literal.String.Symbol */
.highlight .bp { color: #003388 } /* Name.Builtin.Pseudo */
.highlight .fm { color: #0066bb; font-weight: bold } /* Name.Function.Magic */
.highlight .vc { color: #336699 } /* Name.Variable.Class */
.highlight .vg { color: #dd7700 } /* Name.Variable.Global */
.highlight .vi { color: #3333bb } /* Name.Variable.Instance */
.highlight .vm { color: #336699 } /* Name.Variable.Magic */
.highlight .il { color: #0000DD; font-weight: bold } /* Literal.Number.Integer.Long */</style><div class="highlight"><pre><span></span><span class="k">\section</span><span class="nb">{</span>Introduction to Yosys<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>
<span class="k">\sectionpage</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\iffalse</span>
<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Representations of (digital) Circuits<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
	<span class="k">\item</span> Graphical
		<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
			<span class="k">\item</span> <span class="k">\alert</span>&lt;1&gt;<span class="nb">{</span>Schematic Diagram<span class="nb">}</span>
			<span class="k">\item</span> <span class="k">\alert</span>&lt;2&gt;<span class="nb">{</span>Physical Layout<span class="nb">}</span>
		<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>
	<span class="k">\bigskip</span>
	<span class="k">\item</span> Non-graphical
		<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
			<span class="k">\item</span> <span class="k">\alert</span>&lt;3&gt;<span class="nb">{</span>Netlists<span class="nb">}</span>
			<span class="k">\item</span> <span class="k">\alert</span>&lt;4&gt;<span class="nb">{</span>Hardware Description Languages (HDLs)<span class="nb">}</span>
		<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>block<span class="nb">}{</span>Definition:
<span class="k">\only</span>&lt;1&gt;<span class="nb">{</span>Schematic Diagram<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;2&gt;<span class="nb">{</span>Physical Layout<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;3&gt;<span class="nb">{</span>Netlists<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;4&gt;<span class="nb">{</span>Hardware Description Languages (HDLs)<span class="nb">}}</span>
<span class="k">\only</span>&lt;1&gt;<span class="nb">{</span>
	Graphical representation of the circuit topology. Circuit elements
	are represented by symbols and electrical connections by lines. The geometric
	layout is for readability only.
<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;2&gt;<span class="nb">{</span>
	The actual physical geometry of the device (PCB or ASIC manufacturing masks).
	This is the final product of the design process.
<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;3&gt;<span class="nb">{</span>
	A list of circuit elements and a list of connections. This is the raw circuit
	topology.
<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;4&gt;<span class="nb">{</span>
	Computer languages (like programming languages) that can be used to describe
	circuits. HDLs are much more powerful in describing huge circuits than
	schematic diagrams.
<span class="nb">}</span><span class="c">%</span>
<span class="k">\end</span><span class="nb">{</span>block<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>
<span class="k">\fi</span>

<span class="k">\subsection</span><span class="nb">{</span>Levels of Abstraction for Digital Circuits<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
	<span class="k">\item</span> <span class="k">\alert</span>&lt;1&gt;<span class="nb">{</span>System Level<span class="nb">}</span>
	<span class="k">\item</span> <span class="k">\alert</span>&lt;2&gt;<span class="nb">{</span>High Level<span class="nb">}</span>
	<span class="k">\item</span> <span class="k">\alert</span>&lt;3&gt;<span class="nb">{</span>Behavioral Level<span class="nb">}</span>
	<span class="k">\item</span> <span class="k">\alert</span>&lt;4&gt;<span class="nb">{</span>Register-Transfer Level (RTL)<span class="nb">}</span>
	<span class="k">\item</span> <span class="k">\alert</span>&lt;5&gt;<span class="nb">{</span>Logical Gate Level<span class="nb">}</span>
	<span class="k">\item</span> <span class="k">\alert</span>&lt;6&gt;<span class="nb">{</span>Physical Gate Level<span class="nb">}</span>
	<span class="k">\item</span> <span class="k">\alert</span>&lt;7&gt;<span class="nb">{</span>Switch Level<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>block<span class="nb">}{</span>Definition:
<span class="k">\only</span>&lt;1&gt;<span class="nb">{</span>System Level<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;2&gt;<span class="nb">{</span>High Level<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;3&gt;<span class="nb">{</span>Behavioral Level<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;4&gt;<span class="nb">{</span>Register-Transfer Level (RTL)<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;5&gt;<span class="nb">{</span>Logical Gate Level<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;6&gt;<span class="nb">{</span>Physical Gate Level<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;7&gt;<span class="nb">{</span>Switch Level<span class="nb">}}</span>
<span class="k">\only</span>&lt;1&gt;<span class="nb">{</span>
	Overall view of the circuit. E.g. block-diagrams or instruction-set architecture descriptions.
<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;2&gt;<span class="nb">{</span>
	Functional implementation of circuit in high-level programming language (C, C++, SystemC, Matlab, Python, etc.).
<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;3&gt;<span class="nb">{</span>
	Cycle-accurate description of circuit in hardware description language (Verilog, VHDL, etc.).
<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;4&gt;<span class="nb">{</span>
	List of registers (flip-flops) and logic functions that calculate the next state from the previous one. Usually
	a netlist utilizing high-level cells such as adders, multipliers, multiplexer, etc.
<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;5&gt;<span class="nb">{</span>
	Netlist of single-bit registers and basic logic gates (such as AND, OR,
	NOT, etc.). Popular form: And-Inverter-Graphs (AIGs) with pairs of primary
	inputs and outputs for each register bit.
<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;6&gt;<span class="nb">{</span>
	Netlist of cells that actually are available on the target architecture
	(such as CMOS gates in an ASIC or LUTs in an FPGA). Optimized for
	area, power, and/or speed (static timing or number of logic levels).
<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;7&gt;<span class="nb">{</span>
	Netlist of individual transistors.
<span class="nb">}</span><span class="c">%</span>
<span class="k">\end</span><span class="nb">{</span>block<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Digital Circuit Synthesis<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">}</span>
	Synthesis Tools (such as Yosys) can transform HDL code to circuits:

	<span class="k">\bigskip</span>
	<span class="k">\begin</span><span class="nb">{</span>center<span class="nb">}</span>
	<span class="k">\begin</span><span class="nb">{</span>tikzpicture<span class="nb">}</span>[scale=0.8, every node/.style=<span class="nb">{</span>transform shape<span class="nb">}</span>]
			<span class="k">\tikzstyle</span><span class="nb">{</span>lvl<span class="nb">}</span> = [draw, fill=MyBlue, rectangle, minimum height=2em, minimum width=15em]
			<span class="k">\node</span><span class="na">[lvl]</span> (sys) <span class="nb">{</span>System Level<span class="nb">}</span>;
			<span class="k">\node</span><span class="na">[lvl]</span> (hl) [below of=sys] <span class="nb">{</span>High Level<span class="nb">}</span>;
			<span class="k">\node</span><span class="na">[lvl]</span> (beh) [below of=hl] <span class="nb">{</span>Behavioral Level<span class="nb">}</span>;
			<span class="k">\node</span><span class="na">[lvl]</span> (rtl) [below of=beh] <span class="nb">{</span>Register-Transfer Level (RTL)<span class="nb">}</span>;
			<span class="k">\node</span><span class="na">[lvl]</span> (lg) [below of=rtl] <span class="nb">{</span>Logical Gate Level<span class="nb">}</span>;
			<span class="k">\node</span><span class="na">[lvl]</span> (pg) [below of=lg] <span class="nb">{</span>Physical Gate Level<span class="nb">}</span>;
			<span class="k">\node</span><span class="na">[lvl]</span> (sw) [below of=pg] <span class="nb">{</span>Switch Level<span class="nb">}</span>;

			<span class="k">\draw</span><span class="na">[dotted]</span> (sys.east)  -- ++(1,0) coordinate (sysx);
			<span class="k">\draw</span><span class="na">[dotted]</span> (hl.east)  -- ++(1,0) coordinate (hlx);
			<span class="k">\draw</span><span class="na">[dotted]</span> (beh.east) -- ++(1,0) coordinate (behx);
			<span class="k">\draw</span><span class="na">[dotted]</span> (rtl.east) -- ++(1,0) coordinate (rtlx);
			<span class="k">\draw</span><span class="na">[dotted]</span> (lg.east)  -- ++(1,0) coordinate (lgx);
			<span class="k">\draw</span><span class="na">[dotted]</span> (pg.east)  -- ++(1,0) coordinate (pgx);
			<span class="k">\draw</span><span class="na">[dotted]</span> (sw.east)  -- ++(1,0) coordinate (swx);

			<span class="k">\draw</span><span class="na">[gray,|-&gt;]</span> (sysx) -- node[right] <span class="nb">{</span>System Design<span class="nb">}</span> (hlx);
			<span class="k">\draw</span><span class="na">[|-&gt;|]</span> (hlx) -- node[right] <span class="nb">{</span>High Level Synthesis (HLS)<span class="nb">}</span> (behx);
			<span class="k">\draw</span><span class="na">[-&gt;|]</span> (behx) -- node[right] <span class="nb">{</span>Behavioral Synthesis<span class="nb">}</span> (rtlx);
			<span class="k">\draw</span><span class="na">[-&gt;|]</span> (rtlx) -- node[right] <span class="nb">{</span>RTL Synthesis<span class="nb">}</span> (lgx);
			<span class="k">\draw</span><span class="na">[-&gt;|]</span> (lgx) -- node[right] <span class="nb">{</span>Logic Synthesis<span class="nb">}</span> (pgx);
			<span class="k">\draw</span><span class="na">[gray,-&gt;|]</span> (pgx) -- node[right] <span class="nb">{</span>Cell Library<span class="nb">}</span> (swx);

			<span class="k">\draw</span><span class="na">[dotted]</span> (behx) -- ++(4,0) coordinate (a);
			<span class="k">\draw</span><span class="na">[dotted]</span> (pgx) -- ++(4,0) coordinate (b);
			<span class="k">\draw</span><span class="na">[|-&gt;|]</span> (a) -- node[right] <span class="nb">{</span>Yosys<span class="nb">}</span> (b);
	<span class="k">\end</span><span class="nb">{</span>tikzpicture<span class="nb">}</span>
	<span class="k">\end</span><span class="nb">{</span>center<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>What Yosys can and can&#39;t do<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">}</span>

Things Yosys can do:
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Read and process (most of) modern Verilog-2005 code.
<span class="k">\item</span> Perform all kinds of operations on netlist (RTL, Logic, Gate).
<span class="k">\item</span> Perform logic optimizations and gate mapping with ABC<span class="k">\footnote</span><span class="na">[frame]</span><span class="nb">{</span><span class="k">\url</span><span class="nb">{</span>http://www.eecs.berkeley.edu/~alanmi/abc/<span class="nb">}}</span>.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

<span class="k">\bigskip</span>
Things Yosys can&#39;t do:
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Process high-level languages such as C/C++/SystemC.
<span class="k">\item</span> Create physical layouts (place<span class="k">\&amp;</span>route).
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

<span class="k">\bigskip</span>
A typical flow combines Yosys with with a low-level implementation tool, such
as Qflow<span class="k">\footnote</span><span class="na">[frame]</span><span class="nb">{</span><span class="k">\url</span><span class="nb">{</span>http://opencircuitdesign.com/qflow/<span class="nb">}}</span> for ASIC designs.

<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Yosys Data- and Control-Flow<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">}</span>
	A (usually short) synthesis script controls Yosys.

	This scripts contain three types of commands:
	<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
	<span class="k">\item</span> <span class="nb">{</span><span class="k">\bf</span> Frontends<span class="nb">}</span>, that read input files (usually Verilog).
	<span class="k">\item</span> <span class="nb">{</span><span class="k">\bf</span> Passes<span class="nb">}</span>, that perform transformations on the design in memory.
	<span class="k">\item</span> <span class="nb">{</span><span class="k">\bf</span> Backends<span class="nb">}</span>, that write the design in memory to a file (various formats are available: Verilog, BLIF, EDIF, SPICE, BTOR, <span class="k">\dots</span>).
	<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

	<span class="k">\bigskip</span>
	<span class="k">\begin</span><span class="nb">{</span>center<span class="nb">}</span>
	<span class="k">\begin</span><span class="nb">{</span>tikzpicture<span class="nb">}</span>[scale=0.6, every node/.style=<span class="nb">{</span>transform shape<span class="nb">}</span>]
		<span class="k">\path</span> (-1.5,3) coordinate (cursor);
		<span class="k">\draw</span><span class="na">[-latex]</span> (<span class="s">$</span><span class="nb"> </span><span class="o">(</span><span class="nb">cursor</span><span class="o">)</span><span class="nb"> </span><span class="o">+</span><span class="nb"> </span><span class="o">(</span><span class="m">0</span><span class="nb">,</span><span class="o">-</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="o">)</span><span class="nb"> </span><span class="s">$</span>) -- ++(1,0);
		<span class="k">\draw</span><span class="na">[fill=orange!10]</span> (<span class="s">$</span><span class="nb"> </span><span class="o">(</span><span class="nb">cursor</span><span class="o">)</span><span class="nb"> </span><span class="o">+</span><span class="nb"> </span><span class="o">(</span><span class="m">1</span><span class="nb">,</span><span class="o">-</span><span class="m">3</span><span class="o">)</span><span class="nb"> </span><span class="s">$</span>) rectangle node[rotate=90] <span class="nb">{</span>Frontend<span class="nb">}</span> ++(1,3) coordinate (cursor);
		<span class="k">\draw</span><span class="na">[-latex]</span> (<span class="s">$</span><span class="nb"> </span><span class="o">(</span><span class="nb">cursor</span><span class="o">)</span><span class="nb"> </span><span class="o">+</span><span class="nb"> </span><span class="o">(</span><span class="m">0</span><span class="nb">,</span><span class="o">-</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="o">)</span><span class="nb"> </span><span class="s">$</span>) -- ++(1,0);
		<span class="k">\draw</span><span class="na">[fill=green!10]</span> (<span class="s">$</span><span class="nb"> </span><span class="o">(</span><span class="nb">cursor</span><span class="o">)</span><span class="nb"> </span><span class="o">+</span><span class="nb"> </span><span class="o">(</span><span class="m">1</span><span class="nb">,</span><span class="o">-</span><span class="m">3</span><span class="o">)</span><span class="nb"> </span><span class="s">$</span>) rectangle node[rotate=90] <span class="nb">{</span>Pass<span class="nb">}</span> ++(1,3) coordinate (cursor);
		<span class="k">\draw</span><span class="na">[-latex]</span> (<span class="s">$</span><span class="nb"> </span><span class="o">(</span><span class="nb">cursor</span><span class="o">)</span><span class="nb"> </span><span class="o">+</span><span class="nb"> </span><span class="o">(</span><span class="m">0</span><span class="nb">,</span><span class="o">-</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="o">)</span><span class="nb"> </span><span class="s">$</span>) -- ++(1,0);
		<span class="k">\draw</span><span class="na">[fill=green!10]</span> (<span class="s">$</span><span class="nb"> </span><span class="o">(</span><span class="nb">cursor</span><span class="o">)</span><span class="nb"> </span><span class="o">+</span><span class="nb"> </span><span class="o">(</span><span class="m">1</span><span class="nb">,</span><span class="o">-</span><span class="m">3</span><span class="o">)</span><span class="nb"> </span><span class="s">$</span>) rectangle node[rotate=90] <span class="nb">{</span>Pass<span class="nb">}</span> ++(1,3) coordinate (cursor);
		<span class="k">\draw</span><span class="na">[-latex]</span> (<span class="s">$</span><span class="nb"> </span><span class="o">(</span><span class="nb">cursor</span><span class="o">)</span><span class="nb"> </span><span class="o">+</span><span class="nb"> </span><span class="o">(</span><span class="m">0</span><span class="nb">,</span><span class="o">-</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="o">)</span><span class="nb"> </span><span class="s">$</span>) -- ++(1,0);
		<span class="k">\draw</span><span class="na">[fill=green!10]</span> (<span class="s">$</span><span class="nb"> </span><span class="o">(</span><span class="nb">cursor</span><span class="o">)</span><span class="nb"> </span><span class="o">+</span><span class="nb"> </span><span class="o">(</span><span class="m">1</span><span class="nb">,</span><span class="o">-</span><span class="m">3</span><span class="o">)</span><span class="nb"> </span><span class="s">$</span>) rectangle node[rotate=90] <span class="nb">{</span>Pass<span class="nb">}</span> ++(1,3) coordinate (cursor);
		<span class="k">\draw</span><span class="na">[-latex]</span> (<span class="s">$</span><span class="nb"> </span><span class="o">(</span><span class="nb">cursor</span><span class="o">)</span><span class="nb"> </span><span class="o">+</span><span class="nb"> </span><span class="o">(</span><span class="m">0</span><span class="nb">,</span><span class="o">-</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="o">)</span><span class="nb"> </span><span class="s">$</span>) -- ++(1,0);
		<span class="k">\draw</span><span class="na">[fill=orange!10]</span> (<span class="s">$</span><span class="nb"> </span><span class="o">(</span><span class="nb">cursor</span><span class="o">)</span><span class="nb"> </span><span class="o">+</span><span class="nb"> </span><span class="o">(</span><span class="m">1</span><span class="nb">,</span><span class="o">-</span><span class="m">3</span><span class="o">)</span><span class="nb"> </span><span class="s">$</span>) rectangle node[rotate=90] <span class="nb">{</span>Backend<span class="nb">}</span> ++(1,3) coordinate (cursor);
		<span class="k">\draw</span><span class="na">[-latex]</span> (<span class="s">$</span><span class="nb"> </span><span class="o">(</span><span class="nb">cursor</span><span class="o">)</span><span class="nb"> </span><span class="o">+</span><span class="nb"> </span><span class="o">(</span><span class="m">0</span><span class="nb">,</span><span class="o">-</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="o">)</span><span class="nb"> </span><span class="s">$</span>) -- ++(1,0);

		<span class="k">\path</span> (-3,-0.5) coordinate (cursor);
		<span class="k">\draw</span> (cursor) -- node[below] <span class="nb">{</span>HDL<span class="nb">}</span> ++(3,0) coordinate (cursor);
		<span class="k">\draw</span><span class="na">[|-|]</span> (cursor) -- node[below] <span class="nb">{</span>Internal Format (RTLIL)<span class="nb">}</span> ++(8,0) coordinate (cursor);
		<span class="k">\draw</span> (cursor) -- node[below] <span class="nb">{</span>Netlist<span class="nb">}</span> ++(3,0);

		<span class="k">\path</span> (-3,3.5) coordinate (cursor);
		<span class="k">\draw</span><span class="na">[-]</span> (cursor) -- node[above] <span class="nb">{</span>High-Level<span class="nb">}</span> ++(3,0) coordinate (cursor);
		<span class="k">\draw</span><span class="na">[-]</span> (cursor) -- ++(8,0) coordinate (cursor);
		<span class="k">\draw</span><span class="na">[-&gt;]</span> (cursor) -- node[above] <span class="nb">{</span>Low-Level<span class="nb">}</span> ++(3,0);
	<span class="k">\end</span><span class="nb">{</span>tikzpicture<span class="nb">}</span>
	<span class="k">\end</span><span class="nb">{</span>center<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Program Components and Data Formats<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">}</span>
	<span class="k">\begin</span><span class="nb">{</span>center<span class="nb">}</span>
	<span class="k">\begin</span><span class="nb">{</span>tikzpicture<span class="nb">}</span>[scale=0.6, every node/.style=<span class="nb">{</span>transform shape<span class="nb">}</span>]
		<span class="k">\tikzstyle</span><span class="nb">{</span>process<span class="nb">}</span> = [draw, fill=green!10, rectangle, minimum height=3em, minimum width=10em, node distance=15em]
		<span class="k">\tikzstyle</span><span class="nb">{</span>data<span class="nb">}</span> = [draw, fill=blue!10, ellipse, minimum height=3em, minimum width=7em, node distance=15em]
		<span class="k">\node</span><span class="na">[process]</span> (vlog) <span class="nb">{</span>Verilog Frontend<span class="nb">}</span>;
		<span class="k">\node</span><span class="na">[process, dashed, fill=green!5]</span> (vhdl) [right of=vlog] <span class="nb">{</span>VHDL Frontend<span class="nb">}</span>;
		<span class="k">\node</span><span class="na">[process]</span> (ilang) [right of=vhdl] <span class="nb">{</span>Other Frontends<span class="nb">}</span>;
		<span class="k">\node</span><span class="na">[data]</span> (ast) [below of=vlog, node distance=5em, xshift=7.5em] <span class="nb">{</span>AST<span class="nb">}</span>;
		<span class="k">\node</span><span class="na">[process]</span> (astfe) [below of=ast, node distance=5em] <span class="nb">{</span>AST Frontend<span class="nb">}</span>;
		<span class="k">\node</span><span class="na">[data]</span> (rtlil) [below of=astfe, node distance=5em, xshift=7.5em] <span class="nb">{</span>RTLIL<span class="nb">}</span>;
		<span class="k">\node</span><span class="na">[process]</span> (pass) [right of=rtlil, node distance=5em, xshift=7.5em] <span class="nb">{</span>Passes<span class="nb">}</span>;
		<span class="k">\node</span><span class="na">[process]</span> (vlbe) [below of=rtlil, node distance=7em, xshift=-13em] <span class="nb">{</span>Verilog Backend<span class="nb">}</span>;
		<span class="k">\node</span><span class="na">[process]</span> (ilangbe) [below of=rtlil, node distance=7em, xshift=0em] <span class="nb">{</span>ILANG Backend<span class="nb">}</span>;
		<span class="k">\node</span><span class="na">[process, fill=green!5]</span> (otherbe) [below of=rtlil, node distance=7em, xshift=+13em] <span class="nb">{</span>Other Backends<span class="nb">}</span>;

		<span class="k">\draw</span><span class="na">[-latex]</span> (vlog) -- (ast);
		<span class="k">\draw</span><span class="na">[-latex]</span> (vhdl) -- (ast);
		<span class="k">\draw</span><span class="na">[-latex]</span> (ast) -- (astfe);
		<span class="k">\draw</span><span class="na">[-latex]</span> (astfe) -- (rtlil);
		<span class="k">\draw</span><span class="na">[-latex]</span> (ilang) -- (rtlil);
		<span class="k">\draw</span><span class="na">[latex-latex]</span> (rtlil) -- (pass);
		<span class="k">\draw</span><span class="na">[-latex]</span> (rtlil) -- (vlbe);
		<span class="k">\draw</span><span class="na">[-latex]</span> (rtlil) -- (ilangbe);
		<span class="k">\draw</span><span class="na">[-latex]</span> (rtlil) -- (otherbe);
	<span class="k">\end</span><span class="nb">{</span>tikzpicture<span class="nb">}</span>
	<span class="k">\end</span><span class="nb">{</span>center<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Example Project<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">}</span>
The following slides cover an example project. This project contains three files:
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> A simple ASIC synthesis script
<span class="k">\item</span> A digital design written in Verilog
<span class="k">\item</span> A simple CMOS cell library
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\vfill</span>
Direct link to the files: <span class="k">\\</span> <span class="k">\footnotesize</span>
<span class="k">\url</span><span class="nb">{</span>https://github.com/cliffordwolf/yosys/tree/master/manual/PRESENTATION<span class="nb">_</span>Intro<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">{}</span> -- Synthesis Script<span class="nb">}</span>

<span class="k">\setbeamercolor</span><span class="nb">{</span>alerted text<span class="nb">}{</span>fg=white,bg=red<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>minipage<span class="nb">}</span>[t]<span class="nb">{</span>6cm<span class="nb">}</span>
<span class="k">\tt\scriptsize</span>
<span class="nb">{</span><span class="k">\color</span><span class="nb">{</span>YosysGreen<span class="nb">}</span><span class="k">\#</span> read design<span class="nb">}</span><span class="k">\\</span>
<span class="k">\boxalert</span>&lt;1&gt;<span class="nb">{</span>read<span class="k">\_</span>verilog counter.v<span class="nb">}</span><span class="k">\\</span>
<span class="k">\boxalert</span>&lt;2&gt;<span class="nb">{</span>hierarchy -check -top counter<span class="nb">}</span>

<span class="k">\medskip</span>
<span class="nb">{</span><span class="k">\color</span><span class="nb">{</span>YosysGreen<span class="nb">}</span><span class="k">\#</span> the high-level stuff<span class="nb">}</span><span class="k">\\</span>
<span class="k">\boxalert</span>&lt;3&gt;<span class="nb">{</span>proc<span class="nb">}</span>; <span class="k">\boxalert</span>&lt;4&gt;<span class="nb">{</span>opt<span class="nb">}</span>; <span class="k">\boxalert</span>&lt;5&gt;<span class="nb">{</span>fsm<span class="nb">}</span>; <span class="k">\boxalert</span>&lt;6&gt;<span class="nb">{</span>opt<span class="nb">}</span>; <span class="k">\boxalert</span>&lt;7&gt;<span class="nb">{</span>memory<span class="nb">}</span>; <span class="k">\boxalert</span>&lt;8&gt;<span class="nb">{</span>opt<span class="nb">}</span>

<span class="k">\medskip</span>
<span class="nb">{</span><span class="k">\color</span><span class="nb">{</span>YosysGreen<span class="nb">}</span><span class="k">\#</span> mapping to internal cell library<span class="nb">}</span><span class="k">\\</span>
<span class="k">\boxalert</span>&lt;9&gt;<span class="nb">{</span>techmap<span class="nb">}</span>; <span class="k">\boxalert</span>&lt;10&gt;<span class="nb">{</span>opt<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>minipage<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>minipage<span class="nb">}</span>[t]<span class="nb">{</span>5cm<span class="nb">}</span>
<span class="k">\tt\scriptsize</span>
<span class="nb">{</span><span class="k">\color</span><span class="nb">{</span>YosysGreen<span class="nb">}</span><span class="k">\#</span> mapping flip-flops to mycells.lib<span class="nb">}</span><span class="k">\\</span>
<span class="k">\boxalert</span>&lt;11&gt;<span class="nb">{</span>dfflibmap -liberty mycells.lib<span class="nb">}</span>

<span class="k">\medskip</span>
<span class="nb">{</span><span class="k">\color</span><span class="nb">{</span>YosysGreen<span class="nb">}</span><span class="k">\#</span> mapping logic to mycells.lib<span class="nb">}</span><span class="k">\\</span>
<span class="k">\boxalert</span>&lt;12&gt;<span class="nb">{</span>abc -liberty mycells.lib<span class="nb">}</span>

<span class="k">\medskip</span>
<span class="nb">{</span><span class="k">\color</span><span class="nb">{</span>YosysGreen<span class="nb">}</span><span class="k">\#</span> cleanup<span class="nb">}</span><span class="k">\\</span>
<span class="k">\boxalert</span>&lt;13&gt;<span class="nb">{</span>clean<span class="nb">}</span>

<span class="k">\medskip</span>
<span class="nb">{</span><span class="k">\color</span><span class="nb">{</span>YosysGreen<span class="nb">}</span><span class="k">\#</span> write synthesized design<span class="nb">}</span><span class="k">\\</span>
<span class="k">\boxalert</span>&lt;14&gt;<span class="nb">{</span>write<span class="k">\_</span>verilog synth.v<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>minipage<span class="nb">}</span>

<span class="k">\vskip</span>1cm

<span class="k">\begin</span><span class="nb">{</span>block<span class="nb">}{</span>Command: <span class="k">\tt</span>
<span class="k">\only</span>&lt;1&gt;<span class="nb">{</span>read<span class="k">\_</span>verilog counter.v<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;2&gt;<span class="nb">{</span>hierarchy -check -top counter<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;3&gt;<span class="nb">{</span>proc<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;4&gt;<span class="nb">{</span>opt<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;5&gt;<span class="nb">{</span>fsm<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;6&gt;<span class="nb">{</span>opt<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;7&gt;<span class="nb">{</span>memory<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;8&gt;<span class="nb">{</span>opt<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;9&gt;<span class="nb">{</span>techmap<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;10&gt;<span class="nb">{</span>opt<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;11&gt;<span class="nb">{</span>dfflibmap -liberty mycells.lib<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;12&gt;<span class="nb">{</span>abc -liberty mycells.lib<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;13&gt;<span class="nb">{</span>clean<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;14&gt;<span class="nb">{</span>write<span class="k">\_</span>verilog synth.v<span class="nb">}}</span>
<span class="k">\only</span>&lt;1&gt;<span class="nb">{</span>
	Read Verilog source file and convert to internal representation.
<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;2&gt;<span class="nb">{</span>
	Elaborate the design hierarchy. Should always be the first
	command after reading the design. Can re-run AST front-end.
<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;3&gt;<span class="nb">{</span>
	Convert ``processes&#39;&#39; (the internal representation of behavioral
	Verilog code) into multiplexers and registers.
<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;4&gt;<span class="nb">{</span>
	Perform some basic optimizations and cleanups.
<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;5&gt;<span class="nb">{</span>
	Analyze and optimize finite state machines.
<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;6&gt;<span class="nb">{</span>
	Perform some basic optimizations and cleanups.
<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;7&gt;<span class="nb">{</span>
	Analyze memories and create circuits to implement them.
<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;8&gt;<span class="nb">{</span>
	Perform some basic optimizations and cleanups.
<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;9&gt;<span class="nb">{</span>
	Map coarse-grain RTL cells (adders, etc.) to fine-grain
	logic gates (AND, OR, NOT, etc.).
<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;10&gt;<span class="nb">{</span>
	Perform some basic optimizations and cleanups.
<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;11&gt;<span class="nb">{</span>
	Map registers to available hardware flip-flops.
<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;12&gt;<span class="nb">{</span>
	Map logic to available hardware gates.
<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;13&gt;<span class="nb">{</span>
	Clean up the design (just the last step of <span class="nb">{</span><span class="k">\tt</span> opt<span class="nb">}</span>).
<span class="nb">}</span><span class="c">%</span>
<span class="k">\only</span>&lt;14&gt;<span class="nb">{</span>
	Write final synthesis result to output file.
<span class="nb">}</span><span class="c">%</span>
<span class="k">\end</span><span class="nb">{</span>block<span class="nb">}</span>

<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">{}</span> -- Verilog Source: <span class="k">\tt</span> counter.v<span class="nb">}</span>
<span class="k">\lstinputlisting</span><span class="na">[xleftmargin=1cm, language=Verilog]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>Intro/counter.v<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">{}</span> -- Cell Library: <span class="k">\tt</span> mycells.lib<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>columns<span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>5cm<span class="nb">}</span>
<span class="k">\lstinputlisting</span><span class="na">[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=liberty, lastline=20]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>Intro/mycells.lib<span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>5cm<span class="nb">}</span>
<span class="k">\lstinputlisting</span><span class="na">[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=liberty, firstline=21]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>Intro/mycells.lib<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>columns<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Running the Synthesis Script<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t, fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">{}</span> -- Step 1/4<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>verbatim<span class="nb">}</span>
read<span class="nb">_</span>verilog counter.v
hierarchy -check -top counter
<span class="k">\end</span><span class="nb">{</span>verbatim<span class="nb">}</span>

<span class="k">\vfill</span>
<span class="k">\includegraphics</span><span class="na">[width=\linewidth,trim=0 0cm 0 0cm]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>Intro/counter<span class="nb">_</span>00.pdf<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t, fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">{}</span> -- Step 2/4<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>verbatim<span class="nb">}</span>
proc; opt; fsm; opt; memory; opt
<span class="k">\end</span><span class="nb">{</span>verbatim<span class="nb">}</span>

<span class="k">\vfill</span>
<span class="k">\includegraphics</span><span class="na">[width=\linewidth,trim=0 0cm 0 0cm]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>Intro/counter<span class="nb">_</span>01.pdf<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t, fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">{}</span> -- Step 3/4<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>verbatim<span class="nb">}</span>
techmap; opt
<span class="k">\end</span><span class="nb">{</span>verbatim<span class="nb">}</span>

<span class="k">\vfill</span>
<span class="k">\includegraphics</span><span class="na">[width=\linewidth,trim=0 0cm 0 2cm]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>Intro/counter<span class="nb">_</span>02.pdf<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t, fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">{}</span> -- Step 4/4<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>verbatim<span class="nb">}</span>
dfflibmap -liberty mycells.lib
abc -liberty mycells.lib
clean
<span class="k">\end</span><span class="nb">{</span>verbatim<span class="nb">}</span>

<span class="k">\vfill\hfil</span>
<span class="k">\includegraphics</span><span class="na">[width=10cm,trim=0 0cm 0 0cm]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>Intro/counter<span class="nb">_</span>03.pdf<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>The synth command<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">{}}</span>
Yosys contains a default (recommended example) synthesis script in form of the
<span class="nb">{</span><span class="k">\tt</span> synth<span class="nb">}</span> command. The following commands are executed by this synthesis command:

<span class="k">\begin</span><span class="nb">{</span>columns<span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>5cm<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
begin:
    hierarchy -check [-top &lt;top&gt;]

coarse:
    proc
    opt
    wreduce
    alumacc
    share
    opt
    fsm
    opt -fast
    memory -nomap
    opt<span class="nb">_</span>clean
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>5cm<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
fine:
    opt -fast -full
    memory<span class="nb">_</span>map
    opt -full
    techmap
    opt -fast

abc:
    abc -fast
    opt -fast
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>columns<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Yosys Commands<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">{}</span> 1/3 <span class="k">\hspace</span><span class="nb">{</span>0pt plus 1 filll<span class="nb">}</span> (excerpt)<span class="nb">}</span>
Command reference:
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Use ``<span class="nb">{</span><span class="k">\tt</span> help<span class="nb">}</span>&#39;&#39; for a command list and ``<span class="nb">{</span><span class="k">\tt</span> help <span class="k">\it</span> command<span class="nb">}</span>&#39;&#39; for details.
<span class="k">\item</span> Or run ``<span class="nb">{</span><span class="k">\tt</span> yosys -H<span class="nb">}</span>&#39;&#39; or ``<span class="nb">{</span><span class="k">\tt</span> yosys -h <span class="k">\it</span> command<span class="nb">}</span>&#39;&#39;.
<span class="k">\item</span> Or go to <span class="k">\url</span><span class="nb">{</span>http://www.clifford.at/yosys/documentation.html<span class="nb">}</span>.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

<span class="k">\bigskip</span>
Commands for design navigation and investigation:
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
    cd                   # a shortcut for &#39;select -module &lt;name&gt;&#39;
    ls                   # list modules or objects in modules
    dump                 # print parts of the design in ilang format
    show                 # generate schematics using graphviz
    select               # modify and view the list of selected objects
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
Commands for executing scripts or entering interactive mode:
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
    shell                # enter interactive command mode
    history              # show last interactive commands
    script               # execute commands from script file
    tcl                  # execute a TCL script file
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">{}</span> 2/3 <span class="k">\hspace</span><span class="nb">{</span>0pt plus 1 filll<span class="nb">}</span> (excerpt)<span class="nb">}</span>
Commands for reading and elaborating the design:
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
    read<span class="nb">_</span>ilang           # read modules from ilang file
    read<span class="nb">_</span>verilog         # read modules from Verilog file
    hierarchy            # check, expand and clean up design hierarchy
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
Commands for high-level synthesis:
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
    proc                 # translate processes to netlists
    fsm                  # extract and optimize finite state machines
    memory               # translate memories to basic cells
    opt                  # perform simple optimizations
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
Commands for technology mapping:
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
    techmap              # generic technology mapper
    abc                  # use ABC for technology mapping
    dfflibmap            # technology mapping of flip-flops
    hilomap              # technology mapping of constant hi- and/or lo-drivers
    iopadmap             # technology mapping of i/o pads (or buffers)
    flatten              # flatten design
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">{}</span> 3/3 <span class="k">\hspace</span><span class="nb">{</span>0pt plus 1 filll<span class="nb">}</span> (excerpt)<span class="nb">}</span>
Commands for writing the results:
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
    write<span class="nb">_</span>blif           # write design to BLIF file
    write<span class="nb">_</span>btor           # write design to BTOR file
    write<span class="nb">_</span>edif           # write design to EDIF netlist file
    write<span class="nb">_</span>ilang          # write design to ilang file
    write<span class="nb">_</span>spice          # write design to SPICE netlist file
    write<span class="nb">_</span>verilog        # write design to Verilog file
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
Script-Commands for standard synthesis tasks:
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
    synth                # generic synthesis script
    synth<span class="nb">_</span>xilinx         # synthesis for Xilinx FPGAs
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
Commands for model checking:
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
    sat                  # solve a SAT problem in the circuit
    miter                # automatically create a miter circuit
    scc                  # detect strongly connected components (logic loops)
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
... and many many more.
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>More Verilog Examples<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">{}</span> 1/3<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=Verilog]
module detectprime(a, y);
    input [4:0] a;
    output y;

    integer i, j;
    reg [31:0] lut;

    initial begin
        for (i = 0; i &lt; 32; i = i+1) begin
            lut[i] = i &gt; 1;
            for (j = 2; j*j &lt;= i; j = j+1)
                if (i <span class="c">% j == 0)</span>
                    lut[i] = 0;
        end
    end

    assign y = lut[a];
endmodule
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">{}</span> 2/3<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=Verilog]
module carryadd(a, b, y);
    parameter WIDTH = 8;
    input [WIDTH-1:0] a, b;
    output [WIDTH-1:0] y;

    genvar i;
    generate
        for (i = 0; i &lt; WIDTH; i = i+1) begin:STAGE
            wire IN1 = a[i], IN2 = b[i];
            wire C, Y;
            if (i == 0)
                assign C = IN1 <span class="nb">&amp;</span> IN2, Y = IN1 <span class="nb">^</span> IN2;
            else
                assign C = (IN1 <span class="nb">&amp;</span> IN2) | ((IN1 | IN2) <span class="nb">&amp;</span> STAGE[i-1].C),
                       Y = IN1 <span class="nb">^</span> IN2 <span class="nb">^</span> STAGE[i-1].C;
            assign y[i] = Y;
        end
    endgenerate
endmodule
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsecname</span><span class="nb">{}</span> 3/3<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=1cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>7pt<span class="nb">}{</span>8.5pt<span class="nb">}</span><span class="k">\selectfont</span>, language=Verilog]
module cam(clk, wr<span class="nb">_</span>enable, wr<span class="nb">_</span>addr, wr<span class="nb">_</span>data, rd<span class="nb">_</span>data, rd<span class="nb">_</span>addr, rd<span class="nb">_</span>match);
    parameter WIDTH = 8;
    parameter DEPTH = 16;
    localparam ADDR<span class="nb">_</span>BITS = <span class="s">$</span><span class="nb">clog</span><span class="m">2</span><span class="o">(</span><span class="nb">DEPTH</span><span class="o">-</span><span class="m">1</span><span class="o">)</span><span class="nb">;</span>

<span class="nb">    input clk, wr_enable;</span>
<span class="nb">    input </span><span class="o">[</span><span class="nb">ADDR_BITS</span><span class="o">-</span><span class="m">1</span><span class="nb">:</span><span class="m">0</span><span class="o">]</span><span class="nb"> wr_addr;</span>
<span class="nb">    input </span><span class="o">[</span><span class="nb">WIDTH</span><span class="o">-</span><span class="m">1</span><span class="nb">:</span><span class="m">0</span><span class="o">]</span><span class="nb"> wr_data, rd_data;</span>
<span class="nb">    output reg </span><span class="o">[</span><span class="nb">ADDR_BITS</span><span class="o">-</span><span class="m">1</span><span class="nb">:</span><span class="m">0</span><span class="o">]</span><span class="nb"> rd_addr;</span>
<span class="nb">    output reg rd_match;</span>

<span class="nb">    integer i;</span>
<span class="nb">    reg </span><span class="o">[</span><span class="nb">WIDTH</span><span class="o">-</span><span class="m">1</span><span class="nb">:</span><span class="m">0</span><span class="o">]</span><span class="nb"> mem </span><span class="o">[</span><span class="m">0</span><span class="nb">:DEPTH</span><span class="o">-</span><span class="m">1</span><span class="o">]</span><span class="nb">;</span>

<span class="nb">    always @</span><span class="o">(</span><span class="nb">posedge clk</span><span class="o">)</span><span class="nb"> begin</span>
<span class="nb">        rd_addr &lt;</span><span class="o">=</span><span class="nb"> &#39;bx;</span>
<span class="nb">        rd_match &lt;</span><span class="o">=</span><span class="nb"> </span><span class="m">0</span><span class="nb">;</span>
<span class="nb">        for </span><span class="o">(</span><span class="nb">i </span><span class="o">=</span><span class="nb"> </span><span class="m">0</span><span class="nb">; i &lt; DEPTH; i </span><span class="o">=</span><span class="nb"> i</span><span class="o">+</span><span class="m">1</span><span class="o">)</span><span class="nb"></span>
<span class="nb">            if </span><span class="o">(</span><span class="nb">mem</span><span class="o">[</span><span class="nb">i</span><span class="o">]</span><span class="nb"> </span><span class="o">==</span><span class="nb"> rd_data</span><span class="o">)</span><span class="nb"> begin</span>
<span class="nb">                rd_addr &lt;</span><span class="o">=</span><span class="nb"> i;</span>
<span class="nb">                rd_match &lt;</span><span class="o">=</span><span class="nb"> </span><span class="m">1</span><span class="nb">;</span>
<span class="nb">            end</span>
<span class="nb">        if </span><span class="o">(</span><span class="nb">wr_enable</span><span class="o">)</span><span class="nb"></span>
<span class="nb">            mem</span><span class="o">[</span><span class="nb">wr_addr</span><span class="o">]</span><span class="nb"> &lt;</span><span class="o">=</span><span class="nb"> wr_data;</span>
<span class="nb">    end</span>
<span class="nb">endmodule</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="nv">\subsection</span><span class="nb">{Currently unsupported Verilog</span><span class="o">-</span><span class="m">2005</span><span class="nb"> language features}</span>

<span class="nv">\begin</span><span class="nb">{frame}{</span><span class="nv">\subsecname</span><span class="nb">}</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> Tri</span><span class="o">-</span><span class="nb">state logic</span>
<span class="nv">\item</span><span class="nb"> The wor</span><span class="o">/</span><span class="nb">wand wire types </span><span class="o">(</span><span class="nb">maybe for </span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="o">)</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Latched logic </span><span class="o">(</span><span class="nb">is synthesized as logic with feedback loops</span><span class="o">)</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Some non</span><span class="o">-</span><span class="nb">synthesizable features that should be ignored in synthesis are not supported by the parser and cause a parser error </span><span class="o">(</span><span class="nb">file a bug report if you encounter this problem</span><span class="o">)</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="nv">\subsection</span><span class="nb">{Verification of Yosys}</span>

<span class="nv">\begin</span><span class="nb">{frame}{</span><span class="nv">\subsecname</span><span class="nb">}</span>
<span class="nb">Continuously checking the correctness of Yosys and making sure that new features</span>
<span class="nb">do not break old ones is a high priority in Yosys.</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">Two external test suites have been built for Yosys: VlogHammer and yosys</span><span class="o">-</span><span class="nb">bigsim</span>
<span class="o">(</span><span class="nb">see next slides</span><span class="o">)</span><span class="nb"></span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">In addition to that, yosys comes with </span><span class="s">$</span><span class="k">\approx\!</span>200<span class="s">$</span><span class="nb"> test cases used in ``{</span><span class="nv">\tt</span><span class="nb"> make test}&#39;&#39;.</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">A debug build of Yosys also contains a lot of asserts and checks the integrity of</span>
<span class="nb">the internal state after each command.</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> VlogHammer}</span>
<span class="nb">VlogHammer is a Verilog regression test suite developed to test the different</span>
<span class="nb">subsystems in Yosys by comparing them to each other and to the output created</span>
<span class="nb">by some other tools </span><span class="o">(</span><span class="nb">Xilinx Vivado, Xilinx XST, Altera Quartus II, ...</span><span class="o">)</span><span class="nb">.</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">Yosys Subsystems tested: Verilog frontend, const folding, const eval, technology mapping,</span>
<span class="nb">simulation models, SAT models.</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">Thousands of auto</span><span class="o">-</span><span class="nb">generated test cases containing code such as:</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">1</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb"></span>
<span class="nb">assign y</span><span class="m">9</span><span class="nb"> </span><span class="o">=</span><span class="nb"> </span><span class="s">$</span>signed(((+<span class="s">$</span><span class="nb">signed</span><span class="o">((</span><span class="nb">^</span><span class="o">(</span><span class="m">6</span><span class="nb">&#39;d</span><span class="m">2</span><span class="nb"> </span><span class="o">**</span><span class="nb"> a</span><span class="m">2</span><span class="o">))))</span><span class="nb">&lt;</span><span class="s">$</span>unsigned(<span class="s">$</span><span class="nb">unsigned</span><span class="o">(((+</span><span class="nb">a</span><span class="m">3</span><span class="o">))))))</span><span class="nb">;</span>
<span class="nb">assign y</span><span class="m">10</span><span class="nb"> </span><span class="o">=</span><span class="nb"> </span><span class="o">(-((+((+</span><span class="nb">{</span><span class="m">2</span><span class="nb">{</span><span class="o">(</span><span class="nb">~^p</span><span class="m">13</span><span class="o">)</span><span class="nb">}}</span><span class="o">)))</span><span class="nb">^~</span><span class="o">(!</span><span class="nb">{{b</span><span class="m">5</span><span class="nb">,b</span><span class="m">1</span><span class="nb">,a</span><span class="m">0</span><span class="nb">},</span><span class="o">(</span><span class="nb">a</span><span class="m">1</span><span class="nb">&amp;p</span><span class="m">12</span><span class="o">)</span><span class="nb">,</span><span class="o">(</span><span class="nb">a</span><span class="m">4</span><span class="o">+</span><span class="nb">a</span><span class="m">3</span><span class="o">)</span><span class="nb">}</span><span class="o">)))</span><span class="nb">;</span>
<span class="nb">assign y</span><span class="m">11</span><span class="nb"> </span><span class="o">=</span><span class="nb"> </span><span class="o">(</span><span class="nb">~&amp;</span><span class="o">(-</span><span class="nb">{</span><span class="o">(-</span><span class="m">3</span><span class="nb">&#39;sd</span><span class="m">3</span><span class="o">)</span><span class="nb">,</span><span class="o">(</span><span class="s">$</span>unsigned(<span class="s">$</span><span class="nb">signed</span><span class="o">(</span><span class="s">$</span>unsigned(<span class="nb">{</span>p0,b4,b1<span class="nb">}</span>))))<span class="nb">}</span>));
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
Some bugs in Yosys where found and fixed thanks to VlogHammer. Over 50 bugs in
the other tools used as external reference where found and reported so far.
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">{}</span> -- yosys-bigsim<span class="nb">}</span>
yosys-bigsim is a collection of real-world open-source Verilog designs and test
benches. yosys-bigsim compares the testbench outputs of simulations of the original
Verilog code and synthesis results.

<span class="k">\bigskip</span>
The following designs are included in yosys-bigsim (excerpt):
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> openmsp430<span class="nb">}</span> -- an MSP430 compatible 16 bit CPU
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> aes<span class="k">\_</span>5cycle<span class="k">\_</span>2stage<span class="nb">}</span> -- an AES encryption core
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> softusb<span class="k">\_</span>navre<span class="nb">}</span> -- an AVR compatible 8 bit CPU
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> amber23<span class="nb">}</span> -- an ARMv2 compatible 32 bit CPU
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> lm32<span class="nb">}</span> -- another 32 bit CPU from Lattice Semiconductor
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> verilog-pong<span class="nb">}</span> -- a hardware pong game with VGA output
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> elliptic<span class="k">\_</span>curve<span class="k">\_</span>group<span class="nb">}</span> -- ECG point-add and point-scalar-mul core
<span class="k">\item</span> <span class="nb">{</span><span class="k">\tt</span> reed<span class="k">\_</span>solomon<span class="k">\_</span>decoder<span class="nb">}</span> -- a Reed-Solomon Error Correction Decoder
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Benefits of Open Source HDL Synthesis<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Cost (also applies to ``free as in free beer&#39;&#39; solutions)
<span class="k">\item</span> Availability and Reproducibility
<span class="k">\item</span> Framework- and all-in-one-aspects
<span class="k">\item</span> Educational Tool
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

<span class="k">\bigskip</span>

Yosys is open source under the ISC license.
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">{}</span> -- 1/3<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Cost (also applies to ``free as in free beer&#39;&#39; solutions): <span class="k">\smallskip\par</span>
Today the cost for a mask set in <span class="s">$</span><span class="nv">\unit</span><span class="o">[</span><span class="m">180</span><span class="o">]</span><span class="nb">{nm}</span><span class="s">$</span> technology is far less than
the cost for the design tools needed to design the mask layouts. Open Source
ASIC flows are an important enabler for ASIC-level Open Source Hardware.

<span class="k">\bigskip</span>
<span class="k">\item</span> Availability and Reproducibility: <span class="k">\smallskip\par</span>
If you are a researcher who is publishing, you want to use tools that everyone
else can also use. Even if most universities have access to all major
commercial tools, you usually do not have easy access to the version that was
used in a research project a couple of years ago. With Open Source tools you
can even release the source code of the tool you have used alongside your data.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">{}</span> -- 2/3<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Framework: <span class="k">\smallskip\par</span>
Yosys is not only a tool. It is a framework that can be used as basis for other
developments, so researchers and hackers alike do not need to re-invent the
basic functionality. Extensibility was one of Yosys&#39; design goals.

<span class="k">\bigskip</span>
<span class="k">\item</span> All-in-one: <span class="k">\smallskip\par</span>
Because of the framework characteristics of Yosys, an increasing number of features
become available in one tool. Yosys not only can be used for circuit synthesis but
also for formal equivalence checking, SAT solving, and for circuit analysis, to
name just a few other application domains. With proprietary software one needs to
learn a new tool for each of these applications.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">{}</span> -- 3/3<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Educational Tool: <span class="k">\smallskip\par</span>
Proprietary synthesis tools are at times very secretive about their inner
workings. They often are ``black boxes&#39;&#39;. Yosys is very open about its
internals and it is easy to observe the different steps of synthesis.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>block<span class="nb">}{</span>Yosys is licensed under the ISC license:<span class="nb">}</span>
Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.
<span class="k">\end</span><span class="nb">{</span>block<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Typical Applications for Yosys<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Synthesis of final production designs
<span class="k">\item</span> Pre-production synthesis (trial runs before investing in other tools)
<span class="k">\item</span> Conversion of full-featured Verilog to simple Verilog
<span class="k">\item</span> Conversion of Verilog to other formats (BLIF, BTOR, etc)
<span class="k">\item</span> Demonstrating synthesis algorithms (e.g. for educational purposes)
<span class="k">\item</span> Framework for experimenting with new algorithms
<span class="k">\item</span> Framework for building custom flows<span class="k">\footnote</span><span class="na">[frame]</span><span class="nb">{</span>Not limited to synthesis
but also formal verification, reverse engineering, ...<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Projects (that I know of) using Yosys<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">{}</span> -- (1/2)<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Ongoing PhD project on coarse grain synthesis <span class="k">\\</span>
<span class="nb">{</span><span class="k">\setlength</span><span class="nb">{</span><span class="k">\parindent</span><span class="nb">}{</span>0.5cm<span class="nb">}</span><span class="k">\footnotesize</span>
Johann Glaser and Clifford Wolf. Methodology and Example-Driven Interconnect
Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable
Architectures. In Jan Haase, editor, <span class="k">\it</span> Models, Methods, and Tools for Complex
Chip Design. Lecture Notes in Electrical Engineering. Volume 265, 2014, pp
201-221. Springer, 2013.<span class="nb">}</span>

<span class="k">\bigskip</span>
<span class="k">\item</span> I know several people that use Yosys simply as Verilog frontend for other
flows (using either the BLIF and BTOR backends).

<span class="k">\bigskip</span>
<span class="k">\item</span> I know some analog chip designers that use Yosys for small digital
control logic because it is simpler than setting up a commercial flow.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">{}</span> -- (2/2)<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Efabless
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\smallskip</span> <span class="k">\item</span> Not much information on the website (<span class="k">\url</span><span class="nb">{</span>http://efabless.com<span class="nb">}</span>) yet.
<span class="k">\smallskip</span> <span class="k">\item</span> Very cheap 180nm prototyping process (partnering with various fabs)
<span class="k">\smallskip</span> <span class="k">\item</span> A semiconductor company, NOT an EDA company
<span class="k">\smallskip</span> <span class="k">\item</span> Web-based design environment
<span class="k">\smallskip</span> <span class="k">\item</span> HDL Synthesis using Yosys
<span class="k">\smallskip</span> <span class="k">\item</span> Custom place<span class="k">\&amp;</span>route tool

<span class="k">\bigskip</span>
<span class="k">\item</span> efabless is building an Open Source IC as reference design. <span class="k">\\</span>
<span class="k">\hskip</span>1cm (to be announced soon: <span class="k">\url</span><span class="nb">{</span>http://www.openic.io<span class="nb">}</span>)
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Supported Platforms<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Main development OS: Kubuntu 14.04
<span class="k">\item</span> There is a PPA for ubuntu (not maintained by me)
<span class="k">\item</span> Any current Debian-based system should work out of the box
<span class="k">\item</span> When building on other Linux distributions:
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Needs compiler with some C++11 support
<span class="k">\item</span> See README file for build instructions
<span class="k">\item</span> Post to the subreddit if you get stuck
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Ported to OS X (Darwin) and OpenBSD
<span class="k">\item</span> Native win32 build with VisualStudio
<span class="k">\item</span> Cross win32 build with MXE
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Other Open Source Tools<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Icarus Verilog <span class="k">\\</span>
<span class="k">\smallskip\hskip</span>1cm<span class="nb">{}</span>Verilog Simulation (and also a good syntax checker) <span class="k">\\</span>
<span class="k">\smallskip\hskip</span>1cm<span class="nb">{}</span><span class="k">\url</span><span class="nb">{</span>http://iverilog.icarus.com/<span class="nb">}</span>

<span class="k">\bigskip</span>
<span class="k">\item</span> Qflow (incl. TimberWolf, qrouter and Magic) <span class="k">\\</span>
<span class="k">\smallskip\hskip</span>1cm<span class="nb">{}</span>A complete ASIC synthesis flow, using Yosys and ABC <span class="k">\\</span>
<span class="k">\smallskip\hskip</span>1cm<span class="nb">{}</span><span class="k">\url</span><span class="nb">{</span>http://opencircuitdesign.com/qflow/<span class="nb">}</span>

<span class="k">\bigskip</span>
<span class="k">\item</span> ABC <span class="k">\\</span>
<span class="k">\smallskip\hskip</span>1cm<span class="nb">{}</span>Logic optimization, technology mapping, and more <span class="k">\\</span>
<span class="k">\smallskip\hskip</span>1cm<span class="nb">{}</span><span class="k">\url</span><span class="nb">{</span>http://www.eecs.berkeley.edu/~alanmi/abc/<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Yosys needs you<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">}</span>
<span class="k">\dots</span> as an active user:
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Use Yosys for on your own projects
<span class="k">\item</span> .. even if you are not using it as final synthesis tool
<span class="k">\item</span> Join the discussion on the Subreddit
<span class="k">\item</span> Report bugs and send in feature requests
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

<span class="k">\bigskip</span>
<span class="k">\dots</span> as a developer:
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Use Yosys as environment for your (research) work
<span class="k">\item</span> .. you might also want to look into ABC for logic-level stuff
<span class="k">\item</span> Fork the project on github or create loadable plugins
<span class="k">\item</span> We need a VHDL frontend or a good VHDL-to-Verilog converter
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Documentation, Downloads, Contacts<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Website: <span class="k">\\</span>
<span class="k">\smallskip\hskip</span>1cm<span class="k">\url</span><span class="nb">{</span>http://www.clifford.at/yosys/<span class="nb">}</span>

<span class="k">\bigskip</span>
<span class="k">\item</span> Manual, Command Reference, Application Notes: <span class="k">\\</span>
<span class="k">\smallskip\hskip</span>1cm<span class="k">\url</span><span class="nb">{</span>http://www.clifford.at/yosys/documentation.html<span class="nb">}</span>

<span class="k">\bigskip</span>
<span class="k">\item</span> Instead of a mailing list we have a SubReddit: <span class="k">\\</span>
<span class="k">\smallskip\hskip</span>1cm<span class="k">\url</span><span class="nb">{</span>http://www.reddit.com/r/yosys/<span class="nb">}</span>

<span class="k">\bigskip</span>
<span class="k">\item</span> Direct link to the source code: <span class="k">\\</span>
<span class="k">\smallskip\hskip</span>1cm<span class="k">\url</span><span class="nb">{</span>https://github.com/cliffordwolf/yosys<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Summary<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Yosys is a powerful tool and framework for Verilog synthesis.
<span class="k">\item</span> It uses a command-based interface and can be controlled by scripts.
<span class="k">\item</span> By combining existing commands and implementing new commands Yosys can
be used in a wide range of application far beyond simple synthesis.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

<span class="k">\bigskip</span>
<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>center<span class="nb">}</span>
Questions?
<span class="k">\end</span><span class="nb">{</span>center<span class="nb">}</span>

<span class="k">\bigskip</span>
<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>center<span class="nb">}</span>
<span class="k">\url</span><span class="nb">{</span>http://www.clifford.at/yosys/<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>center<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>
</pre></div>
</code></pre></td></tr></table>
</div> <!-- class=content -->
<div class='footer'>generated by <a href='https://git.zx2c4.com/cgit/about/'>cgit v1.2.3</a> (<a href='https://git-scm.com/'>git 2.25.1</a>) at 2025-07-23 03:02:41 +0000</div>
</div> <!-- id=cgit -->
</body>
</html>
