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<div class='path'>path: <a href='/cgit.cgi/iCE40/yosys/log/?id=5a63c197477d59567424faab3b56329c426394b9&amp;showmsg=1'>root</a>/<a href='/cgit.cgi/iCE40/yosys/log/kernel?id=5a63c197477d59567424faab3b56329c426394b9&amp;showmsg=1'>kernel</a>/<a href='/cgit.cgi/iCE40/yosys/log/kernel/yosys.cc?id=5a63c197477d59567424faab3b56329c426394b9&amp;showmsg=1'>yosys.cc</a></div><div class='content'><table class='list nowrap'><tr class='nohover'><th></th><th class='left'>Commit message (<a href='/cgit.cgi/iCE40/yosys/log/kernel/yosys.cc?id=5a63c197477d59567424faab3b56329c426394b9'>Collapse</a>)</th><th class='left'>Author</th><th class='left'>Age</th><th class='left'>Files</th><th class='left'>Lines</th></tr>
<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=cd92a974f4cf8d4db74d504c38e51ce043e02403'>Add Pass::on_register() and Pass::on_shutdown()</a></td><td>Clifford Wolf</td><td><span title='2020-01-09 21:36:34 +0100'>2020-01-09</span></td><td>1</td><td><span class='deletions'>-1</span>/<span class='insertions'>+2</span></td></tr>
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Signed-off-by: Clifford Wolf &lt;clifford@clifford.at&gt;


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<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=e9f3eb97607bc49b6bb77229f1fad9796aea1483'>Bump year in copyright notice</a></td><td>Clifford Wolf</td><td><span title='2019-08-22 18:43:16 +0200'>2019-08-22</span></td><td>1</td><td><span class='deletions'>-1</span>/<span class='insertions'>+1</span></td></tr>
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Signed-off-by: Clifford Wolf &lt;clifford@clifford.at&gt;


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<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=390bf459fbd766d4b1f9d16c6e10d665b43369d5'>Use ID() in kernel/*, add simple ID:: hack (to be improved upon later)</a></td><td>Clifford Wolf</td><td><span title='2019-08-11 11:39:46 +0200'>2019-08-11</span></td><td>1</td><td><span class='deletions'>-0</span>/<span class='insertions'>+7</span></td></tr>
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Signed-off-by: Clifford Wolf &lt;clifford@clifford.at&gt;


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<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=8222c5735e3b31fc2a7507abe607bb5aa9f863de'>More improvements and cleanups in IdString subsystem</a></td><td>Clifford Wolf</td><td><span title='2019-08-11 11:39:46 +0200'>2019-08-11</span></td><td>1</td><td><span class='deletions'>-7</span>/<span class='insertions'>+0</span></td></tr>
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- better use of "inline" keyword
- deprecate "sticky" IDs feature
- improve handling of empty ID
- add move constructor

Signed-off-by: Clifford Wolf &lt;clifford@clifford.at&gt;


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<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=6d77236f3845cd8785e7bdd4da3c5ef966be6043'>substr() -&gt; compare()</a></td><td>Eddie Hung</td><td><span title='2019-08-07 12:20:08 -0700'>2019-08-07</span></td><td>1</td><td><span class='deletions'>-25</span>/<span class='insertions'>+25</span></td></tr>
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<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=95a6582f342537d387063be10cba55c001ed19f5'>Be less aggressive with running design-&gt;check()</a></td><td>Clifford Wolf</td><td><span title='2019-08-06 19:21:37 +0200'>2019-08-06</span></td><td>1</td><td><span class='deletions'>-2</span>/<span class='insertions'>+8</span></td></tr>
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Signed-off-by: Clifford Wolf &lt;clifford@clifford.at&gt;


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<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=da6701c4cd26d559241c8a3de61b51ace1e03fe4'>Fix frontend auto-detection for gzipped input</a></td><td>David Shah</td><td><span title='2019-07-26 10:29:05 +0100'>2019-07-26</span></td><td>1</td><td><span class='deletions'>-9</span>/<span class='insertions'>+12</span></td></tr>
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Signed-off-by: David Shah &lt;dave@ds0.me&gt;


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<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=41d7d9d24b8ba7fd84dd72b27eb9aede10b8ef15'>Clarify script -scriptwire doc</a></td><td>Eddie Hung</td><td><span title='2019-07-08 19:21:21 -0700'>2019-07-08</span></td><td>1</td><td><span class='deletions'>-0</span>/<span class='insertions'>+4</span></td></tr>
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<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=f1504696e56030ba5d1f2d7a4b7616695dd8020b'>Use Pass::call_on_module() as per @cliffordwolf comments</a></td><td>Eddie Hung</td><td><span title='2019-07-02 08:20:37 -0700'>2019-07-02</span></td><td>1</td><td><span class='deletions'>-1</span>/<span class='insertions'>+1</span></td></tr>
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<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=02ba85b13302f0d20f6b51cc7fdff2fb953421df'>script -select -&gt; script -scriptwire</a></td><td>Eddie Hung</td><td><span title='2019-07-02 08:17:26 -0700'>2019-07-02</span></td><td>1</td><td><span class='deletions'>-5</span>/<span class='insertions'>+5</span></td></tr>
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<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=06971385fa5f47498c138f3f36a203b01c7cbb42'>Support ability for "script -select" to take commands from wires</a></td><td>Eddie Hung</td><td><span title='2019-06-28 13:36:33 -0700'>2019-06-28</span></td><td>1</td><td><span class='deletions'>-8</span>/<span class='insertions'>+39</span></td></tr>
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<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=468c41d997477aa6c67a8b97bc4d9dcff185b815'>Support ~ for home directory</a></td><td>Ben Widawsky</td><td><span title='2019-06-18 14:38:40 -0700'>2019-06-18</span></td><td>1</td><td><span class='deletions'>-0</span>/<span class='insertions'>+4</span></td></tr>
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This is tested on Linux only

v2:
Wrap functioanlity in ifndef _WIN32 (eddiehung)
Find '~/' instead of '~' (cliffordwolf)

Signed-off-by: Ben Widawsky &lt;ben@bwidawsk.net&gt;


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<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=bafbb9ee905f042056d723ecde4a62d58b6d8f4c'>Optimize ceil_log2 function</a></td><td>Matthew Daiter</td><td><span title='2019-05-07 12:17:56 -0500'>2019-05-07</span></td><td>1</td><td><span class='deletions'>-2</span>/<span class='insertions'>+4</span></td></tr>
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<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=4f15e7f00fa2b073d6df39d4af7171f2a3f07bc9'>fix codestyle formatting</a></td><td>Oleg Endo</td><td><span title='2019-04-29 19:20:33 +0900'>2019-04-29</span></td><td>1</td><td><span class='deletions'>-11</span>/<span class='insertions'>+11</span></td></tr>
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<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=e531fb203aedeb3863ebf8add0bbd8251183d27a'>escape spaces with backslash when writing dep file</a></td><td>Oleg Endo</td><td><span title='2019-04-29 16:13:34 +0900'>2019-04-29</span></td><td>1</td><td><span class='deletions'>-0</span>/<span class='insertions'>+14</span></td></tr>
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filenames are sparated by spaces in the dep file.  if a filename in the
dep file contains spaces they must be escaped, otherwise the tool that
reads the dep file will see multiple wrong filenames.


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<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=072c9393805d59b988f93b184356c54731237a5a'>Fixed identation</a></td><td>Benedikt Tutzer</td><td><span title='2019-04-01 13:36:01 +0200'>2019-04-01</span></td><td>1</td><td><span class='deletions'>-1</span>/<span class='insertions'>+1</span></td></tr>
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<tr class='logheader'><td class='commitgraph'>*   </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=03d1606b42110f8eac7311ac57c7334d1f781273'>Merge remote-tracking branch 'origin/master' into feature/python_bindings</a></td><td>Benedikt Tutzer</td><td><span title='2019-03-28 12:16:39 +0100'>2019-03-28</span></td><td>1</td><td><span class='deletions'>-22</span>/<span class='insertions'>+43</span></td></tr>
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<tr class='logheader'><td class='commitgraph'><span class='column2'>|</span> * </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=1cd04a68389671c91dddb56cc3d2f9032f9b44e3'>Fix a bug in handling quotes in multi-cmd lines in Yosys scripts</a></td><td>Clifford Wolf</td><td><span title='2019-03-12 21:15:11 +0100'>2019-03-12</span></td><td>1</td><td><span class='deletions'>-1</span>/<span class='insertions'>+7</span></td></tr>
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Signed-off-by: Clifford Wolf &lt;clifford@clifford.at&gt;


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<tr class='logheader'><td class='commitgraph'><span class='column2'>|</span> * </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=d9bb5f3637634ea214194b612aee4bb0c62d7a5c'>Add ENABLE_GLOB Makefile switch</a></td><td>Clifford Wolf</td><td><span title='2019-03-11 01:08:36 -0700'>2019-03-11</span></td><td>1</td><td><span class='deletions'>-3</span>/<span class='insertions'>+5</span></td></tr>
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Signed-off-by: Clifford Wolf &lt;clifford@clifford.at&gt;


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<tr class='logheader'><td class='commitgraph'><span class='column2'>|</span> * </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=efa278e232d20ea080743801bd91d55ec62955cf'>Fix typographical and grammatical errors and inconsistencies.</a></td><td>whitequark</td><td><span title='2019-01-02 13:12:17 +0000'>2019-01-02</span></td><td>1</td><td><span class='deletions'>-1</span>/<span class='insertions'>+1</span></td></tr>
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The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.


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<tr class='logheader'><td class='commitgraph'><span class='column2'>|</span> * </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=2ca237e08665e4307da5bf40b7f3e17ca3e640db'>tcl: add support for passing arguments to scripts.</a></td><td>whitequark</td><td><span title='2018-12-20 07:32:24 +0000'>2018-12-20</span></td><td>1</td><td><span class='deletions'>-7</span>/<span class='insertions'>+18</span></td></tr>
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<tr class='logheader'><td class='commitgraph'><span class='column2'>|</span> * </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=6732e566321b828c83b563d24a10ac31c6d03e28'>Avoid assert when label is an empty string</a></td><td>Jon Burgess</td><td><span title='2018-10-28 14:57:04 +0000'>2018-10-28</span></td><td>1</td><td><span class='deletions'>-1</span>/<span class='insertions'>+1</span></td></tr>
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Calling back() on an empty string is not allowed and triggers
an assert with recent gcc:

$ cd manual/PRESENTATION_Intro
$ ../../yosys counter.ys
...
/usr/include/c++/8/bits/basic_string.h:1136: std::__cxx11::basic_string&lt;_CharT, _Traits, _Alloc&gt;::reference std::__cxx11::basic_string&lt;_CharT, _Traits, _Alloc&gt;::back() [with _CharT = char; _Traits = std::char_traits&lt;char&gt;; _Alloc = std::allocator&lt;char&gt;; std::__cxx11::basic_string&lt;_CharT, _Traits, _Alloc&gt;::reference = char&amp;]: Assertion '!empty()' failed.

802             if (label.back() == ':' &amp;&amp; GetSize(label) &gt; 1)
(gdb) p label
$1 = ""


</td></tr>
<tr class='logheader'><td class='commitgraph'><span class='column2'>|</span> * </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=9ed77f5ba853a316cf88221fa142e188f84765f0'>fix unhandled std::out_of_range when calling yosys with 3-character argument</a></td><td>whentze</td><td><span title='2018-10-22 19:40:22 +0200'>2018-10-22</span></td><td>1</td><td><span class='deletions'>-2</span>/<span class='insertions'>+2</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column2'>|</span> <span class='column3'>|</span> </td>
<td colspan='5' class='logmsg'>
</td></tr>
<tr class='logheader'><td class='commitgraph'><span class='column2'>|</span> * </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=c5e9034834ce0bcc6f6c611bc3ad3d244a32732f'>Fix Cygwin build and document needed packages</a></td><td>Miodrag Milanovic</td><td><span title='2018-09-19 10:16:53 +0200'>2018-09-19</span></td><td>1</td><td><span class='deletions'>-1</span>/<span class='insertions'>+1</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column2'>|</span> <span class='column3'>|</span> </td>
<td colspan='5' class='logmsg'>
</td></tr>
<tr class='logheader'><td class='commitgraph'><span class='column2'>|</span> *   </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=67b10262975340e0b53f8d1072ac2e1c1f087fb1'>Merge pull request #591 from hzeller/virtual-override</a></td><td>Clifford Wolf</td><td><span title='2018-08-15 14:05:38 +0200'>2018-08-15</span></td><td>1</td><td><span class='deletions'>-8</span>/<span class='insertions'>+8</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column2'>|</span> <span class='column4'>|</span><span class='column5'>\</span>  
<span class='column2'>|</span> <span class='column4'>|</span> <span class='column5'>|</span> 
<span class='column2'>|</span> <span class='column4'>|</span> <span class='column5'>|</span> </td>
<td colspan='5' class='logmsg'>
Consistent use of 'override' for virtual methods in derived classes.

</td></tr>
<tr class='logheader'><td class='commitgraph'><span class='column2'>|</span> <span class='column4'>|</span> * </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=3aa4484a3cd9a2e82fddd499cde575eaf8c565cc'>Consistent use of 'override' for virtual methods in derived classes.</a></td><td>Henner Zeller</td><td><span title='2018-07-20 23:51:06 -0700'>2018-07-20</span></td><td>1</td><td><span class='deletions'>-8</span>/<span class='insertions'>+8</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column2'>|</span> <span class='column4'>|</span> <span class='column5'>|</span> 
<span class='column2'>|</span> <span class='column4'>|</span> <span class='column5'>|</span> 
<span class='column2'>|</span> <span class='column4'>|</span> <span class='column5'>|</span> 
<span class='column2'>|</span> <span class='column4'>|</span> <span class='column5'>|</span> 
<span class='column2'>|</span> <span class='column4'>|</span> <span class='column5'>|</span> 
<span class='column2'>|</span> <span class='column4'>|</span> <span class='column5'>|</span> 
<span class='column2'>|</span> <span class='column4'>|</span> <span class='column5'>|</span> 
<span class='column2'>|</span> <span class='column4'>|</span> <span class='column5'>|</span> 
<span class='column2'>|</span> <span class='column4'>|</span> <span class='column5'>|</span> </td>
<td colspan='5' class='logmsg'>
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)


</td></tr>
<tr class='logheader'><td class='commitgraph'><span class='column2'>|</span> * <span class='column5'>|</span> </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=80d7e007ff4cbe0a9669224751c68e5325fbed0a'>Map .eblif extension as blif.</a></td><td>litghost</td><td><span title='2018-08-13 14:02:53 -0700'>2018-08-13</span></td><td>1</td><td><span class='deletions'>-0</span>/<span class='insertions'>+2</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column2'>|</span> <span class='column5'>|</span><span class='column5'>/</span>  
<span class='column2'>|</span> <span class='column5'>|</span>   
<span class='column2'>|</span> <span class='column5'>|</span>   
<span class='column2'>|</span> <span class='column5'>|</span>   </td>
<td colspan='5' class='logmsg'>
Signed-off-by: litghost &lt;537074+litghost@users.noreply.github.com&gt;


</td></tr>
<tr class='logheader'><td class='commitgraph'>* <span class='column5'>|</span> </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=d41c68ee5ad908db1dd75552816789e493d011bf'>The share directory cannot be searched when used as a Python library, only ↵</a></td><td>Benedikt Tutzer</td><td><span title='2018-08-20 15:27:50 +0200'>2018-08-20</span></td><td>1</td><td><span class='deletions'>-1</span>/<span class='insertions'>+0</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column5'>|</span> <span class='column5'>|</span> 
<span class='column5'>|</span> <span class='column5'>|</span> 
<span class='column5'>|</span> <span class='column5'>|</span> 
<span class='column5'>|</span> <span class='column5'>|</span> </td>
<td colspan='5' class='logmsg'>
in shell mode


</td></tr>
<tr class='logheader'><td class='commitgraph'>* <span class='column5'>|</span> </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=6d18837d62436b297b34c20d5a005ef0b6a75da2'>Python passes are now looked for in share/plugins and can be added by ↵</a></td><td>Benedikt Tutzer</td><td><span title='2018-08-20 15:11:06 +0200'>2018-08-20</span></td><td>1</td><td><span class='deletions'>-4</span>/<span class='insertions'>+1</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column5'>|</span> <span class='column5'>|</span> 
<span class='column5'>|</span> <span class='column5'>|</span> 
<span class='column5'>|</span> <span class='column5'>|</span> 
<span class='column5'>|</span> <span class='column5'>|</span> </td>
<td colspan='5' class='logmsg'>
specifying a relative or absolute path


</td></tr>
<tr class='logheader'><td class='commitgraph'>* <span class='column5'>|</span> </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=5864db3c2bf353d4ee124d35aa2f911c4249edbc'>Fixed issue when using a python plugin in the yosys shell</a></td><td>Benedikt Tutzer</td><td><span title='2018-08-20 14:44:03 +0200'>2018-08-20</span></td><td>1</td><td><span class='deletions'>-0</span>/<span class='insertions'>+16</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column5'>|</span> <span class='column5'>|</span> </td>
<td colspan='5' class='logmsg'>
</td></tr>
<tr class='logheader'><td class='commitgraph'>* <span class='column5'>|</span> </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=d79a2808cf2446fa21d91a6141f6fbe2318c03ec'>Python Passes can now be added with the -m option or with the plugin ↵</a></td><td>Benedikt Tutzer</td><td><span title='2018-08-16 16:00:11 +0200'>2018-08-16</span></td><td>1</td><td><span class='deletions'>-0</span>/<span class='insertions'>+26</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column5'>|</span><span class='column5'>/</span>  
<span class='column5'>|</span>   
<span class='column5'>|</span>   
<span class='column5'>|</span>   </td>
<td colspan='5' class='logmsg'>
command. There are still issues when run in shell mode, but they can be used just fine in a python script


</td></tr>
<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=bd87462b47fdd8d7885269246ec1f7b685c6f86f'>Fix reading techlibs under emscripten</a></td><td>Robert Ou</td><td><span title='2018-05-18 22:42:33 -0700'>2018-05-18</span></td><td>1</td><td><span class='deletions'>-1</span>/<span class='insertions'>+1</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column5'>|</span> </td>
<td colspan='5' class='logmsg'>
</td></tr>
<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=c1ecb1b2f1427e5d8616c9177c6962ebf1449a47'>Add "#ifdef __FreeBSD__"</a></td><td>Christian Krämer</td><td><span title='2018-05-13 13:08:26 +0200'>2018-05-13</span></td><td>1</td><td><span class='deletions'>-1</span>/<span class='insertions'>+26</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column5'>|</span> 
<span class='column5'>|</span> 
<span class='column5'>|</span> 
<span class='column5'>|</span> </td>
<td colspan='5' class='logmsg'>
(Re-commit e3575a8 with corrected author field)


</td></tr>
<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=1167538d265b634d6d4d825e9d92d2211f7beee9'>Revert "Add "#ifdef __FreeBSD__""</a></td><td>Clifford Wolf</td><td><span title='2018-05-13 13:06:36 +0200'>2018-05-13</span></td><td>1</td><td><span class='deletions'>-26</span>/<span class='insertions'>+1</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column5'>|</span> 
<span class='column5'>|</span> 
<span class='column5'>|</span> 
<span class='column5'>|</span> </td>
<td colspan='5' class='logmsg'>
This reverts commit e3575a86c525f2511902e7022893c3923ba8093e.


</td></tr>
<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=e3575a86c525f2511902e7022893c3923ba8093e'>Add "#ifdef __FreeBSD__"</a></td><td>Johnny Sorocil</td><td><span title='2018-05-05 13:02:44 +0200'>2018-05-05</span></td><td>1</td><td><span class='deletions'>-1</span>/<span class='insertions'>+26</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column5'>|</span> </td>
<td colspan='5' class='logmsg'>
</td></tr>
<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=64ea55056a4fca35fa4e956d40da98c20bb8d730'>Rename rename to renames</a></td><td>Edmond Cote</td><td><span title='2018-03-20 15:50:50 -0700'>2018-03-20</span></td><td>1</td><td><span class='deletions'>-3</span>/<span class='insertions'>+5</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column5'>|</span> 
<span class='column5'>|</span> 
<span class='column5'>|</span> </td>
<td colspan='5' class='logmsg'>
Create TCL alias for rename command.  Using renames.  Following the same convention as proc -&gt; procs.

</td></tr>
<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=2935e8ea4152b0678314f79bae91258565592032'>Update copyright header</a></td><td>Clifford Wolf</td><td><span title='2018-03-04 21:31:10 +0100'>2018-03-04</span></td><td>1</td><td><span class='deletions'>-1</span>/<span class='insertions'>+1</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column5'>|</span> 
<span class='column5'>|</span> 
<span class='column5'>|</span> 
<span class='column5'>|</span> </td>
<td colspan='5' class='logmsg'>
Signed-off-by: Clifford Wolf &lt;clifford@clifford.at&gt;


</td></tr>
<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=a96c775a7301645b27486a5e663c75fca460f577'>Add support for "yosys -E"</a></td><td>Clifford Wolf</td><td><span title='2018-01-07 16:36:13 +0100'>2018-01-07</span></td><td>1</td><td><span class='deletions'>-1</span>/<span class='insertions'>+5</span></td></tr>
<tr class='nohover-highlight'><td class='commitgraph'><span class='column5'>|</span> 
<span class='column5'>|</span> 
<span class='column5'>|</span> 
<span class='column5'>|</span> </td>
<td colspan='5' class='logmsg'>
Signed-off-by: Clifford Wolf &lt;clifford@clifford.at&gt;


</td></tr>
<tr class='logheader'><td class='commitgraph'>* </td><td class='logsubject'><a href='/cgit.cgi/iCE40/yosys/commit/kernel/yosys.cc?id=9ae25039fb6e28db639372d67c1b72c4170feaa3'>Add support for editline as replacement for readline</a></td><td>Clifford Wolf</td><td><spa<style>pre { line-height: 125%; margin: 0; }
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.highlight .il { color: #0000DD; font-weight: bold } /* Literal.Number.Integer.Long */</style><div class="highlight"><pre><span></span><span class="k">\section</span><span class="nb">{</span>Yosys by example -- Advanced Synthesis<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>
<span class="k">\sectionpage</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span>Overview<span class="nb">}</span>
This section contains 4 subsections:
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Using selections
<span class="k">\item</span> Advanced uses of techmap
<span class="k">\item</span> Coarse-grain synthesis
<span class="k">\item</span> Automatic design changes
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Using selections<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>
<span class="k">\subsectionpage</span>
<span class="k">\subsectionpagesuffix</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\subsubsection</span><span class="nb">{</span>Simple selections<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsubsecname</span><span class="nb">}</span>
Most Yosys commands make use of the ``selection framework&#39;&#39; of Yosys. It can be used
to apply commands only to part of the design. For example:

<span class="k">\medskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=0.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
delete                # will delete the whole design, but

delete foobar         # will only delete the module foobar.
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
The <span class="nb">{</span><span class="k">\tt</span> select<span class="nb">}</span> command can be used to create a selection for subsequent
commands. For example:

<span class="k">\medskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=0.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
select foobar         # select the module foobar
delete                # delete selected objects
select -clear         # reset selection (select whole design)
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\subsubsection</span><span class="nb">{</span>Selection by object name<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsubsecname</span><span class="nb">}</span>
The easiest way to select objects is by object name. This is usually only done
in synthesis scripts that are hand-tailored for a specific design.

<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=0.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
select foobar         # select module foobar
select foo*           # select all modules whose names start with foo
select foo*/bar*      # select all objects matching bar* from modules matching foo*
select */clk          # select objects named clk from all modules
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\subsubsection</span><span class="nb">{</span>Module and design context<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsubsecname</span><span class="nb">}</span>
Commands can be executed in <span class="nb">{</span><span class="k">\it</span> module<span class="k">\/</span><span class="nb">}</span> or <span class="nb">{</span><span class="k">\it</span> design<span class="k">\/</span><span class="nb">}</span> context. Until now all
commands have been executed in design context. The <span class="nb">{</span><span class="k">\tt</span> cd<span class="nb">}</span> command can be used
to switch to module context.

<span class="k">\bigskip</span>
In module context all commands only effect the active module. Objects in the module
are selected without the <span class="nb">{</span><span class="k">\tt</span> &lt;module<span class="k">\_</span>name&gt;/<span class="nb">}</span> prefix. For example:

<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=0.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
cd foo                # switch to module foo
delete bar            # delete object foo/bar

cd mycpu              # switch to module mycpu
dump reg<span class="nb">_</span>*            # print details on all objects whose names start with reg<span class="nb">_</span>

cd ..                 # switch back to design
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
Note: Most synthesis scripts never switch to module context. But it is a very powerful
tool for interactive design investigation.
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\subsubsection</span><span class="nb">{</span>Selecting by object property or type<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsubsecname</span><span class="nb">}</span>
Special patterns can be used to select by object property or type. For example:

<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=0.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
select w:reg<span class="nb">_</span>*        # select all wires whose names start with reg<span class="nb">_</span>
select a:foobar       # select all objects with the attribute foobar set
select a:foobar=42    # select all objects with the attribute foobar set to 42
select A:blabla       # select all modules with the attribute blabla set
select foo/t:<span class="s">$</span><span class="nb">add     # select all </span><span class="s">$</span>add cells from the module foo
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
A complete list of this pattern expressions can be found in the command
reference to the <span class="nb">{</span><span class="k">\tt</span> select<span class="nb">}</span> command.
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\subsubsection</span><span class="nb">{</span>Combining selection<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[fragile]<span class="nb">{</span><span class="k">\subsubsecname</span><span class="nb">}</span>
When more than one selection expression is used in one statement, then they are
pushed on a stack. The final elements on the stack are combined into a union:

<span class="k">\medskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=0.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
select t:<span class="s">$</span><span class="nb">dff r:WIDTH&gt;</span><span class="m">1</span><span class="nb">     # all cells of type </span><span class="s">$</span>dff and/or with a parameter WIDTH &gt; 1
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

<span class="k">\bigskip</span>
Special <span class="k">\%</span>-commands can be used to combine the elements on the stack:

<span class="k">\medskip</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[xleftmargin=0.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
select t:<span class="s">$</span><span class="nb">dff r:WIDTH&gt;</span><span class="m">1</span><span class="nb"> </span><span class="c">%i  # all cells of type $dff *AND* with a parameter WIDTH &gt; 1</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\begin</span><span class="nb">{block}{Examples for {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\%</span><span class="nb">}</span><span class="o">-</span><span class="nb">codes </span><span class="o">(</span><span class="nb">see {</span><span class="nv">\tt</span><span class="nb"> help select} for full list</span><span class="o">)</span><span class="nb">}</span>
<span class="nb">{</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\%</span><span class="nb">u} </span><span class="nv">\dotfill</span><span class="nb"> union of top two elements on stack </span><span class="o">--</span><span class="nb"> pop </span><span class="m">2</span><span class="nb">, push </span><span class="m">1</span><span class="nb"> </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">{</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\%</span><span class="nb">d} </span><span class="nv">\dotfill</span><span class="nb"> difference of top two elements on stack </span><span class="o">--</span><span class="nb"> pop </span><span class="m">2</span><span class="nb">, push </span><span class="m">1</span><span class="nb"> </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">{</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\%</span><span class="nb">i} </span><span class="nv">\dotfill</span><span class="nb"> intersection of top two elements on stack </span><span class="o">--</span><span class="nb"> pop </span><span class="m">2</span><span class="nb">, push </span><span class="m">1</span><span class="nb"> </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">{</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\%</span><span class="nb">n} </span><span class="nv">\dotfill</span><span class="nb"> inverse of top element on stack </span><span class="o">--</span><span class="nb"> pop </span><span class="m">1</span><span class="nb">, push </span><span class="m">1</span><span class="nb"> </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{block}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Expanding selections}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nb">Selections of cells and wires can be expanded along connections using {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\%</span><span class="nb">}</span><span class="o">-</span><span class="nb">codes</span>
<span class="nb">for selecting input cones </span><span class="o">(</span><span class="nb">{</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\%</span><span class="nb">ci}</span><span class="o">)</span><span class="nb">, output cones </span><span class="o">(</span><span class="nb">{</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\%</span><span class="nb">co}</span><span class="o">)</span><span class="nb">, or both </span><span class="o">(</span><span class="nb">{</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\%</span><span class="nb">x}</span><span class="o">)</span><span class="nb">.</span>

<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb"># select all wires that are inputs to </span><span class="s">$</span>add cells
select t:<span class="s">$</span><span class="nb">add </span><span class="c">%ci w:* %i</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">Additional constraints such as port names can be specified.</span>

<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb"># select all wires that connect a &quot;Q&quot; output with a &quot;D&quot; input</span>
<span class="nb">select c:</span><span class="o">*</span><span class="nb"> </span><span class="c">%co:+[Q] w:* %i c:* %ci:+[D] w:* %i %i</span>

<span class="nb"># select the multiplexer tree that drives the signal &#39;state&#39;</span>
<span class="nb">select state </span><span class="c">%ci*:+$mux,$pmux[A,B,Y]</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">See {</span><span class="nv">\tt</span><span class="nb"> help select} for full documentation of this expressions.</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Incremental selection}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nb">Sometimes a selection can most easily be described by a series of add</span><span class="o">/</span><span class="nb">delete operations.</span>
<span class="nb">The commands {</span><span class="nv">\tt</span><span class="nb"> select </span><span class="o">-</span><span class="nb">add} and {</span><span class="nv">\tt</span><span class="nb"> select </span><span class="o">-</span><span class="nb">del} respectively add or remove objects</span>
<span class="nb">from the current selection instead of overwriting it.</span>

<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">select </span><span class="o">-</span><span class="nb">none            # start with an empty selection</span>
<span class="nb">select </span><span class="o">-</span><span class="nb">add reg_</span><span class="o">*</span><span class="nb">       # select a bunch of objects</span>
<span class="nb">select </span><span class="o">-</span><span class="nb">del reg_</span><span class="m">42</span><span class="nb">      # but not this one</span>
<span class="nb">select </span><span class="o">-</span><span class="nb">add state </span><span class="c">%ci   # and add mor stuff</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">Within a select expression the token {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\%</span><span class="nb">} can be used to push the previous selection</span>
<span class="nb">on the stack.</span>

<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">select t:</span><span class="s">$</span>add t:<span class="s">$</span><span class="nb">sub    # select all </span><span class="s">$</span>add and <span class="s">$</span><span class="nb">sub cells</span>
<span class="nb">select </span><span class="c">% %ci % %d       # select only the input wires to those cells</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Creating selection variables}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nb">Selections can be stored under a name with the {</span><span class="nv">\tt</span><span class="nb"> select </span><span class="o">-</span><span class="nb">set &lt;name&gt;}</span>
<span class="nb">command. The stored selections can be used in later select expressions</span>
<span class="nb">using the syntax {</span><span class="nv">\tt</span><span class="nb"> @&lt;name&gt;}.</span>

<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">select </span><span class="o">-</span><span class="nb">set cone_a state_a </span><span class="c">%ci*:-$dff  # set @cone_a to the input cone of state_a</span>
<span class="nb">select </span><span class="o">-</span><span class="nb">set cone_b state_b </span><span class="c">%ci*:-$dff  # set @cone_b to the input cone of state_b</span>
<span class="nb">select @cone_a @cone_b </span><span class="c">%i              # select the objects that are in both cones</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">Remember that select expressions can also be used directly as arguments to most</span>
<span class="nb">commands. Some commands also except a single select argument to some options.</span>
<span class="nb">In those cases selection variables must be used to capture more complex selections.</span>

<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">dump @cone_a @cone_b</span>

<span class="nb">select </span><span class="o">-</span><span class="nb">set cone_ab @cone_a @cone_b </span><span class="c">%i</span>
<span class="nb">show </span><span class="o">-</span><span class="nb">color red @cone_ab </span><span class="o">-</span><span class="nb">color magenta @cone_a </span><span class="o">-</span><span class="nb">color blue @cone_b</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> Example}</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">4</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">6</span><span class="nb">pt}{</span><span class="m">7</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">select.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">7</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys, frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">select.ys}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\hfil\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="nv">\linewidth</span><span class="nb">,trim</span><span class="o">=</span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm </span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">select.pdf}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="nv">\subsection</span><span class="nb">{Advanced uses of techmap}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span>
<span class="nv">\subsectionpage</span><span class="nb"></span>
<span class="nv">\subsectionpagesuffix</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Introduction to techmap}</span>

<span class="nv">\begin</span><span class="nb">{frame}{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"></span>
<span class="nb">The {</span><span class="nv">\tt</span><span class="nb"> techmap} command replaces cells in the design with implementations given</span>
<span class="nb">as Verilog code </span><span class="o">(</span><span class="nb">called ``map files&#39;&#39;</span><span class="o">)</span><span class="nb">. It can replace Yosys&#39; internal cell</span>
<span class="nb">types </span><span class="o">(</span><span class="nb">such as {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$</span><span class="nb">or}</span><span class="o">)</span><span class="nb"> as well as user</span><span class="o">-</span><span class="nb">defined cell types.</span>
<span class="nv">\medskip\item</span><span class="nb"></span>
<span class="nb">Verilog parameters are used extensively to customize the internal cell types.</span>
<span class="nv">\medskip\item</span><span class="nb"></span>
<span class="nb">Additional special parameters are used by techmap to communicate meta</span><span class="o">-</span><span class="nb">data to the</span>
<span class="nb">map files.</span>
<span class="nv">\medskip\item</span><span class="nb"></span>
<span class="nb">Special wires are used to instruct techmap how to handle a module in the map file.</span>
<span class="nv">\medskip\item</span><span class="nb"></span>
<span class="nb">Generate blocks and recursion are powerful tools for writing map files.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> Example </span><span class="m">1</span><span class="o">/</span><span class="m">2</span><span class="nb">}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm</span>
<span class="nb">To map the Verilog OR</span><span class="o">-</span><span class="nb">reduction operator to </span><span class="m">3</span><span class="o">-</span><span class="nb">input OR gates:</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">0</span><span class="nb">.</span><span class="m">35</span><span class="nv">\linewidth</span><span class="nb">}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, lastline</span><span class="o">=</span><span class="m">24</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">red_or</span><span class="m">3</span><span class="nb">x</span><span class="m">1</span><span class="nb">_map.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">0</span><span class="nb">.</span><span class="m">65</span><span class="nv">\linewidth</span><span class="nb">}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, firstline</span><span class="o">=</span><span class="m">25</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">red_or</span><span class="m">3</span><span class="nb">x</span><span class="m">1</span><span class="nb">_map.v}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> Example </span><span class="m">2</span><span class="o">/</span><span class="m">2</span><span class="nb">}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span>
<span class="nv">\hfil\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">10</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm </span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">red_or</span><span class="m">3</span><span class="nb">x</span><span class="m">1</span><span class="nb">.pdf}</span>
<span class="nv">\vss</span><span class="nb"></span>
<span class="nb">}</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">6</span><span class="nb">cm}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">4</span><span class="nb">cm}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">6</span><span class="nb">cm</span><span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys, firstline</span><span class="o">=</span><span class="m">4</span><span class="nb">, lastline</span><span class="o">=</span><span class="m">4</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">red_or</span><span class="m">3</span><span class="nb">x</span><span class="m">1</span><span class="nb">_test.ys}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm</span><span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">red_or</span><span class="m">3</span><span class="nb">x</span><span class="m">1</span><span class="nb">_test.v}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Conditional techmap}</span>

<span class="nv">\begin</span><span class="nb">{frame}{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> In some cases only cells with certain properties should be substituted.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> The special wire {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">FAIL</span><span class="nv">\_</span><span class="nb">} can be used to disable a module</span>
<span class="nb">in the map file for a certain set of parameters.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> The wire {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">FAIL</span><span class="nv">\_</span><span class="nb">} must be set to a constant value. If it</span>
<span class="nb">is non</span><span class="o">-</span><span class="nb">zero then the module is disabled for this set of parameters.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Example use</span><span class="o">-</span><span class="nb">cases:</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> coarse</span><span class="o">-</span><span class="nb">grain cell types that only operate on certain bit widths</span>
<span class="nv">\item</span><span class="nb"> memory resources for different memory geometries </span><span class="o">(</span><span class="nb">width, depth, ports, etc.</span><span class="o">)</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> Example}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span>
<span class="nv">\hfill\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">6</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm </span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">sym_mul.pdf}</span>
<span class="nv">\vss</span><span class="nb"></span>
<span class="nb">}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">sym_mul_map.v}</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">6</span><span class="nb">cm}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">sym_mul_test.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">4</span><span class="nb">cm}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">ys, lastline</span><span class="o">=</span><span class="m">4</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">sym_mul_test.ys}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Scripting in map modules}</span>

<span class="nv">\begin</span><span class="nb">{frame}{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> The special wires {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">DO</span><span class="nv">\_</span><span class="o">*</span><span class="nb">} can be used to run Yosys scripts</span>
<span class="nb">in the context of the replacement module.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> The wire that comes first in alphabetical oder is interpreted as string </span><span class="o">(</span><span class="nb">must</span>
<span class="nb">be connected to constants</span><span class="o">)</span><span class="nb"> that is executed as script. Then the wire is removed. Repeat.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> You can even call techmap recursively</span><span class="o">!</span><span class="nb"></span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Example use</span><span class="o">-</span><span class="nb">cases:</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> Using always blocks in map module: call {</span><span class="nv">\tt</span><span class="nb"> proc}</span>
<span class="nv">\item</span><span class="nb"> Perform expensive optimizations </span><span class="o">(</span><span class="nb">such as {</span><span class="nv">\tt</span><span class="nb"> freduce}</span><span class="o">)</span><span class="nb"> on cells where</span>
<span class="nb">this is known to work well.</span>
<span class="nv">\item</span><span class="nb"> Interacting with custom commands.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>

<span class="nv">\scriptsize</span><span class="nb"></span>
<span class="nb">PROTIP: Commands such as {</span><span class="nv">\tt</span><span class="nb"> shell}, {</span><span class="nv">\tt</span><span class="nb"> show </span><span class="o">-</span><span class="nb">pause}, and {</span><span class="nv">\tt</span><span class="nb"> dump} can be use</span>
<span class="nb">in the {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">DO</span><span class="nv">\_</span><span class="o">*</span><span class="nb">} scripts for debugging map modules.</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> Example}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span>
<span class="nv">\vskip</span><span class="m">4</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm</span>
<span class="nv">\hskip</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">10</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm </span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">mymul.pdf}</span>
<span class="nv">\vss</span><span class="nb"></span>
<span class="nb">}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">6</span><span class="nb">cm</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">6</span><span class="nb">cm}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">6</span><span class="nb">cm</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">mymul_map.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">4</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">6</span><span class="nb">cm</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">mymul_test.v}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">ys, lastline</span><span class="o">=</span><span class="m">5</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">mymul_test.ys}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">ys, firstline</span><span class="o">=</span><span class="m">7</span><span class="nb">, lastline</span><span class="o">=</span><span class="m">12</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">mymul_test.ys}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Handling constant inputs}</span>

<span class="nv">\begin</span><span class="nb">{frame}{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> The special parameters {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">CONSTMSK</span><span class="nv">\_\it</span><span class="nb"> &lt;port</span><span class="o">-</span><span class="nb">name&gt;</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">} and</span>
<span class="nb">{</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">CONSTVAL</span><span class="nv">\_\it</span><span class="nb"> &lt;port</span><span class="o">-</span><span class="nb">name&gt;</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">} can be used to handle constant</span>
<span class="nb">input values to cells.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> The former contains </span><span class="m">1</span><span class="o">-</span><span class="nb">bits for all constant input bits on the port.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> The latter contains the constant bits or undef </span><span class="o">(</span><span class="nb">x</span><span class="o">)</span><span class="nb"> for non</span><span class="o">-</span><span class="nb">constant bits.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Example use</span><span class="o">-</span><span class="nb">cases:</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> Converting arithmetic </span><span class="o">(</span><span class="nb">for example multiply to shift</span><span class="o">)</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Identify constant addresses or enable bits in memory interfaces.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> Example}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span>
<span class="nv">\vskip</span><span class="m">5</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm</span>
<span class="nv">\hskip</span><span class="m">6</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm </span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">mulshift.pdf}</span>
<span class="nv">\vss</span><span class="nb"></span>
<span class="nb">}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">6</span><span class="nb">cm</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">6</span><span class="nb">cm}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">4</span><span class="nb">cm</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">mulshift_map.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">4</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">6</span><span class="nb">cm</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">mulshift_test.v}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">ys, lastline</span><span class="o">=</span><span class="m">5</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">mulshift_test.ys}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Handling shorted inputs}</span>

<span class="nv">\begin</span><span class="nb">{frame}{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> The special parameters {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">BITS</span><span class="nv">\_</span><span class="nb">CONNMAP</span><span class="nv">\_</span><span class="nb">} and</span>
<span class="nb">{</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">CONNMAP</span><span class="nv">\_\it</span><span class="nb"> &lt;port</span><span class="o">-</span><span class="nb">name&gt;</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">} can be used to handle shorted inputs.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Each bit of the port correlates to an {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">BITS</span><span class="nv">\_</span><span class="nb">CONNMAP</span><span class="nv">\_</span><span class="nb">} bits wide</span>
<span class="nb">number in {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">CONNMAP</span><span class="nv">\_\it</span><span class="nb"> &lt;port</span><span class="o">-</span><span class="nb">name&gt;</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">}.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Each unique signal bit is assigned its own number. Identical fields in the {</span><span class="nv">\tt</span><span class="nb"></span>
<span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">CONNMAP</span><span class="nv">\_\it</span><span class="nb"> &lt;port</span><span class="o">-</span><span class="nb">name&gt;</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">} parameters mean shorted signal bits.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> The numbers </span><span class="m">0</span><span class="o">-</span><span class="m">3</span><span class="nb"> are reserved for {</span><span class="nv">\tt</span><span class="nb"> </span><span class="m">0</span><span class="nb">}, {</span><span class="nv">\tt</span><span class="nb"> </span><span class="m">1</span><span class="nb">}, {</span><span class="nv">\tt</span><span class="nb"> x}, and {</span><span class="nv">\tt</span><span class="nb"> z} respectively.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Example use</span><span class="o">-</span><span class="nb">cases:</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> Detecting shared clock or control signals in memory interfaces.</span>
<span class="nv">\item</span><span class="nb"> In some cases this can be used for for optimization.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> Example}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span>
<span class="nv">\vskip</span><span class="m">4</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span>
<span class="nv">\hskip</span><span class="m">6</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm </span><span class="m">0</span><span class="nb"> </span><span class="m">0</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">addshift.pdf}</span>
<span class="nv">\vss</span><span class="nb"></span>
<span class="nb">}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">6</span><span class="nb">cm</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">6</span><span class="nb">cm}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">4</span><span class="nb">cm</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">addshift_map.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">4</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">6</span><span class="nb">cm</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">addshift_test.v}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">ys, lastline</span><span class="o">=</span><span class="m">5</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">addshift_test.ys}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Notes on using techmap}</span>

<span class="nv">\begin</span><span class="nb">{frame}{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> Don&#39;t use positional cell parameters in map modules.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Don&#39;t try to implement basic logic optimization with techmap. </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">{</span><span class="nv">\small</span><span class="nb"> </span><span class="o">(</span><span class="nb">So the OR</span><span class="o">-</span><span class="nb">reduce using OR</span><span class="m">3</span><span class="nb">X</span><span class="m">1</span><span class="nb"> cells map was actually a bad example.</span><span class="o">)</span><span class="nb">}</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> You can use the {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$\_\,\_</span><span class="nb">}</span><span class="o">-</span><span class="nb">prefix for internal cell types to avoid</span>
<span class="nb">collisions with the user</span><span class="o">-</span><span class="nb">namespace. But always use two underscores or the</span>
<span class="nb">internal consistency checker will trigger on this cells.</span>
<span class="nv">\medskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Techmap has two major use cases:</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> Creating good logic</span><span class="o">-</span><span class="nb">level representation of arithmetic functions. </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">This also means using dedicated hardware resources such as half</span><span class="o">-</span><span class="nb"> and full</span><span class="o">-</span><span class="nb">adder</span>
<span class="nb">cells in ASICS or dedicated carry logic in FPGAs.</span>
<span class="nv">\smallskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> Mapping of coarse</span><span class="o">-</span><span class="nb">grain resources such as block memory or DSP cells.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="nv">\subsection</span><span class="nb">{Coarse</span><span class="o">-</span><span class="nb">grain synthesis}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span>
<span class="nv">\subsectionpage</span><span class="nb"></span>
<span class="nv">\subsectionpagesuffix</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Intro to coarse</span><span class="o">-</span><span class="nb">grain synthesis}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nb">In coarse</span><span class="o">-</span><span class="nb">grain synthesis the target architecture has cells of the same</span>
<span class="nb">complexity or larger complexity than the internal RTL representation.</span>

<span class="nb">For example:</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb"></span>
<span class="nb">	wire </span><span class="o">[</span><span class="m">15</span><span class="nb">:</span><span class="m">0</span><span class="o">]</span><span class="nb"> a, b;</span>
<span class="nb">	wire </span><span class="o">[</span><span class="m">31</span><span class="nb">:</span><span class="m">0</span><span class="o">]</span><span class="nb"> c, y;</span>
<span class="nb">	assign y </span><span class="o">=</span><span class="nb"> a </span><span class="o">*</span><span class="nb"> b </span><span class="o">+</span><span class="nb"> c;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nb">This circuit contains two cells in the RTL representation: one multiplier and</span>
<span class="nb">one adder. In some architectures this circuit can be implemented using</span>
<span class="nb">a single circuit element, for example an FPGA DSP core. Coarse grain synthesis</span>
<span class="nb">is this mapping of groups of circuit elements to larger components.</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">Fine</span><span class="o">-</span><span class="nb">grain synthesis would be matching the circuit elements to smaller</span>
<span class="nb">components, such as LUTs, gates, or half</span><span class="o">-</span><span class="nb"> and full</span><span class="o">-</span><span class="nb">adders.</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{The extract pass}</span>

<span class="nv">\begin</span><span class="nb">{frame}{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> Like the {</span><span class="nv">\tt</span><span class="nb"> techmap} pass, the {</span><span class="nv">\tt</span><span class="nb"> extract} pass is called with</span>
<span class="nb">a map file. It compares the circuits inside the modules of the map file</span>
<span class="nb">with the design and looks for sub</span><span class="o">-</span><span class="nb">circuits in the design that match any</span>
<span class="nb">of the modules in the map file.</span>
<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> If a match is found, the {</span><span class="nv">\tt</span><span class="nb"> extract} pass will replace the matching</span>
<span class="nb">subcircuit with an instance of the module from the map file.</span>
<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nv">\item</span><span class="nb"> In a way the {</span><span class="nv">\tt</span><span class="nb"> extract} pass is the inverse of the techmap pass.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> Example </span><span class="m">1</span><span class="o">/</span><span class="m">2</span><span class="nb">}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span>
<span class="nv">\vskip</span><span class="m">2</span><span class="nb">cm</span>
<span class="nv">\begin</span><span class="nb">{tikzpicture}</span>
<span class="nb">    </span><span class="nv">\node</span><span class="nb"> at </span><span class="o">(</span><span class="m">0</span><span class="nb">,</span><span class="m">0</span><span class="o">)</span><span class="nb"> {</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_simple_test_</span><span class="m">00</span><span class="nb">a.pdf}};</span>
<span class="nb">    </span><span class="nv">\node</span><span class="nb"> at </span><span class="o">(</span><span class="m">3</span><span class="nb">,</span><span class="o">-</span><span class="m">3</span><span class="o">)</span><span class="nb"> {</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">8</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_simple_test_</span><span class="m">00</span><span class="nb">b.pdf}};</span>
<span class="nb">    </span><span class="nv">\draw</span><span class="o">[</span><span class="nb">yshift</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm,thick,</span><span class="o">-</span><span class="nb">latex</span><span class="o">]</span><span class="nb"> </span><span class="o">(</span><span class="m">1</span><span class="nb">,</span><span class="o">-</span><span class="m">1</span><span class="o">)</span><span class="nb"> </span><span class="o">--</span><span class="nb"> </span><span class="o">(</span><span class="m">2</span><span class="nb">,</span><span class="o">-</span><span class="m">2</span><span class="o">)</span><span class="nb">;</span>
<span class="nv">\end</span><span class="nb">{tikzpicture}</span>
<span class="nv">\vss</span><span class="nb">}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">1</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_simple_test.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_simple_xmap.v}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, frame</span><span class="o">=</span><span class="nb">single, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">read_verilog macc_simple_test.v</span>
<span class="nb">hierarchy </span><span class="o">-</span><span class="nb">check </span><span class="o">-</span><span class="nb">top test</span>

<span class="nb">extract </span><span class="o">-</span><span class="nb">map macc_simple_xmap.v;;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> Example </span><span class="m">2</span><span class="o">/</span><span class="m">2</span><span class="nb">}</span>
<span class="nv">\hfil\begin</span><span class="nb">{tabular}{cc}</span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\hbox</span><span class="nb"> to </span><span class="m">5</span><span class="nb">cm {</span><span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_simple_test_</span><span class="m">01</span><span class="nb">.v}}} &amp;</span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\hbox</span><span class="nb"> to </span><span class="m">5</span><span class="nb">cm {</span><span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_simple_test_</span><span class="m">02</span><span class="nb">.v}}} </span><span class="nv">\\</span><span class="nb"></span>
<span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> &amp; </span><span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_simple_test_</span><span class="m">01</span><span class="nb">a.pdf}} &amp;</span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_simple_test_</span><span class="m">02</span><span class="nb">a.pdf}} </span><span class="nv">\\</span><span class="nb"></span>
<span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> &amp; </span><span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_simple_test_</span><span class="m">01</span><span class="nb">b.pdf}} &amp;</span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_simple_test_</span><span class="m">02</span><span class="nb">b.pdf}} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{tabular}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{The wrap</span><span class="o">-</span><span class="nb">extract</span><span class="o">-</span><span class="nb">unwrap method}</span>

<span class="nv">\begin</span><span class="nb">{frame}{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nv">\scriptsize</span><span class="nb"></span>
<span class="nb">Often a coarse</span><span class="o">-</span><span class="nb">grain element has a constant bit</span><span class="o">-</span><span class="nb">width, but can be used to</span>
<span class="nb">implement operations with a smaller bit</span><span class="o">-</span><span class="nb">width. For example, a </span><span class="m">18</span><span class="nb">x</span><span class="m">25</span><span class="o">-</span><span class="nb">bit multiplier</span>
<span class="nb">can also be used to implement </span><span class="m">16</span><span class="nb">x</span><span class="m">20</span><span class="o">-</span><span class="nb">bit multiplication.</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">A way of mapping such elements in coarse grain synthesis is the wrap</span><span class="o">-</span><span class="nb">extract</span><span class="o">-</span><span class="nb">unwrap method:</span>

<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> {</span><span class="nv">\bf</span><span class="nb"> wrap} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">Identify candidate</span><span class="o">-</span><span class="nb">cells in the circuit and wrap them in a cell with a constant</span>
<span class="nb">wider bit</span><span class="o">-</span><span class="nb">width using {</span><span class="nv">\tt</span><span class="nb"> techmap}. The wrappers use the same parameters as the original cell, so</span>
<span class="nb">the information about the original width of the ports is preserved. </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">Then use the {</span><span class="nv">\tt</span><span class="nb"> connwrappers} command to connect up the bit</span><span class="o">-</span><span class="nb">extended in</span><span class="o">-</span><span class="nb"> and</span>
<span class="nb">outputs of the wrapper cells.</span>
<span class="nv">\item</span><span class="nb"> {</span><span class="nv">\bf</span><span class="nb"> extract} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">Now all operations are encoded using the same bit</span><span class="o">-</span><span class="nb">width as the coarse grain element. The {</span><span class="nv">\tt</span><span class="nb"></span>
<span class="nb">extract} command can be used to replace circuits with cells of the target architecture.</span>
<span class="nv">\item</span><span class="nb"> {</span><span class="nv">\bf</span><span class="nb"> unwrap} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">The remaining wrapper cell can be unwrapped using {</span><span class="nv">\tt</span><span class="nb"> techmap}.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>

<span class="nv">\bigskip</span><span class="nb"></span>
<span class="nb">The following sides detail an example that shows how to map MACC operations of</span>
<span class="nb">arbitrary size to MACC cells with a </span><span class="m">18</span><span class="nb">x</span><span class="m">25</span><span class="o">-</span><span class="nb">bit multiplier and a </span><span class="m">48</span><span class="o">-</span><span class="nb">bit adder </span><span class="o">(</span><span class="nb">such as</span>
<span class="nb">the Xilinx DSP</span><span class="m">48</span><span class="nb"> cells</span><span class="o">)</span><span class="nb">.</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Example: DSP</span><span class="m">48</span><span class="nv">\_</span><span class="nb">MACC}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">1</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nb">Preconditioning: {</span><span class="nv">\tt</span><span class="nb"> macc</span><span class="nv">\_</span><span class="nb">xilinx</span><span class="nv">\_</span><span class="nb">swap</span><span class="nv">\_</span><span class="nb">map.v} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">Make sure {</span><span class="nv">\tt</span><span class="nb"> A} is the smaller port on all multipliers</span>

<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, lastline</span><span class="o">=</span><span class="m">15</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_swap_map.v}</span>
<span class="nv">\column</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, firstline</span><span class="o">=</span><span class="m">16</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_swap_map.v}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">2</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nb">Wrapping multipliers: {</span><span class="nv">\tt</span><span class="nb"> macc</span><span class="nv">\_</span><span class="nb">xilinx</span><span class="nv">\_</span><span class="nb">wrap</span><span class="nv">\_</span><span class="nb">map.v}</span>

<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, lastline</span><span class="o">=</span><span class="m">23</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_wrap_map.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, firstline</span><span class="o">=</span><span class="m">24</span><span class="nb">, lastline</span><span class="o">=</span><span class="m">46</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_wrap_map.v}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">3</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nb">Wrapping adders: {</span><span class="nv">\tt</span><span class="nb"> macc</span><span class="nv">\_</span><span class="nb">xilinx</span><span class="nv">\_</span><span class="nb">wrap</span><span class="nv">\_</span><span class="nb">map.v}</span>

<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, firstline</span><span class="o">=</span><span class="m">48</span><span class="nb">, lastline</span><span class="o">=</span><span class="m">67</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_wrap_map.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, firstline</span><span class="o">=</span><span class="m">68</span><span class="nb">, lastline</span><span class="o">=</span><span class="m">89</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_wrap_map.v}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">4</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nb">Extract: {</span><span class="nv">\tt</span><span class="nb"> macc</span><span class="nv">\_</span><span class="nb">xilinx</span><span class="nv">\_</span><span class="nb">xmap.v}</span>

<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">xleftmargin</span><span class="o">=</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, firstline</span><span class="o">=</span><span class="m">1</span><span class="nb">,  lastline</span><span class="o">=</span><span class="m">17</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_xmap.v}</span>

<span class="nb">.. simply use the same wrapping commands on this module as on the design to create a template for the {</span><span class="nv">\tt</span><span class="nb"> extract} command.</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">5</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nb">Unwrapping multipliers: {</span><span class="nv">\tt</span><span class="nb"> macc</span><span class="nv">\_</span><span class="nb">xilinx</span><span class="nv">\_</span><span class="nb">unwrap</span><span class="nv">\_</span><span class="nb">map.v}</span>

<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, firstline</span><span class="o">=</span><span class="m">1</span><span class="nb">,  lastline</span><span class="o">=</span><span class="m">17</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_unwrap_map.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, firstline</span><span class="o">=</span><span class="m">18</span><span class="nb">, lastline</span><span class="o">=</span><span class="m">30</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_unwrap_map.v}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">6</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nb">Unwrapping adders: {</span><span class="nv">\tt</span><span class="nb"> macc</span><span class="nv">\_</span><span class="nb">xilinx</span><span class="nv">\_</span><span class="nb">unwrap</span><span class="nv">\_</span><span class="nb">map.v}</span>

<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, firstline</span><span class="o">=</span><span class="m">32</span><span class="nb">, lastline</span><span class="o">=</span><span class="m">48</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_unwrap_map.v}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">7</span><span class="nb">pt}{</span><span class="m">8</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog, firstline</span><span class="o">=</span><span class="m">49</span><span class="nb">, lastline</span><span class="o">=</span><span class="m">61</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_unwrap_map.v}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">7</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nv">\hfil\begin</span><span class="nb">{tabular}{cc}</span>
<span class="nb">{</span><span class="nv">\tt</span><span class="nb"> test</span><span class="m">1</span><span class="nb">} &amp; {</span><span class="nv">\tt</span><span class="nb"> test</span><span class="m">2</span><span class="nb">} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\hbox</span><span class="nb"> to </span><span class="m">5</span><span class="nb">cm {</span><span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, firstline</span><span class="o">=</span><span class="m">1</span><span class="nb">, lastline</span><span class="o">=</span><span class="m">6</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test.v}}} &amp;</span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\hbox</span><span class="nb"> to </span><span class="m">5</span><span class="nb">cm {</span><span class="nv">\lstinputlisting</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, firstline</span><span class="o">=</span><span class="m">8</span><span class="nb">, lastline</span><span class="o">=</span><span class="m">13</span><span class="nb">, language</span><span class="o">=</span><span class="nb">verilog</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test.v}}} </span><span class="nv">\\</span><span class="nb"></span>
<span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> &amp; </span><span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{tabular}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">                            read_verilog macc_xilinx_test.v</span>
<span class="nb">                            hierarchy </span><span class="o">-</span><span class="nb">check</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span>
<span class="nv">\hfil\begin</span><span class="nb">{tabular}{cc}</span>
<span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> &amp; </span><span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">1</span><span class="nb">a.pdf}} &amp;</span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">2</span><span class="nb">a.pdf}} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{tabular}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">8</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nv">\hfil\begin</span><span class="nb">{tabular}{cc}</span>
<span class="nb">{</span><span class="nv">\tt</span><span class="nb"> test</span><span class="m">1</span><span class="nb">} &amp; {</span><span class="nv">\tt</span><span class="nb"> test</span><span class="m">2</span><span class="nb">} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">1</span><span class="nb">a.pdf}} &amp;</span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">2</span><span class="nb">a.pdf}} </span><span class="nv">\\</span><span class="nb"></span>
<span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> &amp; </span><span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{tabular}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">                         techmap </span><span class="o">-</span><span class="nb">map macc_xilinx_swap_map.v ;;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">2</span><span class="nb">cm</span>
<span class="nv">\hfil\begin</span><span class="nb">{tabular}{cc}</span>
<span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> &amp; </span><span class="s">$</span><span class="k">\downarrow</span><span class="s">$</span><span class="nb"> </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">1</span><span class="nb">b.pdf}} &amp;</span>
<span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">2</span><span class="nb">b.pdf}} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{tabular}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">9</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nb">Wrapping in {</span><span class="nv">\tt</span><span class="nb"> test</span><span class="m">1</span><span class="nb">}:</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span><span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">4</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">1</span><span class="nb">b.pdf}}</span><span class="nv">\vss</span><span class="nb">}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">6</span><span class="nb">cm}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">techmap </span><span class="o">-</span><span class="nb">map macc_xilinx_wrap_map.v</span>

<span class="nb">connwrappers </span><span class="o">-</span><span class="nb">unsigned </span><span class="s">$</span><span class="nb">__</span>mul<span class="nb">_</span>wrapper <span class="k">\</span>
                            Y Y<span class="nb">_</span>WIDTH <span class="k">\</span>
             -unsigned <span class="s">$</span><span class="nb">__add_wrapper </span><span class="err">\</span><span class="nb"></span>
<span class="nb">                            Y Y_WIDTH ;;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>

<span class="nv">\vskip</span><span class="m">1</span><span class="nb">cm</span>
<span class="nv">\hfil\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="nv">\linewidth</span><span class="nb">,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">1</span><span class="nb">c.pdf}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">10</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nb">Wrapping in {</span><span class="nv">\tt</span><span class="nb"> test</span><span class="m">2</span><span class="nb">}:</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span><span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">4</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">2</span><span class="nb">b.pdf}}</span><span class="nv">\vss</span><span class="nb">}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">6</span><span class="nb">cm}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">techmap </span><span class="o">-</span><span class="nb">map macc_xilinx_wrap_map.v</span>

<span class="nb">connwrappers </span><span class="o">-</span><span class="nb">unsigned </span><span class="s">$</span><span class="nb">__</span>mul<span class="nb">_</span>wrapper <span class="k">\</span>
                            Y Y<span class="nb">_</span>WIDTH <span class="k">\</span>
             -unsigned <span class="s">$</span><span class="nb">__add_wrapper </span><span class="err">\</span><span class="nb"></span>
<span class="nb">                            Y Y_WIDTH ;;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>

<span class="nv">\vskip</span><span class="m">1</span><span class="nb">cm</span>
<span class="nv">\hfil\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="nv">\linewidth</span><span class="nb">,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">2</span><span class="nb">c.pdf}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">11</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nb">Extract in {</span><span class="nv">\tt</span><span class="nb"> test</span><span class="m">1</span><span class="nb">}:</span>
<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">4</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">design </span><span class="o">-</span><span class="nb">push</span>
<span class="nb">read_verilog macc_xilinx_xmap.v</span>
<span class="nb">techmap </span><span class="o">-</span><span class="nb">map macc_xilinx_swap_map.v</span>
<span class="nb">techmap </span><span class="o">-</span><span class="nb">map macc_xilinx_wrap_map.v;;</span>
<span class="nb">design </span><span class="o">-</span><span class="nb">save __macc_xilinx_xmap</span>
<span class="nb">design </span><span class="o">-</span><span class="nb">pop</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\vss</span><span class="nb">}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">5</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm}</span>
<span class="nv">\vskip</span><span class="o">-</span><span class="m">1</span><span class="nb">cm</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">extract </span><span class="o">-</span><span class="nb">constports </span><span class="o">-</span><span class="nb">ignore_parameters </span><span class="err">\</span><span class="nb"></span>
<span class="nb">        </span><span class="o">-</span><span class="nb">map </span><span class="c">%__macc_xilinx_xmap       \</span>
<span class="nb">        </span><span class="o">-</span><span class="nb">swap </span><span class="s">$</span><span class="nb">__</span>add<span class="nb">_</span>wrapper A,B ;;
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\vbox</span> to 0cm<span class="nb">{</span><span class="k">\fbox</span><span class="nb">{</span><span class="k">\includegraphics</span><span class="na">[width=4.5cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExAdv/macc<span class="nb">_</span>xilinx<span class="nb">_</span>test1c.pdf<span class="nb">}}</span><span class="k">\vss</span><span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>columns<span class="nb">}</span>

<span class="k">\vskip</span>2cm
<span class="k">\hfil\includegraphics</span><span class="na">[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]</span><span class="nb">{</span>PRESENTATION<span class="nb">_</span>ExAdv/macc<span class="nb">_</span>xilinx<span class="nb">_</span>test1d.pdf<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}</span>[t, fragile]<span class="nb">{</span><span class="k">\subsubsecname</span><span class="nb">{}</span> -- 12/13<span class="nb">}</span>
Extract in <span class="nb">{</span><span class="k">\tt</span> test2<span class="nb">}</span>:
<span class="k">\begin</span><span class="nb">{</span>columns<span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>4.5cm<span class="nb">}</span>
<span class="k">\vbox</span> to 0cm<span class="nb">{</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[linewidth=5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
design -push
read<span class="nb">_</span>verilog macc<span class="nb">_</span>xilinx<span class="nb">_</span>xmap.v
techmap -map macc<span class="nb">_</span>xilinx<span class="nb">_</span>swap<span class="nb">_</span>map.v
techmap -map macc<span class="nb">_</span>xilinx<span class="nb">_</span>wrap<span class="nb">_</span>map.v;;
design -save <span class="nb">__</span>macc<span class="nb">_</span>xilinx<span class="nb">_</span>xmap
design -pop
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\vss</span><span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>5.5cm<span class="nb">}</span>
<span class="k">\vskip</span>-1cm
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[linewidth=5.5cm, basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=ys]
extract -constports -ignore<span class="nb">_</span>parameters <span class="k">\</span>
        -map <span class="c">%__macc_xilinx_xmap       \</span>
        -swap <span class="s">$</span><span class="nb">__add_wrapper A,B ;;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span><span class="nv">\fbox</span><span class="nb">{</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">4</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">2</span><span class="nb">c.pdf}}</span><span class="nv">\vss</span><span class="nb">}</span>
<span class="nv">\end</span><span class="nb">{columns}</span>

<span class="nv">\vskip</span><span class="m">2</span><span class="nb">cm</span>
<span class="nv">\hfil\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">11</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">2</span><span class="nb">d.pdf}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">{} </span><span class="o">--</span><span class="nb"> </span><span class="m">13</span><span class="o">/</span><span class="m">13</span><span class="nb">}</span>
<span class="nb">Unwrap in {</span><span class="nv">\tt</span><span class="nb"> test</span><span class="m">2</span><span class="nb">}:</span>

<span class="nv">\hfil\begin</span><span class="nb">{tikzpicture}</span>
<span class="nv">\node</span><span class="nb"> at </span><span class="o">(</span><span class="m">0</span><span class="nb">,</span><span class="m">0</span><span class="o">)</span><span class="nb"> {</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">11</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">2</span><span class="nb">d.pdf}};</span>
<span class="nv">\node</span><span class="nb"> at </span><span class="o">(</span><span class="m">0</span><span class="nb">,</span><span class="o">-</span><span class="m">4</span><span class="o">)</span><span class="nb"> {</span><span class="nv">\includegraphics</span><span class="o">[</span><span class="nb">width</span><span class="o">=</span><span class="m">8</span><span class="nb">cm,trim</span><span class="o">=</span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm </span><span class="m">1</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm</span><span class="o">]</span><span class="nb">{PRESENTATION_ExAdv</span><span class="o">/</span><span class="nb">macc_xilinx_test</span><span class="m">2</span><span class="nb">e.pdf}};</span>
<span class="nv">\node</span><span class="nb"> at </span><span class="o">(</span><span class="m">1</span><span class="nb">,</span><span class="o">-</span><span class="m">1</span><span class="nb">.</span><span class="m">7</span><span class="o">)</span><span class="nb"> {</span><span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">linewidth</span><span class="o">=</span><span class="m">5</span><span class="nb">.</span><span class="m">5</span><span class="nb">cm, frame</span><span class="o">=</span><span class="nb">single, basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">ys</span><span class="o">]</span><span class="nb"></span>
<span class="nb">techmap </span><span class="o">-</span><span class="nb">map macc_xilinx_unwrap_map.v ;;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}};</span>
<span class="nv">\draw</span><span class="o">[-</span><span class="nb">latex</span><span class="o">]</span><span class="nb"> </span><span class="o">(</span><span class="m">4</span><span class="nb">,</span><span class="o">-</span><span class="m">0</span><span class="nb">.</span><span class="m">7</span><span class="o">)</span><span class="nb"> .. controls </span><span class="o">(</span><span class="m">5</span><span class="nb">,</span><span class="o">-</span><span class="m">1</span><span class="nb">.</span><span class="m">7</span><span class="o">)</span><span class="nb"> .. </span><span class="o">(</span><span class="m">4</span><span class="nb">,</span><span class="o">-</span><span class="m">2</span><span class="nb">.</span><span class="m">7</span><span class="o">)</span><span class="nb">;</span>
<span class="nv">\end</span><span class="nb">{tikzpicture}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>


<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="nv">\subsection</span><span class="nb">{Automatic design changes}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span>
<span class="nv">\subsectionpage</span><span class="nb"></span>
<span class="nv">\subsectionpagesuffix</span><span class="nb"></span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Changing the design from Yosys}</span>

<span class="nv">\begin</span><span class="nb">{frame}{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nb">Yosys commands can be used to change the design in memory. Examples of this are:</span>

<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> {</span><span class="nv">\bf</span><span class="nb"> Changes in design hierarchy} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">Commands such as {</span><span class="nv">\tt</span><span class="nb"> flatten} and {</span><span class="nv">\tt</span><span class="nb"> submod} can be used to change the design hierarchy, i.e.</span>
<span class="nb">flatten the hierarchy or moving parts of a module to a submodule. This has applications in synthesis</span>
<span class="nb">scripts as well as in reverse engineering and analysis.</span>

<span class="nv">\item</span><span class="nb"> {</span><span class="nv">\bf</span><span class="nb"> Behavioral changes} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">Commands such as {</span><span class="nv">\tt</span><span class="nb"> techmap} can be used to make behavioral changes to the design, for example</span>
<span class="nb">changing asynchronous resets to synchronous resets. This has applications in design space exploration</span>
<span class="o">(</span><span class="nb">evaluation of various architectures for one circuit</span><span class="o">)</span><span class="nb">.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{frame}</span>

<span class="nv">\subsubsection</span><span class="nb">{Example: Async reset to sync reset}</span>

<span class="nv">\begin</span><span class="nb">{frame}</span><span class="o">[</span><span class="nb">t, fragile</span><span class="o">]</span><span class="nb">{</span><span class="nv">\subsubsecname</span><span class="nb">}</span>
<span class="nb">The following techmap map file replaces all positive</span><span class="o">-</span><span class="nb">edge async reset flip</span><span class="o">-</span><span class="nb">flops with</span>
<span class="nb">positive</span><span class="o">-</span><span class="nb">edge sync reset flip</span><span class="o">-</span><span class="nb">flops. The code is taken from the example Yosys script</span>
<span class="nb">for ASIC synthesis of the Amber ARMv</span><span class="m">2</span><span class="nb"> CPU.</span>

<span class="nv">\begin</span><span class="nb">{columns}</span>
<span class="nv">\column</span><span class="o">[</span><span class="nb">t</span><span class="o">]</span><span class="nb">{</span><span class="m">6</span><span class="nb">cm}</span>
<span class="nv">\vbox</span><span class="nb"> to </span><span class="m">0</span><span class="nb">cm{</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">basicstyle</span><span class="o">=</span><span class="nv">\ttfamily\fontsize</span><span class="nb">{</span><span class="m">8</span><span class="nb">pt}{</span><span class="m">10</span><span class="nb">pt}</span><span class="nv">\selectfont</span><span class="nb">, language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb"></span>
<span class="o">(*</span><span class="nb"> techmap_celltype </span><span class="o">=</span><span class="nb"> &quot;</span><span class="s">$</span>adff&quot; *)
module adff2dff (CLK, ARST, D, Q);

    parameter WIDTH = 1;
    parameter CLK<span class="nb">_</span>POLARITY = 1;
    parameter ARST<span class="nb">_</span>POLARITY = 1;
    parameter ARST<span class="nb">_</span>VALUE = 0;

    input CLK, ARST;
    input [WIDTH-1:0] D;
    output reg [WIDTH-1:0] Q;

    wire [1023:0] <span class="nb">_</span>TECHMAP<span class="nb">_</span>DO<span class="nb">_</span> = &quot;proc&quot;;

    wire <span class="nb">_</span>TECHMAP<span class="nb">_</span>FAIL<span class="nb">_</span> = !CLK<span class="nb">_</span>POLARITY || !ARST<span class="nb">_</span>POLARITY;
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\vss</span><span class="nb">}</span>
<span class="k">\column</span><span class="na">[t]</span><span class="nb">{</span>4cm<span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[basicstyle=<span class="k">\ttfamily\fontsize</span><span class="nb">{</span>8pt<span class="nb">}{</span>10pt<span class="nb">}</span><span class="k">\selectfont</span>, language=Verilog]
// ..continued..


    always @(posedge CLK)
        if (ARST)
            Q &lt;= ARST<span class="nb">_</span>VALUE;
        else
             &lt;= D;

endmodule
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>columns<span class="nb">}</span>

<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\subsection</span><span class="nb">{</span>Summary<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>frame<span class="nb">}{</span><span class="k">\subsecname</span><span class="nb">}</span>
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> A lot can be achieved in Yosys just with the standard set of commands.
<span class="k">\item</span> The commands <span class="nb">{</span><span class="k">\tt</span> techmap<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> extract<span class="nb">}</span> can be used to prototype many complex synthesis tasks.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

<span class="k">\bigskip</span>
<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>center<span class="nb">}</span>
Questions?
<span class="k">\end</span><span class="nb">{</span>center<span class="nb">}</span>

<span class="k">\bigskip</span>
<span class="k">\bigskip</span>
<span class="k">\begin</span><span class="nb">{</span>center<span class="nb">}</span>
<span class="k">\url</span><span class="nb">{</span>http://www.clifford.at/yosys/<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>center<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>frame<span class="nb">}</span>
</pre></div>
</code></pre></td></tr></table>
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