<!DOCTYPE html>
<html lang='en'>
<head>
<title>xen/xen - xen</title>
<meta name='generator' content='cgit v1.2.3'/>
<meta name='robots' content='index, nofollow'/>
<link rel='stylesheet' type='text/css' href='/cgit.css'/>
<link rel='shortcut icon' href='/favicon.ico'/>
<link rel='alternate' title='Atom feed' href='http://git.panaceas.org/cgit.cgi/xen/xen/atom/xen/xsm/acm/acm_xsm_hooks.c?h=master' type='application/atom+xml'/>
<link rel='vcs-git' href='git://git.panaceas.org/xen/xen' title='xen/xen Git repository'/>
<link rel='vcs-git' href='ssh://git@git.panaceas.org/git/xen/xen' title='xen/xen Git repository'/>
</head>
<body>
<div id='cgit'><table id='header'>
<tr>
<td class='logo' rowspan='2'><a href='/cgit.cgi/'><img src='/cgit.png' alt='cgit logo'/></a></td>
<td class='main'><a href='/cgit.cgi/'>index</a> : <a title='xen/xen' href='/cgit.cgi/xen/xen/'>xen/xen</a></td><td class='form'><form method='get'>
<input type='hidden' name='id' value='6102cace934c5ef156e7e1e21966cf3950dc40e5'/><select name='h' onchange='this.form.submit();'>
<option value='master' selected='selected'>master</option>
<option value='stable-4.0'>stable-4.0</option>
<option value='stable-4.1'>stable-4.1</option>
<option value='stable-4.2'>stable-4.2</option>
<option value='stable-4.3'>stable-4.3</option>
<option value='staging'>staging</option>
<option value='staging-4.0'>staging-4.0</option>
<option value='staging-4.1'>staging-4.1</option>
<option value='staging-4.2'>staging-4.2</option>
<option value='staging-4.3'>staging-4.3</option>
</select> <input type='submit' value='switch'/></form></td></tr>
<tr><td class='sub'>xen</td><td class='sub right'>James</td></tr></table>
<table class='tabs'><tr><td>
<a href='/cgit.cgi/xen/xen/about/'>about</a><a href='/cgit.cgi/xen/xen/'>summary</a><a href='/cgit.cgi/xen/xen/refs/?id=6102cace934c5ef156e7e1e21966cf3950dc40e5'>refs</a><a href='/cgit.cgi/xen/xen/log/xen/xsm/acm/acm_xsm_hooks.c'>log</a><a href='/cgit.cgi/xen/xen/tree/xen/xsm/acm/acm_xsm_hooks.c?id=6102cace934c5ef156e7e1e21966cf3950dc40e5'>tree</a><a href='/cgit.cgi/xen/xen/commit/xen/xsm/acm/acm_xsm_hooks.c?id=6102cace934c5ef156e7e1e21966cf3950dc40e5'>commit</a><a class='active' href='/cgit.cgi/xen/xen/diff/xen/xsm/acm/acm_xsm_hooks.c?id=6102cace934c5ef156e7e1e21966cf3950dc40e5'>diff</a><a href='/cgit.cgi/xen/xen/stats/xen/xsm/acm/acm_xsm_hooks.c'>stats</a></td><td class='form'><form class='right' method='get' action='/cgit.cgi/xen/xen/log/xen/xsm/acm/acm_xsm_hooks.c'>
<input type='hidden' name='id' value='6102cace934c5ef156e7e1e21966cf3950dc40e5'/><select name='qt'>
<option value='grep'>log msg</option>
<option value='author'>author</option>
<option value='committer'>committer</option>
<option value='range'>range</option>
</select>
<input class='txt' type='search' size='10' name='q' value=''/>
<input type='submit' value='search'/>
</form>
</td></tr></table>
<div class='path'>path: <a href='/cgit.cgi/xen/xen/diff/?id=6102cace934c5ef156e7e1e21966cf3950dc40e5'>root</a>/<a href='/cgit.cgi/xen/xen/diff/xen?id=6102cace934c5ef156e7e1e21966cf3950dc40e5'>xen</a>/<a href='/cgit.cgi/xen/xen/diff/xen/xsm?id=6102cace934c5ef156e7e1e21966cf3950dc40e5'>xsm</a>/<a href='/cgit.cgi/xen/xen/diff/xen/xsm/acm?id=6102cace934c5ef156e7e1e21966cf3950dc40e5'>acm</a>/<a href='/cgit.cgi/xen/xen/diff/xen/xsm/acm/acm_xsm_hooks.c?id=6102cace934c5ef156e7e1e21966cf3950dc40e5'>acm_xsm_hooks.c</a></div><div class='content'><div class='cgit-panel'><b>diff options</b><form method='get'><input type='hidden' name='id' value='6102cace934c5ef156e7e1e21966cf3950dc40e5'/><table><tr><td colspan='2'/></tr><tr><td class='label'>context:</td><td class='ctrl'><select name='context' onchange='this.form.submit();'><option value='1'>1</option><option value='2'>2</option><option value='3' selected='selected'>3</option><option value='4'>4</option><option value='5'>5</option><option value='6'>6</option><option value='7'>7</option><option value='8'>8</option><option value='9'>9</option><option value='10'>10</option><option value='15'>15</option><option value='20'>20</option><option value='25'>25</option><option value='30'>30</option><option value='35'>35</option><option value='40'>40</option></select></td></tr><tr><td class='label'>space:</td><td class='ctrl'><select name='ignorews' onchange='this.form.submit();'><option value='0' selected='selected'>include</option><option value='1'>ignore</option></select></td></tr><tr><td class='label'>mode:</td><td class='ctrl'><select name='dt' onchange='this.form.submit();'><option value='0' selected='selected'>unified</option><option value='1'>ssdiff</option><option value='2'>stat only</option></select></td></tr><tr><td/><td class='ctrl'><noscript><input type='submit' value='reload'/></noscript></td></tr></table></form></div><div class='diffstat-header'><a href='/cgit.cgi/xen/xen/diff/?id=6102cace934c5ef156e7e1e21966cf3950dc40e5'>Diffstat</a> (limited to 'xen/xsm/acm/acm_xsm_hooks.c')</div><table summary='diffstat' class='diffstat'><tr><td class='mode'>-rw-r--r--</td><td class='del'><a href='/cgit.cgi/xen/xen/diff/xen/xsm/acm/acm_xsm_hooks.c?id=6102cace934c5ef156e7e1e21966cf3950dc40e5'>xen/xsm/acm/acm_xsm_hooks.c</a></td><td class='right'>74</td><td class='graph'><table summary='file diffstat' width='74%'><tr><td class='add' style='width: 0.0%;'/><td class='rem' style='width: 100.0%;'/><td class='none' style='width: 0.0%;'/></tr></table></td></tr>
</table><div class='diffstat-summary'>1 files changed, 0 insertions, 74 deletions</div><table summary='diff' class='diff'><tr><td><div class='head'>diff --git a/xen/xsm/acm/acm_xsm_hooks.c b/xen/xsm/acm/acm_xsm_hooks.c<br/>deleted file mode 100644<br/>index 6d3202b45f..0000000000<br/>--- a/<a href='/cgit.cgi/xen/xen/tree/xen/xsm/acm/acm_xsm_hooks.c?id=662f524483de23084ae4dde930fa7570fb15e033'>xen/xsm/acm/acm_xsm_hooks.c</a><br/>+++ /dev/null</div><div class='hunk'>@@ -1,74 +0,0 @@</div><div class='del'>-/****************************************************************</div><div class='del'>- * acm_xsm_hooks.c</div><div class='del'>- * </div><div class='del'>- * Copyright (C) 2005 IBM Corporation</div><div class='del'>- *</div><div class='del'>- * Author:</div><div class='del'>- * Reiner Sailer &lt;sailer@watson.ibm.com&gt;</div><div class='del'>- *</div><div class='del'>- * Contributors: </div><div class='del'>- * Michael LeMay, &lt;mdlemay@epoch.ncsc.mil&gt;</div><div class='del'>- * George Coker, &lt;gscoker@alpha.ncsc.mil&gt;</div><div class='del'>- *</div><div class='del'>- * sHype hooks for XSM based on the original ACM hooks.</div><div class='del'>- *</div><div class='del'>- * This program is free software; you can redistribute it and/or</div><div class='del'>- * modify it under the terms of the GNU General Public License as</div><div class='del'>- * published by the Free Software Foundation, version 2 of the</div><div class='del'>- * License.</div><div class='del'>- *</div><div class='del'>- */</div><div class='del'>-</div><div class='del'>-#include &lt;xsm/xsm.h&gt;</div><div class='del'>-#include &lt;xsm/acm/acm_hooks.h&gt;</div><div class='del'>-#include &lt;public/xsm/acm.h&gt;</div><div class='del'>-</div><div class='del'>-static int acm_grant_mapref(</div><div class='del'>-    struct domain *ld, struct domain *rd, uint32_t flags) </div><div class='del'>-{</div><div class='del'>-    domid_t id = rd-&gt;domain_id;</div><div class='del'>-</div><div class='del'>-    return acm_pre_grant_map_ref(id);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int acm_evtchn_unbound(</div><div class='del'>-    struct domain *d1, struct evtchn *chn1, domid_t id2) </div><div class='del'>-{</div><div class='del'>-    domid_t id1 = d1-&gt;domain_id;</div><div class='del'>-    </div><div class='del'>-    return acm_pre_eventchannel_unbound(id1, id2);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static int acm_evtchn_interdomain(</div><div class='del'>-    struct domain *d1, struct evtchn *chn1, </div><div class='del'>-    struct domain *d2, struct evtchn *chn2) </div><div class='del'>-{</div><div class='del'>-    domid_t id2 = d2-&gt;domain_id;</div><div class='del'>-</div><div class='del'>-    return acm_pre_eventchannel_interdomain(id2);</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-static void acm_security_domaininfo(</div><div class='del'>-    struct domain *d, struct xen_domctl_getdomaininfo *info)</div><div class='del'>-{</div><div class='del'>-    if ( d-&gt;ssid != NULL )</div><div class='del'>-        info-&gt;ssidref = ((struct acm_ssid_domain *)d-&gt;ssid)-&gt;ssidref;</div><div class='del'>-    else    </div><div class='del'>-        info-&gt;ssidref = ACM_DEFAULT_SSID;</div><div class='del'>-}</div><div class='del'>-</div><div class='del'>-extern long do_acm_op(XEN_GUEST_HANDLE(xsm_op_t) arg);</div><div class='del'>-</div><div class='del'>-struct xsm_operations acm_xsm_ops = {</div><div class='del'>-    .domain_create = acm_domain_create,</div><div class='del'>-    .free_security_domain = acm_domain_destroy,</div><div class='del'>-</div><div class='del'>-    .grant_mapref = acm_grant_mapref,</div><div class='del'>-</div><div class='del'>-    .evtchn_unbound = acm_evtchn_unbound,</div><div class='del'>-    .evtchn_interdomain = acm_evtchn_interdomain,</div><div class='del'>-</div><div class='del'>-    .security_domaininfo = acm_security_domaininfo,</div><div class='del'>-</div><div class='del'>-    .__do_xsm_op = do_acm_op,</div><div class='del'>-};</div></td></tr></table></div> <!-- class=content -->
<div class='footer'>generated by <a href='https://git.zx2c4.com/cgit/about/'>cgit v1.2.3</a> (<a href='https://git-scm.com/'>git 2.25.1</a>) at 2025-09-11 19:41:59 +0000</div>
</div> <!-- id=cgit -->
</body>
</html>
00</a>
<a id='n201' href='#n201'>201</a>
<a id='n202' href='#n202'>202</a>
<a id='n203' href='#n203'>203</a>
<a id='n204' href='#n204'>204</a>
<a id='n205' href='#n205'>205</a>
<a id='n206' href='#n206'>206</a>
<a id='n207' href='#n207'>207</a>
<a id='n208' href='#n208'>208</a>
<a id='n209' href='#n209'>209</a>
<a id='n210' href='#n210'>210</a>
<a id='n211' href='#n211'>211</a>
<a id='n212' href='#n212'>212</a>
<a id='n213' href='#n213'>213</a>
<a id='n214' href='#n214'>214</a>
<a id='n215' href='#n215'>215</a>
<a id='n216' href='#n216'>216</a>
<a id='n217' href='#n217'>217</a>
<a id='n218' href='#n218'>218</a>
<a id='n219' href='#n219'>219</a>
<a id='n220' href='#n220'>220</a>
<a id='n221' href='#n221'>221</a>
<a id='n222' href='#n222'>222</a>
<a id='n223' href='#n223'>223</a>
<a id='n224' href='#n224'>224</a>
<a id='n225' href='#n225'>225</a>
<a id='n226' href='#n226'>226</a>
<a id='n227' href='#n227'>227</a>
<a id='n228' href='#n228'>228</a>
<a id='n229' href='#n229'>229</a>
<a id='n230' href='#n230'>230</a>
<a id='n231' href='#n231'>231</a>
<a id='n232' href='#n232'>232</a>
<a id='n233' href='#n233'>233</a>
<a id='n234' href='#n234'>234</a>
<a id='n235' href='#n235'>235</a>
<a id='n236' href='#n236'>236</a>
<a id='n237' href='#n237'>237</a>
<a id='n238' href='#n238'>238</a>
<a id='n239' href='#n239'>239</a>
<a id='n240' href='#n240'>240</a>
<a id='n241' href='#n241'>241</a>
<a id='n242' href='#n242'>242</a>
<a id='n243' href='#n243'>243</a>
<a id='n244' href='#n244'>244</a>
<a id='n245' href='#n245'>245</a>
<a id='n246' href='#n246'>246</a>
<a id='n247' href='#n247'>247</a>
<a id='n248' href='#n248'>248</a>
<a id='n249' href='#n249'>249</a>
<a id='n250' href='#n250'>250</a>
<a id='n251' href='#n251'>251</a>
<a id='n252' href='#n252'>252</a>
<a id='n253' href='#n253'>253</a>
<a id='n254' href='#n254'>254</a>
<a id='n255' href='#n255'>255</a>
<a id='n256' href='#n256'>256</a>
<a id='n257' href='#n257'>257</a>
<a id='n258' href='#n258'>258</a>
<a id='n259' href='#n259'>259</a>
<a id='n260' href='#n260'>260</a>
<a id='n261' href='#n261'>261</a>
<a id='n262' href='#n262'>262</a>
<a id='n263' href='#n263'>263</a>
<a id='n264' href='#n264'>264</a>
<a id='n265' href='#n265'>265</a>
<a id='n266' href='#n266'>266</a>
<a id='n267' href='#n267'>267</a>
<a id='n268' href='#n268'>268</a>
<a id='n269' href='#n269'>269</a>
<a id='n270' href='#n270'>270</a>
<a id='n271' href='#n271'>271</a>
<a id='n272' href='#n272'>272</a>
<a id='n273' href='#n273'>273</a>
<a id='n274' href='#n274'>274</a>
<a id='n275' href='#n275'>275</a>
<a id='n276' href='#n276'>276</a>
<a id='n277' href='#n277'>277</a>
<a id='n278' href='#n278'>278</a>
<a id='n279' href='#n279'>279</a>
<a id='n280' href='#n280'>280</a>
<a id='n281' href='#n281'>281</a>
<a id='n282' href='#n282'>282</a>
<a id='n283' href='#n283'>283</a>
<a id='n284' href='#n284'>284</a>
<a id='n285' href='#n285'>285</a>
<a id='n286' href='#n286'>286</a>
<a id='n287' href='#n287'>287</a>
<a id='n288' href='#n288'>288</a>
<a id='n289' href='#n289'>289</a>
</pre></td>
<td class='lines'><pre><code><style>pre { line-height: 125%; margin: 0; }
td.linenos pre { color: #000000; background-color: #f0f0f0; padding: 0 5px 0 5px; }
span.linenos { color: #000000; background-color: #f0f0f0; padding: 0 5px 0 5px; }
td.linenos pre.special { color: #000000; background-color: #ffffc0; padding: 0 5px 0 5px; }
span.linenos.special { color: #000000; background-color: #ffffc0; padding: 0 5px 0 5px; }
.highlight .hll { background-color: #ffffcc }
.highlight { background: #ffffff; }
.highlight .c { color: #888888 } /* Comment */
.highlight .err { color: #a61717; background-color: #e3d2d2 } /* Error */
.highlight .k { color: #008800; font-weight: bold } /* Keyword */
.highlight .ch { color: #888888 } /* Comment.Hashbang */
.highlight .cm { color: #888888 } /* Comment.Multiline */
.highlight .cp { color: #cc0000; font-weight: bold } /* Comment.Preproc */
.highlight .cpf { color: #888888 } /* Comment.PreprocFile */
.highlight .c1 { color: #888888 } /* Comment.Single */
.highlight .cs { color: #cc0000; font-weight: bold; background-color: #fff0f0 } /* Comment.Special */
.highlight .gd { color: #000000; background-color: #ffdddd } /* Generic.Deleted */
.highlight .ge { font-style: italic } /* Generic.Emph */
.highlight .gr { color: #aa0000 } /* Generic.Error */
.highlight .gh { color: #333333 } /* Generic.Heading */
.highlight .gi { color: #000000; background-color: #ddffdd } /* Generic.Inserted */
.highlight .go { color: #888888 } /* Generic.Output */
.highlight .gp { color: #555555 } /* Generic.Prompt */
.highlight .gs { font-weight: bold } /* Generic.Strong */
.highlight .gu { color: #666666 } /* Generic.Subheading */
.highlight .gt { color: #aa0000 } /* Generic.Traceback */
.highlight .kc { color: #008800; font-weight: bold } /* Keyword.Constant */
.highlight .kd { color: #008800; font-weight: bold } /* Keyword.Declaration */
.highlight .kn { color: #008800; font-weight: bold } /* Keyword.Namespace */
.highlight .kp { color: #008800 } /* Keyword.Pseudo */
.highlight .kr { color: #008800; font-weight: bold } /* Keyword.Reserved */
.highlight .kt { color: #888888; font-weight: bold } /* Keyword.Type */
.highlight .m { color: #0000DD; font-weight: bold } /* Literal.Number */
.highlight .s { color: #dd2200; background-color: #fff0f0 } /* Literal.String */
.highlight .na { color: #336699 } /* Name.Attribute */
.highlight .nb { color: #003388 } /* Name.Builtin */
.highlight .nc { color: #bb0066; font-weight: bold } /* Name.Class */
.highlight .no { color: #003366; font-weight: bold } /* Name.Constant */
.highlight .nd { color: #555555 } /* Name.Decorator */
.highlight .ne { color: #bb0066; font-weight: bold } /* Name.Exception */
.highlight .nf { color: #0066bb; font-weight: bold } /* Name.Function */
.highlight .nl { color: #336699; font-style: italic } /* Name.Label */
.highlight .nn { color: #bb0066; font-weight: bold } /* Name.Namespace */
.highlight .py { color: #336699; font-weight: bold } /* Name.Property */
.highlight .nt { color: #bb0066; font-weight: bold } /* Name.Tag */
.highlight .nv { color: #336699 } /* Name.Variable */
.highlight .ow { color: #008800 } /* Operator.Word */
.highlight .w { color: #bbbbbb } /* Text.Whitespace */
.highlight .mb { color: #0000DD; font-weight: bold } /* Literal.Number.Bin */
.highlight .mf { color: #0000DD; font-weight: bold } /* Literal.Number.Float */
.highlight .mh { color: #0000DD; font-weight: bold } /* Literal.Number.Hex */
.highlight .mi { color: #0000DD; font-weight: bold } /* Literal.Number.Integer */
.highlight .mo { color: #0000DD; font-weight: bold } /* Literal.Number.Oct */
.highlight .sa { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Affix */
.highlight .sb { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Backtick */
.highlight .sc { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Char */
.highlight .dl { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Delimiter */
.highlight .sd { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Doc */
.highlight .s2 { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Double */
.highlight .se { color: #0044dd; background-color: #fff0f0 } /* Literal.String.Escape */
.highlight .sh { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Heredoc */
.highlight .si { color: #3333bb; background-color: #fff0f0 } /* Literal.String.Interpol */
.highlight .sx { color: #22bb22; background-color: #f0fff0 } /* Literal.String.Other */
.highlight .sr { color: #008800; background-color: #fff0ff } /* Literal.String.Regex */
.highlight .s1 { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Single */
.highlight .ss { color: #aa6600; background-color: #fff0f0 } /* Literal.String.Symbol */
.highlight .bp { color: #003388 } /* Name.Builtin.Pseudo */
.highlight .fm { color: #0066bb; font-weight: bold } /* Name.Function.Magic */
.highlight .vc { color: #336699 } /* Name.Variable.Class */
.highlight .vg { color: #dd7700 } /* Name.Variable.Global */
.highlight .vi { color: #3333bb } /* Name.Variable.Instance */
.highlight .vm { color: #336699 } /* Name.Variable.Magic */
.highlight .il { color: #0000DD; font-weight: bold } /* Literal.Number.Integer.Long */</style><div class="highlight"><pre><span></span><span class="k">\chapter</span><span class="nb">{</span>Evaluation of other OSS Verilog Synthesis Tools<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>chapter:sota<span class="nb">}</span>

In this appendix<span class="k">\footnote</span><span class="nb">{</span>This appendix is an updated version of an
unpublished student research paper. <span class="k">\cite</span><span class="nb">{</span>VerilogFossEval<span class="nb">}}</span>
the existing FOSS Verilog synthesis tools<span class="k">\footnote</span><span class="nb">{</span>To the
author&#39;s best knowledge, all relevant tools that existed at the time of this
writing are included. But as there is no formal channel through which such
tools are published it is hard to give any guarantees in that matter.<span class="nb">}</span> are
evaluated. Extremely limited or application specific tools (e.g.~pure Verilog
Netlist parsers) as well as Verilog simulators are not included. These existing
solutions are tested using a set of representative Verilog code snippets. It is
shown that no existing FOSS tool implements even close to a sufficient subset
of Verilog to be usable as synthesis tool for a wide range existing Verilog code.

The packages evaluated are:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Icarus Verilog <span class="k">\citeweblink</span><span class="nb">{</span>Icarus<span class="nb">}</span><span class="k">\footnote</span><span class="nb">{</span>Icarus Verilog is mainly a simulation
tool but also supported synthesis up to version 0.8. Therefore version 0.8.7 is used
for this evaluation.)<span class="nb">}</span>
<span class="k">\item</span> Verilog-to-Routing (VTR) / Odin-II <span class="k">\cite</span><span class="nb">{</span>vtr2012<span class="nb">}</span><span class="k">\cite</span><span class="nb">{</span>Odin<span class="nb">}</span><span class="k">\citeweblink</span><span class="nb">{</span>VTR<span class="nb">}</span>
<span class="k">\item</span> HDL Analyzer and Netlist Architect (HANA) <span class="k">\citeweblink</span><span class="nb">{</span>HANA<span class="nb">}</span>
<span class="k">\item</span> Verilog front-end to VIS (vl2mv) <span class="k">\cite</span><span class="nb">{</span>Cheng93vl2mv:a<span class="nb">}</span><span class="k">\citeweblink</span><span class="nb">{</span>VIS<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

In each of the following sections Verilog modules that test a certain Verilog
language feature are presented and the support for these features is tested in all
the tools mentioned above. It is evaluated whether the tools under test
successfully generate netlists for the Verilog input and whether these netlists
match the simulation behavior of the designs using testbenches.

All test cases are verified to be synthesizeable using Xilinx XST from the Xilinx
WebPACK <span class="k">\citeweblink</span><span class="nb">{</span>XilinxWebPACK<span class="nb">}</span> suite.

Trivial features such as support for simple structural Verilog are not explicitly tested.

Vl2mv and Odin-II generate output in the BLIF (Berkeley Logic Interchange
Format) and BLIF-MV (an extended version of BLIF) formats respectively.
ABC <span class="k">\citeweblink</span><span class="nb">{</span>ABC<span class="nb">}</span> is used to convert this output to Verilog for verification
using testbenches.

Icarus Verilog generates EDIF (Electronic Design Interchange Format) output
utilizing LPM (Library of Parameterized Modules) cells. The EDIF files are
converted to Verilog using edif2ngd and netgen from Xilinx WebPACK. A
hand-written implementation of the LPM cells utilized by the generated netlists
is used for verification.

Following these functional tests, a quick analysis of the extensibility of the tools
under test is provided in a separate section.

The last section of this chapter finally concludes these series of evaluations
with a summary of the results.

<span class="k">\begin</span><span class="nb">{</span>figure<span class="nb">}</span>[t!]
	<span class="k">\begin</span><span class="nb">{</span>minipage<span class="nb">}{</span>7.7cm<span class="nb">}</span>
		<span class="k">\lstinputlisting</span><span class="na">[numbers=left,frame=single,language=Verilog]</span><span class="nb">{</span>CHAPTER<span class="nb">_</span>StateOfTheArt/always01<span class="nb">_</span>pub.v<span class="nb">}</span>
	<span class="k">\end</span><span class="nb">{</span>minipage<span class="nb">}</span>
	<span class="k">\hfill</span>
	<span class="k">\begin</span><span class="nb">{</span>minipage<span class="nb">}{</span>7.7cm<span class="nb">}</span>
		<span class="k">\lstinputlisting</span><span class="na">[frame=single,language=Verilog]</span><span class="nb">{</span>CHAPTER<span class="nb">_</span>StateOfTheArt/always02<span class="nb">_</span>pub.v<span class="nb">}</span>
	<span class="k">\end</span><span class="nb">{</span>minipage<span class="nb">}</span>
	<span class="k">\caption</span><span class="nb">{</span>1st and 2nd Verilog always examples<span class="nb">}</span>
	<span class="k">\label</span><span class="nb">{</span>fig:StateOfTheArt<span class="nb">_</span>always12<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>figure<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>figure<span class="nb">}</span>[!]
	<span class="k">\lstinputlisting</span><span class="na">[numbers=left,frame=single,language=Verilog]</span><span class="nb">{</span>CHAPTER<span class="nb">_</span>StateOfTheArt/always03.v<span class="nb">}</span>
	<span class="k">\caption</span><span class="nb">{</span>3rd Verilog always example<span class="nb">}</span>
	<span class="k">\label</span><span class="nb">{</span>fig:StateOfTheArt<span class="nb">_</span>always3<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>figure<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>Always blocks and blocking vs.~nonblocking assignments<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>sec:blocking<span class="nb">_</span>nonblocking<span class="nb">}</span>

The ``always&#39;&#39;-block is one of the most fundamental non-trivial Verilog
language features.  It can be used to model a combinatorial path (with optional
registers on the outputs) in a way that mimics a regular programming language.

Within an always block, if- and case-statements can be used to model multiplexers.
Blocking assignments (<span class="s">$</span><span class="o">=</span><span class="s">$</span>) and nonblocking assignments (<span class="s">$</span><span class="nb">&lt;</span><span class="o">=</span><span class="s">$</span>) are used to populate the
leaf-nodes of these multiplexer trees. Unassigned leaf-nodes default to feedback
paths that cause the output register to hold the previous value. More advanced
synthesis tools often convert these feedback paths to register enable signals or
even generate circuits with clock gating.

Registers assigned with nonblocking assignments (<span class="s">$</span><span class="nb">&lt;</span><span class="o">=</span><span class="s">$</span>) behave differently from
variables in regular programming languages: In a simulation they are not
updated immediately after being assigned.  Instead the right-hand sides are
evaluated and the results stored in temporary memory locations. After all
pending updates have been prepared in this way they are executed, thus yielding
semi-parallel execution of all nonblocking assignments.

For synthesis this means that every occurrence of that register in an expression
addresses the output port of the corresponding register regardless of the question whether the register
has been assigned a new value in an earlier command in the same always block.
Therefore with nonblocking assignments the order of the assignments has no effect
on the resulting circuit as long as the left-hand sides of the assignments are
unique.

The three example codes in Fig.~<span class="k">\ref</span><span class="nb">{</span>fig:StateOfTheArt<span class="nb">_</span>always12<span class="nb">}</span> and
Fig.~<span class="k">\ref</span><span class="nb">{</span>fig:StateOfTheArt<span class="nb">_</span>always3<span class="nb">}</span> use all these features and can thus be used
to test the synthesis tools capabilities to synthesize always blocks correctly.

The first example is only using the most fundamental Verilog features. All
tools under test were able to successfully synthesize this design.

<span class="k">\begin</span><span class="nb">{</span>figure<span class="nb">}</span>[b!]
	<span class="k">\lstinputlisting</span><span class="na">[numbers=left,frame=single,language=Verilog]</span><span class="nb">{</span>CHAPTER<span class="nb">_</span>StateOfTheArt/arrays01.v<span class="nb">}</span>
	<span class="k">\caption</span><span class="nb">{</span>Verilog array example<span class="nb">}</span>
	<span class="k">\label</span><span class="nb">{</span>fig:StateOfTheArt<span class="nb">_</span>arrays<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>figure<span class="nb">}</span>

The 2nd example is functionally identical to the 1st one but is using an
if-statement inside the always block. Odin-II fails to synthesize it and
instead produces the following error message:

<span class="k">\begin</span><span class="nb">{</span>verbatim<span class="nb">}</span>
ERROR: (File: always02.v) (Line number: 13)
You&#39;ve defined the driver &quot;count~0&quot; twice
<span class="k">\end</span><span class="nb">{</span>verbatim<span class="nb">}</span>

Vl2mv does not produce an error message but outputs an invalid synthesis result
that is not using the reset input at all.

Icarus Verilog also doesn&#39;t produce an error message but generates an invalid output
for this 2nd example. The code generated by Icarus Verilog only implements the reset
path for the count register, effectively setting the output to constant 0.

So of all tools under test only HANA was able to create correct synthesis results
for the 2nd example.

The 3rd example is using blocking and nonblocking assignments and many if statements.
Odin also fails to synthesize this example:

<span class="k">\begin</span><span class="nb">{</span>verbatim<span class="nb">}</span>
ERROR: (File: always03.v) (Line number: 8)
ODIN doesn&#39;t handle blocking statements in Sequential blocks
<span class="k">\end</span><span class="nb">{</span>verbatim<span class="nb">}</span>

HANA, Icarus Verilog and vl2mv create invalid synthesis results for the 3rd example.

So unfortunately none of the tools under test provide a complete and correct
implementation of blocking and nonblocking assignments.

<span class="k">\section</span><span class="nb">{</span>Arrays for memory modelling<span class="nb">}</span>

Verilog arrays are part of the synthesizeable subset of Verilog and are
commonly used to model addressable memory. The Verilog code in
Fig.~<span class="k">\ref</span><span class="nb">{</span>fig:StateOfTheArt<span class="nb">_</span>arrays<span class="nb">}</span> demonstrates this by implementing a single
port memory.

For this design HANA, vl2m and ODIN-II generate error messages indicating that
arrays are not supported.

<span class="k">\begin</span><span class="nb">{</span>figure<span class="nb">}</span>[t!]
	<span class="k">\lstinputlisting</span><span class="na">[numbers=left,frame=single,language=Verilog]</span><span class="nb">{</span>CHAPTER<span class="nb">_</span>StateOfTheArt/forgen01.v<span class="nb">}</span>
	<span class="k">\caption</span><span class="nb">{</span>Verilog for loop example<span class="nb">}</span>
	<span class="k">\label</span><span class="nb">{</span>fig:StateOfTheArt<span class="nb">_</span>for<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>figure<span class="nb">}</span>

Icarus Verilog produces an invalid output that is using the address only for
reads. Instead of using the address input for writes, the generated design
simply loads the data to all memory locations whenever the write-enable input
is active, effectively turning the design into a single 4-bit D-Flip-Flop with
enable input.

As all tools under test already fail this simple test, there is nothing to gain
by continuing tests on this aspect of Verilog synthesis such as synthesis of dual port
memories, correct handling of write collisions, and so forth.

<span class="k">\begin</span><span class="nb">{</span>figure<span class="nb">}</span>[t!]
	<span class="k">\lstinputlisting</span><span class="na">[numbers=left,frame=single,language=Verilog]</span><span class="nb">{</span>CHAPTER<span class="nb">_</span>StateOfTheArt/forgen02.v<span class="nb">}</span>
	<span class="k">\caption</span><span class="nb">{</span>Verilog generate example<span class="nb">}</span>
	<span class="k">\label</span><span class="nb">{</span>fig:StateOfTheArt<span class="nb">_</span>gen<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>figure<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>For-loops and generate blocks<span class="nb">}</span>

For-loops and generate blocks are more advanced Verilog features. These features
allow the circuit designer to add program code to her design that is evaluated
during synthesis to generate (parts of) the circuits description; something that
could only be done using a code generator otherwise.

For-loops are only allowed in synthesizeable Verilog if they can be completely
unrolled. Then they can be a powerful tool to generate array logic or static
lookup tables. The code in Fig.~<span class="k">\ref</span><span class="nb">{</span>fig:StateOfTheArt<span class="nb">_</span>for<span class="nb">}</span> generates a circuit that
tests a 5 bit value for being a prime number using a static lookup table.

Generate blocks can be used to model array logic in complex parametric designs. The
code in Fig.~<span class="k">\ref</span><span class="nb">{</span>fig:StateOfTheArt<span class="nb">_</span>gen<span class="nb">}</span> implements a ripple-carry adder with
parametric width from simple assign-statements and logic operations using a Verilog
generate block.

All tools under test failed to synthesize both test cases. HANA creates invalid
output in both cases. Icarus Verilog creates invalid output for the first
test and fails with an error for the second case. The other two tools fail with
error messages for both tests.

<span class="k">\section</span><span class="nb">{</span>Extensibility<span class="nb">}</span>

This section briefly discusses the extensibility of the tools under test and
their internal data- and control-flow.  As all tools under test already failed
to synthesize simple Verilog always-blocks correctly, not much resources have
been spent on evaluating the extensibility of these tools and therefore only a
very brief discussion of the topic is provided here.

HANA synthesizes for a built-in library of standard cells using two passes over
an AST representation of the Verilog input. This approach executes fast but
limits the extensibility as everything happens in only two comparable complex
AST walks and there is no universal intermediate representation that is flexible
enough to be used in arbitrary optimizations.

Odin-II and vl2m are both front ends to existing synthesis flows. As such they
only try to quickly convert the Verilog input into the internal representation
of their respective flows (BLIF). So extensibility is less of an issue here as
potential extensions would likely be implemented in other components of the
flow.

Icarus Verilog is clearly designed to be a simulation tool rather than a
synthesis tool. The synthesis part of Icarus Verilog is an ad-hoc add-on to
Icarus Verilog that aims at converting an internal representation that is meant
for generation of a virtual machine based simulation code to netlists.

<span class="k">\section</span><span class="nb">{</span>Summary and Outlook<span class="nb">}</span>

Table~<span class="k">\ref</span><span class="nb">{</span>tab:StateOfTheArt<span class="nb">_</span>sum<span class="nb">}</span> summarizes the tests performed. Clearly none
of the tools under test make a serious attempt at providing a feature-complete
implementation of Verilog. It can be argued that Odin-II performed best in the
test as it never generated incorrect code but instead produced error messages
indicating that unsupported Verilog features where used in the Verilog input.

In conclusion, to the best knowledge of the author, there is no FOSS Verilog
synthesis tool other than Yosys that is anywhere near feature completeness and
therefore there is no other candidate for a generic Verilog front end and/or
synthesis framework to be used as a basis for custom synthesis tools.

Yosys could also replace vl2m and/or Odin-II in their respective flows or
function as a pre-compiler that can translate full-featured Verilog code to the
simple subset of Verilog that is understood by vl2m and Odin-II.

Yosys is designed for extensibility. It can be used as-is to synthesize Verilog
code to netlists, but its main purpose is to be used as basis for custom tools.
Yosys is structured in a language dependent Verilog front end and language
independent synthesis code (which is in itself structured in independent
passes). This architecture will simplify implementing additional HDL front
ends and/or additional synthesis passes.

Chapter~<span class="k">\ref</span><span class="nb">{</span>chapter:eval<span class="nb">}</span> contains a more detailed evaluation of Yosys using real-world
designs that are far out of reach for any of the other tools discussed in this appendix.

<span class="k">\vskip</span>2cm
<span class="k">\begin</span><span class="nb">{</span>table<span class="nb">}</span>[h]
	<span class="c">%             yosys       hana        vis         icarus      odin</span>
	<span class="c">% always01    ok          ok          ok          ok          ok</span>
	<span class="c">% always02    ok          ok          failed      failed      error</span>
	<span class="c">% always03    ok          failed      failed      missing     error</span>
	<span class="c">% arrays01    ok          error       error       failed      error</span>
	<span class="c">% forgen01    ok          failed      error       failed      error</span>
	<span class="c">% forgen02    ok          failed      error       error       error</span>
	<span class="k">\def\ok</span><span class="nb">{</span><span class="k">\ding</span><span class="nb">{</span>52<span class="nb">}}</span>
	<span class="k">\def\error</span><span class="nb">{</span><span class="k">\ding</span><span class="nb">{</span>56<span class="nb">}}</span>
	<span class="k">\def\failed</span><span class="nb">{</span><span class="s">$</span><span class="nv">\skull</span><span class="s">$</span><span class="nb">}</span>
	<span class="k">\def\missing</span><span class="nb">{</span><span class="s">$</span><span class="nv">\skull</span><span class="s">$</span><span class="nb">}</span>
	<span class="k">\rowcolors</span><span class="nb">{</span>2<span class="nb">}{</span>gray!25<span class="nb">}{</span>white<span class="nb">}</span>
	<span class="k">\centerline</span><span class="nb">{</span>
		<span class="k">\begin</span><span class="nb">{</span>tabular<span class="nb">}{</span>|l|cccc|c|<span class="nb">}</span>
		<span class="k">\hline</span>
		<span class="nb">&amp;</span> <span class="k">\bf</span> HANA <span class="nb">&amp;</span> <span class="k">\bf</span> VIS / vl2m <span class="nb">&amp;</span> <span class="k">\bf</span> Icarus Verilog <span class="nb">&amp;</span> <span class="k">\bf</span> Odin-II <span class="nb">&amp;</span> <span class="k">\bf</span> Yosys <span class="k">\\</span>
		<span class="k">\hline</span>
		<span class="k">\tt</span> always01 <span class="nb">&amp;</span>  <span class="k">\ok</span>       <span class="nb">&amp;</span>  <span class="k">\ok</span>       <span class="nb">&amp;</span>  <span class="k">\ok</span>       <span class="nb">&amp;</span>  <span class="k">\ok</span>     <span class="nb">&amp;</span> <span class="k">\ok</span> <span class="k">\\</span>
		<span class="k">\tt</span> always02 <span class="nb">&amp;</span>  <span class="k">\ok</span>       <span class="nb">&amp;</span>  <span class="k">\failed</span>   <span class="nb">&amp;</span>  <span class="k">\failed</span>   <span class="nb">&amp;</span>  <span class="k">\error</span>  <span class="nb">&amp;</span> <span class="k">\ok</span> <span class="k">\\</span>
		<span class="k">\tt</span> always03 <span class="nb">&amp;</span>  <span class="k">\failed</span>   <span class="nb">&amp;</span>  <span class="k">\failed</span>   <span class="nb">&amp;</span>  <span class="k">\missing</span>  <span class="nb">&amp;</span>  <span class="k">\error</span>  <span class="nb">&amp;</span> <span class="k">\ok</span> <span class="k">\\</span>
		<span class="k">\tt</span> arrays01 <span class="nb">&amp;</span>  <span class="k">\error</span>    <span class="nb">&amp;</span>  <span class="k">\error</span>    <span class="nb">&amp;</span>  <span class="k">\failed</span>   <span class="nb">&amp;</span>  <span class="k">\error</span>  <span class="nb">&amp;</span> <span class="k">\ok</span> <span class="k">\\</span>
		<span class="k">\tt</span> forgen01 <span class="nb">&amp;</span>  <span class="k">\failed</span>   <span class="nb">&amp;</span>  <span class="k">\error</span>    <span class="nb">&amp;</span>  <span class="k">\failed</span>   <span class="nb">&amp;</span>  <span class="k">\error</span>  <span class="nb">&amp;</span> <span class="k">\ok</span> <span class="k">\\</span>
		<span class="k">\tt</span> forgen02 <span class="nb">&amp;</span>  <span class="k">\failed</span>   <span class="nb">&amp;</span>  <span class="k">\error</span>    <span class="nb">&amp;</span>  <span class="k">\error</span>    <span class="nb">&amp;</span>  <span class="k">\error</span>  <span class="nb">&amp;</span> <span class="k">\ok</span> <span class="k">\\</span>
		<span class="k">\hline</span>
		<span class="k">\end</span><span class="nb">{</span>tabular<span class="nb">}</span>
	<span class="nb">}</span>
	<span class="k">\centerline</span><span class="nb">{</span>
		<span class="k">\ding</span><span class="nb">{</span>52<span class="nb">}</span> <span class="k">\dots</span> passed <span class="k">\hskip</span>2em
		<span class="k">\ding</span><span class="nb">{</span>56<span class="nb">}</span> <span class="k">\dots</span> produced error <span class="k">\hskip</span>2em
		<span class="s">$</span><span class="nv">\skull</span><span class="s">$</span> <span class="k">\dots</span> incorrect output
	<span class="nb">}</span>
	<span class="k">\caption</span><span class="nb">{</span>Summary of all test results<span class="nb">}</span>
	<span class="k">\label</span><span class="nb">{</span>tab:StateOfTheArt<span class="nb">_</span>sum<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>table<span class="nb">}</span>
</pre></div>
</code></pre></td></tr></table>
</div> <!-- class=content -->
<div class='footer'>generated by <a href='https://git.zx2c4.com/cgit/about/'>cgit v1.2.3</a> (<a href='https://git-scm.com/'>git 2.25.1</a>) at 2025-09-11 19:41:59 +0000</div>
</div> <!-- id=cgit -->
</body>
</html>
