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<div class='path'>path: <a href='/cgit.cgi/avr/qmk/lufa/commit/'>root</a>/<a href='/cgit.cgi/avr/qmk/lufa/commit/Bootloaders'>Bootloaders</a>/<a href='/cgit.cgi/avr/qmk/lufa/commit/Bootloaders/MassStorage'>MassStorage</a></div><div class='content'><div class='cgit-panel'><b>diff options</b><form method='get'><table><tr><td colspan='2'/></tr><tr><td class='label'>context:</td><td class='ctrl'><select name='context' onchange='this.form.submit();'><option value='1'>1</option><option value='2'>2</option><option value='3' selected='selected'>3</option><option value='4'>4</option><option value='5'>5</option><option value='6'>6</option><option value='7'>7</option><option value='8'>8</option><option value='9'>9</option><option value='10'>10</option><option value='15'>15</option><option value='20'>20</option><option value='25'>25</option><option value='30'>30</option><option value='35'>35</option><option value='40'>40</option></select></td></tr><tr><td class='label'>space:</td><td class='ctrl'><select name='ignorews' onchange='this.form.submit();'><option value='0' selected='selected'>include</option><option value='1'>ignore</option></select></td></tr><tr><td class='label'>mode:</td><td class='ctrl'><select name='dt' onchange='this.form.submit();'><option value='0' selected='selected'>unified</option><option value='1'>ssdiff</option><option value='2'>stat only</option></select></td></tr><tr><td/><td class='ctrl'><noscript><input type='submit' value='reload'/></noscript></td></tr></table></form></div><table summary='commit info' class='commit-info'>
<tr><th>author</th><td>fauxpark &lt;fauxpark@gmail.com&gt;</td><td class='right'>2019-11-06 20:04:21 +1100</td></tr>
<tr><th>committer</th><td>Drashna Jaelre &lt;drashna@live.com&gt;</td><td class='right'>2019-12-19 13:09:43 -0800</td></tr>
<tr><th>commit</th><td colspan='2' class='sha1'><a href='/cgit.cgi/avr/qmk/lufa/commit/Bootloaders/MassStorage?id=07bea4f0c7a2770a6e4f23779893524d3452881b'>07bea4f0c7a2770a6e4f23779893524d3452881b</a> (<a href='/cgit.cgi/avr/qmk/lufa/patch/Bootloaders/MassStorage?id=07bea4f0c7a2770a6e4f23779893524d3452881b'>patch</a>)</td></tr>
<tr><th>tree</th><td colspan='2' class='sha1'><a href='/cgit.cgi/avr/qmk/lufa/tree/'>7e1c3370d00e12f2b0c50090d13819e3cc602e11</a> /<a href='/cgit.cgi/avr/qmk/lufa/tree/Bootloaders/MassStorage'>Bootloaders/MassStorage</a></td></tr>
<tr><th>parent</th><td colspan='2' class='sha1'><a href='/cgit.cgi/avr/qmk/lufa/commit/Bootloaders/MassStorage?id=4f66a7a3258bae4d2a859529a719bb5142506346'>4f66a7a3258bae4d2a859529a719bb5142506346</a> (<a href='/cgit.cgi/avr/qmk/lufa/diff/Bootloaders/MassStorage?id2=4f66a7a3258bae4d2a859529a719bb5142506346'>diff</a>)</td></tr><tr><th>download</th><td colspan='2' class='sha1'><a href='/cgit.cgi/avr/qmk/lufa/snapshot/lufa-master.tar.gz'>lufa-master.tar.gz</a><br/><a href='/cgit.cgi/avr/qmk/lufa/snapshot/lufa-master.tar.bz2'>lufa-master.tar.bz2</a><br/><a href='/cgit.cgi/avr/qmk/lufa/snapshot/lufa-master.zip'>lufa-master.zip</a><br/></td></tr></table>
<div class='commit-subject'>Set magic ReleaseNumber for QMK-DFU<span class='decoration'><a class='deco' href='/cgit.cgi/avr/qmk/lufa/commit/Bootloaders/MassStorage?id=07bea4f0c7a2770a6e4f23779893524d3452881b'>HEAD</a><a class='branch-deco' href='/cgit.cgi/avr/qmk/lufa/log/Bootloaders/MassStorage'>master</a></span></div><div class='commit-msg'></div><div class='diffstat-header'><a href='/cgit.cgi/avr/qmk/lufa/diff/'>Diffstat</a> (limited to 'Bootloaders/MassStorage')</div><table summary='diffstat' class='diffstat'></table><div class='diffstat-summary'>0 files changed, 0 insertions, 0 deletions</div><table summary='diff' class='diff'><tr><td></td></tr></table></div> <!-- class=content -->
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</pre></td>
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.highlight .il { color: #0000DD; font-weight: bold } /* Literal.Number.Integer.Long */</style><div class="highlight"><pre><span></span><span class="k">\chapter</span><span class="nb">{</span>Evaluation, Conclusion, Future Work<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>chapter:eval<span class="nb">}</span>

The Yosys source tree contains over 200 test cases<span class="k">\footnote</span><span class="nb">{</span>Most of this test
cases are copied from HANA <span class="k">\citeweblink</span><span class="nb">{</span>HANA<span class="nb">}</span> or the ASIC-WORLD website
<span class="k">\citeweblink</span><span class="nb">{</span>ASIC-WORLD<span class="nb">}</span>.<span class="nb">}</span> which are used in the <span class="nb">{</span><span class="k">\tt</span> make test<span class="nb">}</span> make-target.
Besides these there is an external Yosys benchmark and test case package that
contains a few larger designs <span class="k">\citeweblink</span><span class="nb">{</span>YosysTestsGit<span class="nb">}</span>. This package
contains the designs listed in Tab.~<span class="k">\ref</span><span class="nb">{</span>tab:yosys-test-designs<span class="nb">}</span>.

<span class="k">\begin</span><span class="nb">{</span>table<span class="nb">}</span>
	<span class="k">\hfil</span>
	<span class="k">\begin</span><span class="nb">{</span>tabular<span class="nb">}{</span>lrrp<span class="nb">{</span>8.5cm<span class="nb">}}</span>
		Test-Design <span class="nb">&amp;</span> Source <span class="nb">&amp;</span> Gates<span class="k">\footnotemark</span> <span class="nb">&amp;</span> Description / Comments <span class="k">\\</span>
		<span class="k">\hline</span>
		<span class="nb">{</span><span class="k">\tt</span> aes<span class="k">\_</span>core<span class="nb">}</span>   <span class="nb">&amp;</span>  IWLS2005 <span class="nb">&amp;</span> <span class="s">$</span><span class="nb"> </span><span class="m">41</span><span class="nb">{,}</span><span class="m">837</span><span class="nb"> </span><span class="s">$</span> <span class="nb">&amp;</span> <span class="k">\footnotesize</span> AES Cipher written by Rudolf Usselmann <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> i2c<span class="nb">}</span>         <span class="nb">&amp;</span>  IWLS2005 <span class="nb">&amp;</span> <span class="s">$</span><span class="nb">  </span><span class="m">1</span><span class="nb">{,}</span><span class="m">072</span><span class="nb"> </span><span class="s">$</span> <span class="nb">&amp;</span> <span class="k">\footnotesize</span> WISHBONE compliant I2C Master by Richard Herveille <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> openmsp430<span class="nb">}</span>  <span class="nb">&amp;</span> OpenCores <span class="nb">&amp;</span> <span class="s">$</span><span class="nb">  </span><span class="m">7</span><span class="nb">{,}</span><span class="m">173</span><span class="nb"> </span><span class="s">$</span> <span class="nb">&amp;</span> <span class="k">\footnotesize</span> MSP430 compatible CPU by Olivier Girard <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> or1200<span class="nb">}</span>      <span class="nb">&amp;</span> OpenCores <span class="nb">&amp;</span> <span class="s">$</span><span class="nb"> </span><span class="m">42</span><span class="nb">{,}</span><span class="m">675</span><span class="nb"> </span><span class="s">$</span> <span class="nb">&amp;</span> <span class="k">\footnotesize</span> The OpenRISC 1200 CPU by Damjan Lampret <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> sasc<span class="nb">}</span>        <span class="nb">&amp;</span>  IWLS2005 <span class="nb">&amp;</span> <span class="s">$</span><span class="nb">      </span><span class="m">456</span><span class="nb"> </span><span class="s">$</span> <span class="nb">&amp;</span> <span class="k">\footnotesize</span> Simple Async. Serial Comm. Device by Rudolf Usselmann <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> simple<span class="k">\_</span>spi<span class="nb">}</span> <span class="nb">&amp;</span>  IWLS2005 <span class="nb">&amp;</span> <span class="s">$</span><span class="nb">      </span><span class="m">690</span><span class="nb"> </span><span class="s">$</span> <span class="nb">&amp;</span> <span class="k">\footnotesize</span> MC68HC11E based SPI interface by Richard Herveille <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> spi<span class="nb">}</span>         <span class="nb">&amp;</span>  IWLS2005 <span class="nb">&amp;</span> <span class="s">$</span><span class="nb">  </span><span class="m">2</span><span class="nb">{,}</span><span class="m">478</span><span class="nb"> </span><span class="s">$</span> <span class="nb">&amp;</span> <span class="k">\footnotesize</span> SPI IP core by Simon Srot <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> ss<span class="k">\_</span>pcm<span class="nb">}</span>     <span class="nb">&amp;</span>  IWLS2005 <span class="nb">&amp;</span> <span class="s">$</span><span class="nb">      </span><span class="m">279</span><span class="nb"> </span><span class="s">$</span> <span class="nb">&amp;</span> <span class="k">\footnotesize</span> PCM IO Slave by Rudolf Usselmann <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> systemcaes<span class="nb">}</span>  <span class="nb">&amp;</span>  IWLS2005 <span class="nb">&amp;</span> <span class="s">$</span><span class="nb">  </span><span class="m">6</span><span class="nb">{,}</span><span class="m">893</span><span class="nb"> </span><span class="s">$</span> <span class="nb">&amp;</span> <span class="k">\footnotesize</span> AES core (using SystemC to Verilog) by Javier Castillo <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> usb<span class="k">\_</span>phy<span class="nb">}</span>    <span class="nb">&amp;</span>  IWLS2005 <span class="nb">&amp;</span> <span class="s">$</span><span class="nb">      </span><span class="m">515</span><span class="nb"> </span><span class="s">$</span> <span class="nb">&amp;</span> <span class="k">\footnotesize</span> USB 1.1 PHY by Rudolf Usselmann <span class="k">\\</span>
	<span class="k">\end</span><span class="nb">{</span>tabular<span class="nb">}</span>
	<span class="k">\caption</span><span class="nb">{</span>Tests included in the yosys-tests package.<span class="nb">}</span>
	<span class="k">\label</span><span class="nb">{</span>tab:yosys-test-designs<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>table<span class="nb">}</span>

<span class="k">\footnotetext</span><span class="nb">{</span>
Number of gates determined using the Yosys synthesis script ``<span class="nb">{</span><span class="k">\tt</span> hierarchy -top <span class="k">\$</span>top; proc; opt; memory; opt; techmap; opt; abc; opt; flatten <span class="k">\$</span>top; hierarchy -top <span class="k">\$</span>top; abc; opt; select -count */c:*<span class="nb">}</span>&#39;&#39;.
<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>Correctness of Synthesis Results<span class="nb">}</span>

The following measures were taken to increase the confidence in the correctness of the Yosys synthesis results:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Yosys comes with a large selection<span class="k">\footnote</span><span class="nb">{</span>At the time of this writing
269 test cases.<span class="nb">}</span> of small test cases that are evaluated when the command <span class="nb">{</span><span class="k">\tt</span>
make test<span class="nb">}</span> is executed. During development of Yosys it was shown that this
collection of test cases is sufficient to catch most bugs. The following more
sophisticated test procedures only caught a few additional bugs. Whenever this
happened, an appropriate test case was added to the collection of small test
cases for <span class="nb">{</span><span class="k">\tt</span> make test<span class="nb">}</span> to ensure better testability of the feature in
question in the future.

<span class="k">\item</span> The designs listed in Tab.~<span class="k">\ref</span><span class="nb">{</span>tab:yosys-test-designs<span class="nb">}</span> where validated
using the formal verification tool Synopsys Formality<span class="k">\citeweblink</span><span class="nb">{</span>Formality<span class="nb">}</span>.
The Yosys synthesis scripts used to synthesize the individual designs for this
test are slightly different per design in order to broaden the coverage of
Yosys features. The large majority of all errors encountered using these tests
are false-negatives, mostly related to FSM encoding or signal naming in large
array logic (such as in memory blocks). Therefore the <span class="nb">{</span><span class="k">\tt</span> fsm<span class="k">\_</span>recode<span class="nb">}</span> pass
was extended so it can be used to generate TCL commands for Synopsys Formality
that describe the relationship between old and new state encodings. Also the
method used to generate signal and cell names in the Verilog backend was
slightly modified in order to improve the automatic matching of net names in
Synopsys Formality. With these changes in place all designs in Tab.~<span class="k">\ref</span><span class="nb">{</span>tab:yosys-test-designs<span class="nb">}</span>
validate successfully using Formality.

<span class="k">\item</span> VlogHammer <span class="k">\citeweblink</span><span class="nb">{</span>VlogHammer<span class="nb">}</span> is a set of scripts that
auto-generate a large collection of test cases<span class="k">\footnote</span><span class="nb">{</span>At the time of this
writing over 6600 test cases.<span class="nb">}</span> and synthesize them using Yosys and the
following freely available proprietary synthesis tools.
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Xilinx Vivado WebPack (2013.2) <span class="k">\citeweblink</span><span class="nb">{</span>XilinxWebPACK<span class="nb">}</span>
<span class="k">\item</span> Xilinx ISE (XST) WebPack (14.5) <span class="k">\citeweblink</span><span class="nb">{</span>XilinxWebPACK<span class="nb">}</span>
<span class="k">\item</span> Altera Quartus II Web Edition (13.0) <span class="k">\citeweblink</span><span class="nb">{</span>QuartusWeb<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>
The built-in SAT solver of Yosys is used to formally
verify the Yosys RTL- and Gate-Level netlists against the netlists generated by
this other tools.<span class="k">\footnote</span><span class="nb">{</span>A SAT solver is a program that can solve the boolean
satisfiability problem. The built-in SAT solver in Yosys can be used for formal
equivalence checking, amongst other things. See Sec.~<span class="k">\ref</span><span class="nb">{</span>cmd:sat<span class="nb">}</span> for details.<span class="nb">}</span>
When differences are found, the input pattern that result in
different outputs are used for simulating the original Verilog code as well as
the synthesis results using the following Verilog simulators.
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Xilinx ISIM (from Xilinx ISE 14.5 <span class="k">\citeweblink</span><span class="nb">{</span>XilinxWebPACK<span class="nb">}</span>)
<span class="k">\item</span> Modelsim 10.1d (from Quartus II 13.0 <span class="k">\citeweblink</span><span class="nb">{</span>QuartusWeb<span class="nb">}</span>)
<span class="k">\item</span> Icarus Verilog (no specific version)
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>
The set of tests performed by VlogHammer systematically verify the correct
behaviour of
<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Yosys Verilog Frontend and RTL generation
<span class="k">\item</span> Yosys Gate-Level Technology Mapping
<span class="k">\item</span> Yosys SAT Models for RTL- and Gate-Level cells
<span class="k">\item</span> Yosys Constant Evaluator Models for RTL- and Gate-Level cells
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>
against the reference provided by the other tools. A few bugs related to sign
extensions and bit-width extensions where found (and have been fixed meanwhile)
using this approach. This test also revealed a small number of bugs in the
other tools (i.e.~Vivado, XST, Quartus, ISIM and Icarus Verilog; no bugs where
found in Modelsim using vlogHammer so far).
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

Although complex software can never be expected to be fully bug-free
<span class="k">\cite</span><span class="nb">{</span>MURPHY<span class="nb">}</span>, it has been shown that Yosys is mature and feature-complete
enough to handle most real-world cases correctly.

<span class="k">\section</span><span class="nb">{</span>Quality of synthesis results<span class="nb">}</span>

In this section an attempt to evaluate the quality of Yosys synthesis results is made. To this end the
synthesis results of a commercial FPGA synthesis tool when presented with the original HDL code vs.~when
presented with the Yosys synthesis result are compared.

The OpenMSP430 and the OpenRISC 1200 test cases were synthesized using the following Yosys synthesis script:

<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single,mathescape]
hierarchy -check
proc; opt; fsm; opt; memory; opt
techmap; opt; abc; opt
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

The original RTL and the Yosys output where both passed to the Xilinx XST 14.5
FPGA synthesis tool. The following setting where used for XST:

<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single,mathescape]
-p artix7
-use<span class="nb">_</span>dsp48 NO
-iobuf NO
-ram<span class="nb">_</span>extract NO
-rom<span class="nb">_</span>extract NO
-fsm<span class="nb">_</span>extract YES
-fsm<span class="nb">_</span>encoding Auto
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>

The results of this comparison is summarized in Tab.~<span class="k">\ref</span><span class="nb">{</span>tab:synth-test<span class="nb">}</span>. The
used FPGA resources (registers and LUTs) and performance (maximum frequency as
reported by XST) are given per module (indentation indicates module hierarchy,
the numbers are including all contained modules).

For most modules the results are very similar between XST and Yosys. XST is
used in both cases for the final mapping of logic to LUTs. So this comparison
only compares the high-level synthesis functions (such as FSM extraction and
encoding) of Yosys and XST.

<span class="k">\begin</span><span class="nb">{</span>table<span class="nb">}</span>
	<span class="k">\def\nomhz</span><span class="nb">{</span>--- <span class="k">\phantom</span><span class="nb">{</span>MHz<span class="nb">}}</span>
	<span class="k">\def\P</span>#1 <span class="nb">{</span>(#1<span class="k">\hbox</span> to 0px<span class="nb">{</span>)<span class="k">\hss</span><span class="nb">}}</span>
	<span class="k">\hfil</span>
	<span class="k">\begin</span><span class="nb">{</span>tabular<span class="nb">}{</span>l|rrr|rrr<span class="nb">}</span>
		<span class="nb">&amp;</span> <span class="k">\multicolumn</span><span class="nb">{</span>3<span class="nb">}{</span>c|<span class="nb">}{</span>Without Yosys<span class="nb">}</span> <span class="nb">&amp;</span> <span class="k">\multicolumn</span><span class="nb">{</span>3<span class="nb">}{</span>c<span class="nb">}{</span>With Yosys<span class="nb">}</span> <span class="k">\\</span>
		Module <span class="nb">&amp;</span> Regs <span class="nb">&amp;</span> LUTs <span class="nb">&amp;</span> Max. Freq. <span class="nb">&amp;</span> Regs <span class="nb">&amp;</span> LUTs <span class="nb">&amp;</span> Max. Freq. <span class="k">\\</span>
		<span class="k">\hline</span>
		<span class="nb">{</span><span class="k">\tt</span> openMSP430<span class="nb">}</span>                                    <span class="nb">&amp;</span>    689 <span class="nb">&amp;</span>   2210 <span class="nb">&amp;</span>   71 MHz <span class="nb">&amp;</span>    719 <span class="nb">&amp;</span>   2779 <span class="nb">&amp;</span>   53 MHz <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em omsp<span class="k">\_</span>clock<span class="k">\_</span>module<span class="nb">}</span>                 <span class="nb">&amp;</span>     21 <span class="nb">&amp;</span>     30 <span class="nb">&amp;</span>  645 MHz <span class="nb">&amp;</span>     21 <span class="nb">&amp;</span>     30 <span class="nb">&amp;</span>  644 MHz <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em <span class="k">\hskip</span>1em omsp<span class="k">\_</span>sync<span class="k">\_</span>cell<span class="nb">}</span>          <span class="nb">&amp;</span>      2 <span class="nb">&amp;</span>    --- <span class="nb">&amp;</span> 1542 MHz <span class="nb">&amp;</span>      2 <span class="nb">&amp;</span>    --- <span class="nb">&amp;</span> 1542 MHz <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em <span class="k">\hskip</span>1em omsp<span class="k">\_</span>sync<span class="k">\_</span>reset<span class="nb">}</span>         <span class="nb">&amp;</span>      2 <span class="nb">&amp;</span>    --- <span class="nb">&amp;</span> 1542 MHz <span class="nb">&amp;</span>      2 <span class="nb">&amp;</span>    --- <span class="nb">&amp;</span> 1542 MHz <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em omsp<span class="k">\_</span>dbg<span class="nb">}</span>                           <span class="nb">&amp;</span>    143 <span class="nb">&amp;</span>    344 <span class="nb">&amp;</span>  292 MHz <span class="nb">&amp;</span>    149 <span class="nb">&amp;</span>    430 <span class="nb">&amp;</span>  353 MHz <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em <span class="k">\hskip</span>1em omsp<span class="k">\_</span>dbg<span class="k">\_</span>uart<span class="nb">}</span>           <span class="nb">&amp;</span>     76 <span class="nb">&amp;</span>    135 <span class="nb">&amp;</span>  377 MHz <span class="nb">&amp;</span>     79 <span class="nb">&amp;</span>    139 <span class="nb">&amp;</span>  389 MHz <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em omsp<span class="k">\_</span>execution<span class="k">\_</span>unit<span class="nb">}</span>               <span class="nb">&amp;</span>    266 <span class="nb">&amp;</span>    911 <span class="nb">&amp;</span>   80 MHz <span class="nb">&amp;</span>    266 <span class="nb">&amp;</span>   1034 <span class="nb">&amp;</span>  137 MHz <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em <span class="k">\hskip</span>1em omsp<span class="k">\_</span>alu<span class="nb">}</span>                 <span class="nb">&amp;</span>    --- <span class="nb">&amp;</span>    202 <span class="nb">&amp;</span>   <span class="k">\nomhz</span> <span class="nb">&amp;</span>    --- <span class="nb">&amp;</span>    263 <span class="nb">&amp;</span>   <span class="k">\nomhz</span> <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em <span class="k">\hskip</span>1em omsp<span class="k">\_</span>register<span class="k">\_</span>file<span class="nb">}</span>      <span class="nb">&amp;</span>    231 <span class="nb">&amp;</span>    478 <span class="nb">&amp;</span>  285 MHz <span class="nb">&amp;</span>    231 <span class="nb">&amp;</span>    506 <span class="nb">&amp;</span>  293 MHz <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em omsp<span class="k">\_</span>frontend<span class="nb">}</span>                      <span class="nb">&amp;</span>    115 <span class="nb">&amp;</span>    340 <span class="nb">&amp;</span>  178 MHz <span class="nb">&amp;</span>    118 <span class="nb">&amp;</span>    527 <span class="nb">&amp;</span>  206 MHz <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em omsp<span class="k">\_</span>mem<span class="k">\_</span>backbone<span class="nb">}</span>                 <span class="nb">&amp;</span>     38 <span class="nb">&amp;</span>    141 <span class="nb">&amp;</span> 1087 MHz <span class="nb">&amp;</span>     38 <span class="nb">&amp;</span>    144 <span class="nb">&amp;</span> 1087 MHz <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em omsp<span class="k">\_</span>multiplier<span class="nb">}</span>                    <span class="nb">&amp;</span>     73 <span class="nb">&amp;</span>    397 <span class="nb">&amp;</span>  129 MHz <span class="nb">&amp;</span>    102 <span class="nb">&amp;</span>   1053 <span class="nb">&amp;</span>   55 MHz <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em omsp<span class="k">\_</span>sfr<span class="nb">}</span>                           <span class="nb">&amp;</span>      6 <span class="nb">&amp;</span>     18 <span class="nb">&amp;</span> 1023 MHz <span class="nb">&amp;</span>      6 <span class="nb">&amp;</span>     20 <span class="nb">&amp;</span> 1023 MHz <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em omsp<span class="k">\_</span>watchdog<span class="nb">}</span>                      <span class="nb">&amp;</span>     24 <span class="nb">&amp;</span>     53 <span class="nb">&amp;</span>  362 MHz <span class="nb">&amp;</span>     24 <span class="nb">&amp;</span>     70 <span class="nb">&amp;</span>  360 MHz <span class="k">\\</span>
		<span class="k">\hline</span>
		<span class="nb">{</span><span class="k">\tt</span> or1200<span class="k">\_</span>top<span class="nb">}</span>                                   <span class="nb">&amp;</span>   7148 <span class="nb">&amp;</span>   9969 <span class="nb">&amp;</span>  135 MHz <span class="nb">&amp;</span>   7173 <span class="nb">&amp;</span>  10238 <span class="nb">&amp;</span>  108 MHz <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em or1200<span class="k">\_</span>alu<span class="nb">}</span>                         <span class="nb">&amp;</span>    --- <span class="nb">&amp;</span>    681 <span class="nb">&amp;</span>   <span class="k">\nomhz</span> <span class="nb">&amp;</span>    --- <span class="nb">&amp;</span>    641 <span class="nb">&amp;</span>   <span class="k">\nomhz</span> <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em or1200<span class="k">\_</span>cfgr<span class="nb">}</span>                        <span class="nb">&amp;</span>    --- <span class="nb">&amp;</span>     11 <span class="nb">&amp;</span>   <span class="k">\nomhz</span> <span class="nb">&amp;</span>    --- <span class="nb">&amp;</span>     11 <span class="nb">&amp;</span>   <span class="k">\nomhz</span> <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em or1200<span class="k">\_</span>ctrl<span class="nb">}</span>                        <span class="nb">&amp;</span>    175 <span class="nb">&amp;</span>    186 <span class="nb">&amp;</span>  464 MHz <span class="nb">&amp;</span>    174 <span class="nb">&amp;</span>    279 <span class="nb">&amp;</span>  377 MHz <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em or1200<span class="k">\_</span>except<span class="nb">}</span>                      <span class="nb">&amp;</span>    241 <span class="nb">&amp;</span>    451 <span class="nb">&amp;</span>  313 MHz <span class="nb">&amp;</span>    241 <span class="nb">&amp;</span>    353 <span class="nb">&amp;</span>  301 MHz <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em or1200<span class="k">\_</span>freeze<span class="nb">}</span>                      <span class="nb">&amp;</span>      6 <span class="nb">&amp;</span>     18 <span class="nb">&amp;</span>  507 MHz <span class="nb">&amp;</span>      6 <span class="nb">&amp;</span>     16 <span class="nb">&amp;</span>  515 MHz <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em or1200<span class="k">\_</span>if<span class="nb">}</span>                          <span class="nb">&amp;</span>     68 <span class="nb">&amp;</span>    143 <span class="nb">&amp;</span>  806 MHz <span class="nb">&amp;</span>     68 <span class="nb">&amp;</span>    139 <span class="nb">&amp;</span>  790 MHz <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em or1200<span class="k">\_</span>lsu<span class="nb">}</span>                         <span class="nb">&amp;</span>      8 <span class="nb">&amp;</span>    138 <span class="nb">&amp;</span>   <span class="k">\nomhz</span> <span class="nb">&amp;</span>     12 <span class="nb">&amp;</span>    205 <span class="nb">&amp;</span> 1306 MHz <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em <span class="k">\hskip</span>1em or1200<span class="k">\_</span>mem2reg<span class="nb">}</span>           <span class="nb">&amp;</span>    --- <span class="nb">&amp;</span>     60 <span class="nb">&amp;</span>   <span class="k">\nomhz</span> <span class="nb">&amp;</span>    --- <span class="nb">&amp;</span>     66 <span class="nb">&amp;</span>   <span class="k">\nomhz</span> <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em <span class="k">\hskip</span>1em or1200<span class="k">\_</span>reg2mem<span class="nb">}</span>           <span class="nb">&amp;</span>    --- <span class="nb">&amp;</span>     29 <span class="nb">&amp;</span>   <span class="k">\nomhz</span> <span class="nb">&amp;</span>    --- <span class="nb">&amp;</span>     29 <span class="nb">&amp;</span>   <span class="k">\nomhz</span> <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em or1200<span class="k">\_</span>mult<span class="k">\_</span>mac<span class="nb">}</span>                   <span class="nb">&amp;</span>    394 <span class="nb">&amp;</span>   2209 <span class="nb">&amp;</span>  240 MHz <span class="nb">&amp;</span>    394 <span class="nb">&amp;</span>   2230 <span class="nb">&amp;</span>  241 MHz <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em <span class="k">\hskip</span>1em or1200<span class="k">\_</span>amultp2<span class="k">\_</span>32x32<span class="nb">}</span>    <span class="nb">&amp;</span>    256 <span class="nb">&amp;</span>   1783 <span class="nb">&amp;</span>  240 MHz <span class="nb">&amp;</span>    256 <span class="nb">&amp;</span>   1770 <span class="nb">&amp;</span>  241 MHz <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em or1200<span class="k">\_</span>operandmuxes<span class="nb">}</span>                <span class="nb">&amp;</span>     65 <span class="nb">&amp;</span>    129 <span class="nb">&amp;</span> 1145 MHz <span class="nb">&amp;</span>     65 <span class="nb">&amp;</span>    129 <span class="nb">&amp;</span> 1145 MHz <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em or1200<span class="k">\_</span>rf<span class="nb">}</span>                          <span class="nb">&amp;</span>   1041 <span class="nb">&amp;</span>   1722 <span class="nb">&amp;</span>  822 MHz <span class="nb">&amp;</span>   1042 <span class="nb">&amp;</span>   1722 <span class="nb">&amp;</span>  581 MHz <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em or1200<span class="k">\_</span>sprs<span class="nb">}</span>                        <span class="nb">&amp;</span>     18 <span class="nb">&amp;</span>    432 <span class="nb">&amp;</span>  724 MHz <span class="nb">&amp;</span>     18 <span class="nb">&amp;</span>    469 <span class="nb">&amp;</span>  722 MHz <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em or1200<span class="k">\_</span>wbmux<span class="nb">}</span>                       <span class="nb">&amp;</span>     33 <span class="nb">&amp;</span>     93 <span class="nb">&amp;</span>   <span class="k">\nomhz</span> <span class="nb">&amp;</span>     33 <span class="nb">&amp;</span>     78 <span class="nb">&amp;</span>   <span class="k">\nomhz</span> <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em or1200<span class="k">\_</span>dc<span class="k">\_</span>top<span class="nb">}</span>                     <span class="nb">&amp;</span>    --- <span class="nb">&amp;</span>      5 <span class="nb">&amp;</span>   <span class="k">\nomhz</span> <span class="nb">&amp;</span>    --- <span class="nb">&amp;</span>      5 <span class="nb">&amp;</span>   <span class="k">\nomhz</span> <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em or1200<span class="k">\_</span>dmmu<span class="k">\_</span>top<span class="nb">}</span>                   <span class="nb">&amp;</span>   2445 <span class="nb">&amp;</span>   1004 <span class="nb">&amp;</span>   <span class="k">\nomhz</span> <span class="nb">&amp;</span>   2445 <span class="nb">&amp;</span>   1043 <span class="nb">&amp;</span>   <span class="k">\nomhz</span> <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em <span class="k">\hskip</span>1em or1200<span class="k">\_</span>dmmu<span class="k">\_</span>tlb<span class="nb">}</span>         <span class="nb">&amp;</span>   2444 <span class="nb">&amp;</span>    975 <span class="nb">&amp;</span>   <span class="k">\nomhz</span> <span class="nb">&amp;</span>   2444 <span class="nb">&amp;</span>   1013 <span class="nb">&amp;</span>   <span class="k">\nomhz</span> <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em or1200<span class="k">\_</span>du<span class="nb">}</span>                          <span class="nb">&amp;</span>     67 <span class="nb">&amp;</span>     56 <span class="nb">&amp;</span>  859 MHz <span class="nb">&amp;</span>     67 <span class="nb">&amp;</span>     56 <span class="nb">&amp;</span>  859 MHz <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em or1200<span class="k">\_</span>ic<span class="k">\_</span>top<span class="nb">}</span>                     <span class="nb">&amp;</span>     39 <span class="nb">&amp;</span>    100 <span class="nb">&amp;</span>  527 MHz <span class="nb">&amp;</span>     41 <span class="nb">&amp;</span>    136 <span class="nb">&amp;</span>  514 MHz <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em <span class="k">\hskip</span>1em or1200<span class="k">\_</span>ic<span class="k">\_</span>fsm<span class="nb">}</span>           <span class="nb">&amp;</span>     40 <span class="nb">&amp;</span>     42 <span class="nb">&amp;</span>  408 MHz <span class="nb">&amp;</span>     40 <span class="nb">&amp;</span>     75 <span class="nb">&amp;</span>  484 MHz <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em or1200<span class="k">\_</span>pic<span class="nb">}</span>                         <span class="nb">&amp;</span>     38 <span class="nb">&amp;</span>     50 <span class="nb">&amp;</span> 1169 MHz <span class="nb">&amp;</span>     38 <span class="nb">&amp;</span>     50 <span class="nb">&amp;</span> 1177 MHz <span class="k">\\</span>
		<span class="nb">{</span><span class="k">\tt</span> <span class="k">\hskip</span>1em or1200<span class="k">\_</span>tt<span class="nb">}</span>                          <span class="nb">&amp;</span>     64 <span class="nb">&amp;</span>    112 <span class="nb">&amp;</span>  370 MHz <span class="nb">&amp;</span>     64 <span class="nb">&amp;</span>    186 <span class="nb">&amp;</span>  437 MHz <span class="k">\\</span>
	<span class="k">\end</span><span class="nb">{</span>tabular<span class="nb">}</span>
	<span class="k">\caption</span><span class="nb">{</span>Synthesis results (as reported by XST) for OpenMSP430 and OpenRISC 1200<span class="nb">}</span>
	<span class="k">\label</span><span class="nb">{</span>tab:synth-test<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>table<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>Conclusion and Future Work<span class="nb">}</span>

Yosys is capable of correctly synthesizing real-world Verilog designs. The
generated netlists are of a decent quality. However, in cases where dedicated
hardware resources should be used for certain functions it is of course
necessary to implement proper technology mapping for these functions in
Yosys. This can be as easy as calling the <span class="nb">{</span><span class="k">\tt</span> techmap<span class="nb">}</span> pass with an
architecture-specific mapping file in the synthesis script. As no such thing
has been done in the above tests, it is only natural that the resulting designs
cannot benefit from these dedicated hardware resources.

Therefore future work includes the implementation of architecture-specific
technology mappings besides additional frontends (VHDL), backends (EDIF),
and above all else, application specific passes. After all, this was
the main motivation for the development of Yosys in the first place.
</pre></div>
</code></pre></td></tr></table>
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