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<a id='n380' href='#n380'>380</a>
<a id='n381' href='#n381'>381</a>
<a id='n382' href='#n382'>382</a>
<a id='n383' href='#n383'>383</a>
<a id='n384' href='#n384'>384</a>
<a id='n385' href='#n385'>385</a>
<a id='n386' href='#n386'>386</a>
<a id='n387' href='#n387'>387</a>
<a id='n388' href='#n388'>388</a>
<a id='n389' href='#n389'>389</a>
<a id='n390' href='#n390'>390</a>
<a id='n391' href='#n391'>391</a>
<a id='n392' href='#n392'>392</a>
<a id='n393' href='#n393'>393</a>
<a id='n394' href='#n394'>394</a>
<a id='n395' href='#n395'>395</a>
<a id='n396' href='#n396'>396</a>
<a id='n397' href='#n397'>397</a>
<a id='n398' href='#n398'>398</a>
<a id='n399' href='#n399'>399</a>
<a id='n400' href='#n400'>400</a>
<a id='n401' href='#n401'>401</a>
<a id='n402' href='#n402'>402</a>
<a id='n403' href='#n403'>403</a>
<a id='n404' href='#n404'>404</a>
<a id='n405' href='#n405'>405</a>
<a id='n406' href='#n406'>406</a>
<a id='n407' href='#n407'>407</a>
<a id='n408' href='#n408'>408</a>
<a id='n409' href='#n409'>409</a>
<a id='n410' href='#n410'>410</a>
<a id='n411' href='#n411'>411</a>
<a id='n412' href='#n412'>412</a>
<a id='n413' href='#n413'>413</a>
<a id='n414' href='#n414'>414</a>
<a id='n415' href='#n415'>415</a>
<a id='n416' href='#n416'>416</a>
<a id='n417' href='#n417'>417</a>
<a id='n418' href='#n418'>418</a>
<a id='n419' href='#n419'>419</a>
<a id='n420' href='#n420'>420</a>
<a id='n421' href='#n421'>421</a>
<a id='n422' href='#n422'>422</a>
<a id='n423' href='#n423'>423</a>
<a id='n424' href='#n424'>424</a>
<a id='n425' href='#n425'>425</a>
<a id='n426' href='#n426'>426</a>
<a id='n427' href='#n427'>427</a>
<a id='n428' href='#n428'>428</a>
<a id='n429' href='#n429'>429</a>
<a id='n430' href='#n430'>430</a>
<a id='n431' href='#n431'>431</a>
<a id='n432' href='#n432'>432</a>
<a id='n433' href='#n433'>433</a>
<a id='n434' href='#n434'>434</a>
<a id='n435' href='#n435'>435</a>
<a id='n436' href='#n436'>436</a>
<a id='n437' href='#n437'>437</a>
<a id='n438' href='#n438'>438</a>
<a id='n439' href='#n439'>439</a>
<a id='n440' href='#n440'>440</a>
<a id='n441' href='#n441'>441</a>
<a id='n442' href='#n442'>442</a>
<a id='n443' href='#n443'>443</a>
<a id='n444' href='#n444'>444</a>
<a id='n445' href='#n445'>445</a>
<a id='n446' href='#n446'>446</a>
<a id='n447' href='#n447'>447</a>
<a id='n448' href='#n448'>448</a>
<a id='n449' href='#n449'>449</a>
<a id='n450' href='#n450'>450</a>
<a id='n451' href='#n451'>451</a>
<a id='n452' href='#n452'>452</a>
<a id='n453' href='#n453'>453</a>
<a id='n454' href='#n454'>454</a>
<a id='n455' href='#n455'>455</a>
<a id='n456' href='#n456'>456</a>
<a id='n457' href='#n457'>457</a>
<a id='n458' href='#n458'>458</a>
<a id='n459' href='#n459'>459</a>
<a id='n460' href='#n460'>460</a>
<a id='n461' href='#n461'>461</a>
<a id='n462' href='#n462'>462</a>
<a id='n463' href='#n463'>463</a>
<a id='n464' href='#n464'>464</a>
<a id='n465' href='#n465'>465</a>
<a id='n466' href='#n466'>466</a>
<a id='n467' href='#n467'>467</a>
<a id='n468' href='#n468'>468</a>
<a id='n469' href='#n469'>469</a>
<a id='n470' href='#n470'>470</a>
<a id='n471' href='#n471'>471</a>
<a id='n472' href='#n472'>472</a>
<a id='n473' href='#n473'>473</a>
<a id='n474' href='#n474'>474</a>
<a id='n475' href='#n475'>475</a>
<a id='n476' href='#n476'>476</a>
<a id='n477' href='#n477'>477</a>
<a id='n478' href='#n478'>478</a>
<a id='n479' href='#n479'>479</a>
<a id='n480' href='#n480'>480</a>
<a id='n481' href='#n481'>481</a>
<a id='n482' href='#n482'>482</a>
<a id='n483' href='#n483'>483</a>
<a id='n484' href='#n484'>484</a>
<a id='n485' href='#n485'>485</a>
<a id='n486' href='#n486'>486</a>
<a id='n487' href='#n487'>487</a>
<a id='n488' href='#n488'>488</a>
<a id='n489' href='#n489'>489</a>
<a id='n490' href='#n490'>490</a>
<a id='n491' href='#n491'>491</a>
<a id='n492' href='#n492'>492</a>
<a id='n493' href='#n493'>493</a>
<a id='n494' href='#n494'>494</a>
<a id='n495' href='#n495'>495</a>
<a id='n496' href='#n496'>496</a>
<a id='n497' href='#n497'>497</a>
<a id='n498' href='#n498'>498</a>
<a id='n499' href='#n499'>499</a>
<a id='n500' href='#n500'>500</a>
<a id='n501' href='#n501'>501</a>
<a id='n502' href='#n502'>502</a>
<a id='n503' href='#n503'>503</a>
<a id='n504' href='#n504'>504</a>
<a id='n505' href='#n505'>505</a>
<a id='n506' href='#n506'>506</a>
<a id='n507' href='#n507'>507</a>
<a id='n508' href='#n508'>508</a>
<a id='n509' href='#n509'>509</a>
<a id='n510' href='#n510'>510</a>
<a id='n511' href='#n511'>511</a>
<a id='n512' href='#n512'>512</a>
<a id='n513' href='#n513'>513</a>
<a id='n514' href='#n514'>514</a>
<a id='n515' href='#n515'>515</a>
<a id='n516' href='#n516'>516</a>
<a id='n517' href='#n517'>517</a>
<a id='n518' href='#n518'>518</a>
<a id='n519' href='#n519'>519</a>
<a id='n520' href='#n520'>520</a>
<a id='n521' href='#n521'>521</a>
<a id='n522' href='#n522'>522</a>
<a id='n523' href='#n523'>523</a>
<a id='n524' href='#n524'>524</a>
<a id='n525' href='#n525'>525</a>
<a id='n526' href='#n526'>526</a>
<a id='n527' href='#n527'>527</a>
<a id='n528' href='#n528'>528</a>
<a id='n529' href='#n529'>529</a>
<a id='n530' href='#n530'>530</a>
<a id='n531' href='#n531'>531</a>
<a id='n532' href='#n532'>532</a>
<a id='n533' href='#n533'>533</a>
<a id='n534' href='#n534'>534</a>
<a id='n535' href='#n535'>535</a>
<a id='n536' href='#n536'>536</a>
<a id='n537' href='#n537'>537</a>
<a id='n538' href='#n538'>538</a>
<a id='n539' href='#n539'>539</a>
<a id='n540' href='#n540'>540</a>
<a id='n541' href='#n541'>541</a>
<a id='n542' href='#n542'>542</a>
<a id='n543' href='#n543'>543</a>
<a id='n544' href='#n544'>544</a>
<a id='n545' href='#n545'>545</a>
<a id='n546' href='#n546'>546</a>
<a id='n547' href='#n547'>547</a>
<a id='n548' href='#n548'>548</a>
<a id='n549' href='#n549'>549</a>
<a id='n550' href='#n550'>550</a>
<a id='n551' href='#n551'>551</a>
<a id='n552' href='#n552'>552</a>
<a id='n553' href='#n553'>553</a>
<a id='n554' href='#n554'>554</a>
<a id='n555' href='#n555'>555</a>
<a id='n556' href='#n556'>556</a>
<a id='n557' href='#n557'>557</a>
<a id='n558' href='#n558'>558</a>
<a id='n559' href='#n559'>559</a>
<a id='n560' href='#n560'>560</a>
<a id='n561' href='#n561'>561</a>
<a id='n562' href='#n562'>562</a>
<a id='n563' href='#n563'>563</a>
<a id='n564' href='#n564'>564</a>
<a id='n565' href='#n565'>565</a>
<a id='n566' href='#n566'>566</a>
<a id='n567' href='#n567'>567</a>
<a id='n568' href='#n568'>568</a>
<a id='n569' href='#n569'>569</a>
<a id='n570' href='#n570'>570</a>
<a id='n571' href='#n571'>571</a>
<a id='n572' href='#n572'>572</a>
<a id='n573' href='#n573'>573</a>
<a id='n574' href='#n574'>574</a>
<a id='n575' href='#n575'>575</a>
<a id='n576' href='#n576'>576</a>
<a id='n577' href='#n577'>577</a>
<a id='n578' href='#n578'>578</a>
<a id='n579' href='#n579'>579</a>
<a id='n580' href='#n580'>580</a>
<a id='n581' href='#n581'>581</a>
<a id='n582' href='#n582'>582</a>
<a id='n583' href='#n583'>583</a>
<a id='n584' href='#n584'>584</a>
<a id='n585' href='#n585'>585</a>
<a id='n586' href='#n586'>586</a>
<a id='n587' href='#n587'>587</a>
<a id='n588' href='#n588'>588</a>
<a id='n589' href='#n589'>589</a>
<a id='n590' href='#n590'>590</a>
<a id='n591' href='#n591'>591</a>
<a id='n592' href='#n592'>592</a>
<a id='n593' href='#n593'>593</a>
<a id='n594' href='#n594'>594</a>
<a id='n595' href='#n595'>595</a>
<a id='n596' href='#n596'>596</a>
<a id='n597' href='#n597'>597</a>
<a id='n598' href='#n598'>598</a>
<a id='n599' href='#n599'>599</a>
<a id='n600' href='#n600'>600</a>
<a id='n601' href='#n601'>601</a>
<a id='n602' href='#n602'>602</a>
<a id='n603' href='#n603'>603</a>
<a id='n604' href='#n604'>604</a>
<a id='n605' href='#n605'>605</a>
<a id='n606' href='#n606'>606</a>
<a id='n607' href='#n607'>607</a>
<a id='n608' href='#n608'>608</a>
<a id='n609' href='#n609'>609</a>
<a id='n610' href='#n610'>610</a>
<a id='n611' href='#n611'>611</a>
<a id='n612' href='#n612'>612</a>
<a id='n613' href='#n613'>613</a>
<a id='n614' href='#n614'>614</a>
<a id='n615' href='#n615'>615</a>
<a id='n616' href='#n616'>616</a>
<a id='n617' href='#n617'>617</a>
<a id='n618' href='#n618'>618</a>
<a id='n619' href='#n619'>619</a>
<a id='n620' href='#n620'>620</a>
<a id='n621' href='#n621'>621</a>
<a id='n622' href='#n622'>622</a>
<a id='n623' href='#n623'>623</a>
<a id='n624' href='#n624'>624</a>
<a id='n625' href='#n625'>625</a>
<a id='n626' href='#n626'>626</a>
<a id='n627' href='#n627'>627</a>
<a id='n628' href='#n628'>628</a>
<a id='n629' href='#n629'>629</a>
<a id='n630' href='#n630'>630</a>
<a id='n631' href='#n631'>631</a>
<a id='n632' href='#n632'>632</a>
<a id='n633' href='#n633'>633</a>
<a id='n634' href='#n634'>634</a>
<a id='n635' href='#n635'>635</a>
<a id='n636' href='#n636'>636</a>
<a id='n637' href='#n637'>637</a>
<a id='n638' href='#n638'>638</a>
<a id='n639' href='#n639'>639</a>
<a id='n640' href='#n640'>640</a>
<a id='n641' href='#n641'>641</a>
<a id='n642' href='#n642'>642</a>
<a id='n643' href='#n643'>643</a>
<a id='n644' href='#n644'>644</a>
<a id='n645' href='#n645'>645</a>
<a id='n646' href='#n646'>646</a>
<a id='n647' href='#n647'>647</a>
<a id='n648' href='#n648'>648</a>
<a id='n649' href='#n649'>649</a>
<a id='n650' href='#n650'>650</a>
<a id='n651' href='#n651'>651</a>
<a id='n652' href='#n652'>652</a>
<a id='n653' href='#n653'>653</a>
<a id='n654' href='#n654'>654</a>
<a id='n655' href='#n655'>655</a>
<a id='n656' href='#n656'>656</a>
<a id='n657' href='#n657'>657</a>
<a id='n658' href='#n658'>658</a>
<a id='n659' href='#n659'>659</a>
<a id='n660' href='#n660'>660</a>
<a id='n661' href='#n661'>661</a>
<a id='n662' href='#n662'>662</a>
<a id='n663' href='#n663'>663</a>
<a id='n664' href='#n664'>664</a>
<a id='n665' href='#n665'>665</a>
<a id='n666' href='#n666'>666</a>
<a id='n667' href='#n667'>667</a>
<a id='n668' href='#n668'>668</a>
<a id='n669' href='#n669'>669</a>
<a id='n670' href='#n670'>670</a>
<a id='n671' href='#n671'>671</a>
<a id='n672' href='#n672'>672</a>
<a id='n673' href='#n673'>673</a>
<a id='n674' href='#n674'>674</a>
<a id='n675' href='#n675'>675</a>
<a id='n676' href='#n676'>676</a>
<a id='n677' href='#n677'>677</a>
<a id='n678' href='#n678'>678</a>
<a id='n679' href='#n679'>679</a>
<a id='n680' href='#n680'>680</a>
<a id='n681' href='#n681'>681</a>
<a id='n682' href='#n682'>682</a>
<a id='n683' href='#n683'>683</a>
<a id='n684' href='#n684'>684</a>
<a id='n685' href='#n685'>685</a>
<a id='n686' href='#n686'>686</a>
<a id='n687' href='#n687'>687</a>
<a id='n688' href='#n688'>688</a>
<a id='n689' href='#n689'>689</a>
<a id='n690' href='#n690'>690</a>
<a id='n691' href='#n691'>691</a>
<a id='n692' href='#n692'>692</a>
<a id='n693' href='#n693'>693</a>
<a id='n694' href='#n694'>694</a>
<a id='n695' href='#n695'>695</a>
<a id='n696' href='#n696'>696</a>
<a id='n697' href='#n697'>697</a>
<a id='n698' href='#n698'>698</a>
<a id='n699' href='#n699'>699</a>
<a id='n700' href='#n700'>700</a>
<a id='n701' href='#n701'>701</a>
<a id='n702' href='#n702'>702</a>
<a id='n703' href='#n703'>703</a>
<a id='n704' href='#n704'>704</a>
<a id='n705' href='#n705'>705</a>
<a id='n706' href='#n706'>706</a>
<a id='n707' href='#n707'>707</a>
<a id='n708' href='#n708'>708</a>
<a id='n709' href='#n709'>709</a>
<a id='n710' href='#n710'>710</a>
<a id='n711' href='#n711'>711</a>
<a id='n712' href='#n712'>712</a>
<a id='n713' href='#n713'>713</a>
<a id='n714' href='#n714'>714</a>
<a id='n715' href='#n715'>715</a>
<a id='n716' href='#n716'>716</a>
<a id='n717' href='#n717'>717</a>
<a id='n718' href='#n718'>718</a>
<a id='n719' href='#n719'>719</a>
<a id='n720' href='#n720'>720</a>
<a id='n721' href='#n721'>721</a>
<a id='n722' href='#n722'>722</a>
<a id='n723' href='#n723'>723</a>
<a id='n724' href='#n724'>724</a>
<a id='n725' href='#n725'>725</a>
<a id='n726' href='#n726'>726</a>
<a id='n727' href='#n727'>727</a>
<a id='n728' href='#n728'>728</a>
<a id='n729' href='#n729'>729</a>
<a id='n730' href='#n730'>730</a>
<a id='n731' href='#n731'>731</a>
<a id='n732' href='#n732'>732</a>
<a id='n733' href='#n733'>733</a>
<a id='n734' href='#n734'>734</a>
<a id='n735' href='#n735'>735</a>
<a id='n736' href='#n736'>736</a>
<a id='n737' href='#n737'>737</a>
<a id='n738' href='#n738'>738</a>
<a id='n739' href='#n739'>739</a>
<a id='n740' href='#n740'>740</a>
<a id='n741' href='#n741'>741</a>
<a id='n742' href='#n742'>742</a>
<a id='n743' href='#n743'>743</a>
<a id='n744' href='#n744'>744</a>
<a id='n745' href='#n745'>745</a>
<a id='n746' href='#n746'>746</a>
<a id='n747' href='#n747'>747</a>
<a id='n748' href='#n748'>748</a>
<a id='n749' href='#n749'>749</a>
<a id='n750' href='#n750'>750</a>
<a id='n751' href='#n751'>751</a>
<a id='n752' href='#n752'>752</a>
<a id='n753' href='#n753'>753</a>
<a id='n754' href='#n754'>754</a>
<a id='n755' href='#n755'>755</a>
<a id='n756' href='#n756'>756</a>
<a id='n757' href='#n757'>757</a>
<a id='n758' href='#n758'>758</a>
<a id='n759' href='#n759'>759</a>
<a id='n760' href='#n760'>760</a>
<a id='n761' href='#n761'>761</a>
<a id='n762' href='#n762'>762</a>
<a id='n763' href='#n763'>763</a>
<a id='n764' href='#n764'>764</a>
<a id='n765' href='#n765'>765</a>
<a id='n766' href='#n766'>766</a>
<a id='n767' href='#n767'>767</a>
<a id='n768' href='#n768'>768</a>
<a id='n769' href='#n769'>769</a>
<a id='n770' href='#n770'>770</a>
<a id='n771' href='#n771'>771</a>
<a id='n772' href='#n772'>772</a>
<a id='n773' href='#n773'>773</a>
<a id='n774' href='#n774'>774</a>
<a id='n775' href='#n775'>775</a>
<a id='n776' href='#n776'>776</a>
<a id='n777' href='#n777'>777</a>
<a id='n778' href='#n778'>778</a>
<a id='n779' href='#n779'>779</a>
<a id='n780' href='#n780'>780</a>
<a id='n781' href='#n781'>781</a>
<a id='n782' href='#n782'>782</a>
<a id='n783' href='#n783'>783</a>
<a id='n784' href='#n784'>784</a>
<a id='n785' href='#n785'>785</a>
<a id='n786' href='#n786'>786</a>
<a id='n787' href='#n787'>787</a>
<a id='n788' href='#n788'>788</a>
<a id='n789' href='#n789'>789</a>
<a id='n790' href='#n790'>790</a>
<a id='n791' href='#n791'>791</a>
<a id='n792' href='#n792'>792</a>
<a id='n793' href='#n793'>793</a>
<a id='n794' href='#n794'>794</a>
<a id='n795' href='#n795'>795</a>
<a id='n796' href='#n796'>796</a>
<a id='n797' href='#n797'>797</a>
<a id='n798' href='#n798'>798</a>
<a id='n799' href='#n799'>799</a>
<a id='n800' href='#n800'>800</a>
<a id='n801' href='#n801'>801</a>
<a id='n802' href='#n802'>802</a>
<a id='n803' href='#n803'>803</a>
<a id='n804' href='#n804'>804</a>
<a id='n805' href='#n805'>805</a>
<a id='n806' href='#n806'>806</a>
<a id='n807' href='#n807'>807</a>
<a id='n808' href='#n808'>808</a>
<a id='n809' href='#n809'>809</a>
<a id='n810' href='#n810'>810</a>
<a id='n811' href='#n811'>811</a>
<a id='n812' href='#n812'>812</a>
<a id='n813' href='#n813'>813</a>
<a id='n814' href='#n814'>814</a>
<a id='n815' href='#n815'>815</a>
<a id='n816' href='#n816'>816</a>
<a id='n817' href='#n817'>817</a>
<a id='n818' href='#n818'>818</a>
<a id='n819' href='#n819'>819</a>
<a id='n820' href='#n820'>820</a>
<a id='n821' href='#n821'>821</a>
<a id='n822' href='#n822'>822</a>
<a id='n823' href='#n823'>823</a>
<a id='n824' href='#n824'>824</a>
<a id='n825' href='#n825'>825</a>
<a id='n826' href='#n826'>826</a>
<a id='n827' href='#n827'>827</a>
<a id='n828' href='#n828'>828</a>
<a id='n829' href='#n829'>829</a>
<a id='n830' href='#n830'>830</a>
<a id='n831' href='#n831'>831</a>
<a id='n832' href='#n832'>832</a>
<a id='n833' href='#n833'>833</a>
<a id='n834' href='#n834'>834</a>
<a id='n835' href='#n835'>835</a>
<a id='n836' href='#n836'>836</a>
<a id='n837' href='#n837'>837</a>
<a id='n838' href='#n838'>838</a>
<a id='n839' href='#n839'>839</a>
<a id='n840' href='#n840'>840</a>
<a id='n841' href='#n841'>841</a>
<a id='n842' href='#n842'>842</a>
<a id='n843' href='#n843'>843</a>
<a id='n844' href='#n844'>844</a>
<a id='n845' href='#n845'>845</a>
<a id='n846' href='#n846'>846</a>
<a id='n847' href='#n847'>847</a>
<a id='n848' href='#n848'>848</a>
<a id='n849' href='#n849'>849</a>
<a id='n850' href='#n850'>850</a>
<a id='n851' href='#n851'>851</a>
<a id='n852' href='#n852'>852</a>
<a id='n853' href='#n853'>853</a>
<a id='n854' href='#n854'>854</a>
<a id='n855' href='#n855'>855</a>
<a id='n856' href='#n856'>856</a>
<a id='n857' href='#n857'>857</a>
<a id='n858' href='#n858'>858</a>
<a id='n859' href='#n859'>859</a>
<a id='n860' href='#n860'>860</a>
<a id='n861' href='#n861'>861</a>
<a id='n862' href='#n862'>862</a>
<a id='n863' href='#n863'>863</a>
<a id='n864' href='#n864'>864</a>
<a id='n865' href='#n865'>865</a>
<a id='n866' href='#n866'>866</a>
<a id='n867' href='#n867'>867</a>
<a id='n868' href='#n868'>868</a>
<a id='n869' href='#n869'>869</a>
<a id='n870' href='#n870'>870</a>
<a id='n871' href='#n871'>871</a>
<a id='n872' href='#n872'>872</a>
<a id='n873' href='#n873'>873</a>
<a id='n874' href='#n874'>874</a>
<a id='n875' href='#n875'>875</a>
<a id='n876' href='#n876'>876</a>
<a id='n877' href='#n877'>877</a>
<a id='n878' href='#n878'>878</a>
<a id='n879' href='#n879'>879</a>
<a id='n880' href='#n880'>880</a>
<a id='n881' href='#n881'>881</a>
<a id='n882' href='#n882'>882</a>
<a id='n883' href='#n883'>883</a>
<a id='n884' href='#n884'>884</a>
<a id='n885' href='#n885'>885</a>
<a id='n886' href='#n886'>886</a>
<a id='n887' href='#n887'>887</a>
<a id='n888' href='#n888'>888</a>
<a id='n889' href='#n889'>889</a>
<a id='n890' href='#n890'>890</a>
<a id='n891' href='#n891'>891</a>
<a id='n892' href='#n892'>892</a>
<a id='n893' href='#n893'>893</a>
<a id='n894' href='#n894'>894</a>
<a id='n895' href='#n895'>895</a>
<a id='n896' href='#n896'>896</a>
<a id='n897' href='#n897'>897</a>
<a id='n898' href='#n898'>898</a>
<a id='n899' href='#n899'>899</a>
<a id='n900' href='#n900'>900</a>
<a id='n901' href='#n901'>901</a>
<a id='n902' href='#n902'>902</a>
<a id='n903' href='#n903'>903</a>
<a id='n904' href='#n904'>904</a>
<a id='n905' href='#n905'>905</a>
<a id='n906' href='#n906'>906</a>
<a id='n907' href='#n907'>907</a>
<a id='n908' href='#n908'>908</a>
<a id='n909' href='#n909'>909</a>
<a id='n910' href='#n910'>910</a>
<a id='n911' href='#n911'>911</a>
<a id='n912' href='#n912'>912</a>
<a id='n913' href='#n913'>913</a>
<a id='n914' href='#n914'>914</a>
<a id='n915' href='#n915'>915</a>
<a id='n916' href='#n916'>916</a>
<a id='n917' href='#n917'>917</a>
<a id='n918' href='#n918'>918</a>
<a id='n919' href='#n919'>919</a>
<a id='n920' href='#n920'>920</a>
<a id='n921' href='#n921'>921</a>
<a id='n922' href='#n922'>922</a>
<a id='n923' href='#n923'>923</a>
<a id='n924' href='#n924'>924</a>
<a id='n925' href='#n925'>925</a>
<a id='n926' href='#n926'>926</a>
<a id='n927' href='#n927'>927</a>
<a id='n928' href='#n928'>928</a>
<a id='n929' href='#n929'>929</a>
<a id='n930' href='#n930'>930</a>
<a id='n931' href='#n931'>931</a>
<a id='n932' href='#n932'>932</a>
<a id='n933' href='#n933'>933</a>
<a id='n934' href='#n934'>934</a>
<a id='n935' href='#n935'>935</a>
<a id='n936' href='#n936'>936</a>
<a id='n937' href='#n937'>937</a>
<a id='n938' href='#n938'>938</a>
<a id='n939' href='#n939'>939</a>
<a id='n940' href='#n940'>940</a>
<a id='n941' href='#n941'>941</a>
<a id='n942' href='#n942'>942</a>
<a id='n943' href='#n943'>943</a>
<a id='n944' href='#n944'>944</a>
<a id='n945' href='#n945'>945</a>
<a id='n946' href='#n946'>946</a>
<a id='n947' href='#n947'>947</a>
<a id='n948' href='#n948'>948</a>
<a id='n949' href='#n949'>949</a>
<a id='n950' href='#n950'>950</a>
<a id='n951' href='#n951'>951</a>
<a id='n952' href='#n952'>952</a>
<a id='n953' href='#n953'>953</a>
<a id='n954' href='#n954'>954</a>
<a id='n955' href='#n955'>955</a>
<a id='n956' href='#n956'>956</a>
<a id='n957' href='#n957'>957</a>
<a id='n958' href='#n958'>958</a>
<a id='n959' href='#n959'>959</a>
<a id='n960' href='#n960'>960</a>
<a id='n961' href='#n961'>961</a>
<a id='n962' href='#n962'>962</a>
<a id='n963' href='#n963'>963</a>
<a id='n964' href='#n964'>964</a>
<a id='n965' href='#n965'>965</a>
<a id='n966' href='#n966'>966</a>
<a id='n967' href='#n967'>967</a>
<a id='n968' href='#n968'>968</a>
<a id='n969' href='#n969'>969</a>
<a id='n970' href='#n970'>970</a>
<a id='n971' href='#n971'>971</a>
<a id='n972' href='#n972'>972</a>
<a id='n973' href='#n973'>973</a>
<a id='n974' href='#n974'>974</a>
<a id='n975' href='#n975'>975</a>
<a id='n976' href='#n976'>976</a>
<a id='n977' href='#n977'>977</a>
<a id='n978' href='#n978'>978</a>
<a id='n979' href='#n979'>979</a>
<a id='n980' href='#n980'>980</a>
<a id='n981' href='#n981'>981</a>
<a id='n982' href='#n982'>982</a>
<a id='n983' href='#n983'>983</a>
<a id='n984' href='#n984'>984</a>
<a id='n985' href='#n985'>985</a>
<a id='n986' href='#n986'>986</a>
<a id='n987' href='#n987'>987</a>
<a id='n988' href='#n988'>988</a>
<a id='n989' href='#n989'>989</a>
<a id='n990' href='#n990'>990</a>
<a id='n991' href='#n991'>991</a>
<a id='n992' href='#n992'>992</a>
<a id='n993' href='#n993'>993</a>
<a id='n994' href='#n994'>994</a>
<a id='n995' href='#n995'>995</a>
<a id='n996' href='#n996'>996</a>
<a id='n997' href='#n997'>997</a>
<a id='n998' href='#n998'>998</a>
<a id='n999' href='#n999'>999</a>
<a id='n1000' href='#n1000'>1000</a>
<a id='n1001' href='#n1001'>1001</a>
<a id='n1002' href='#n1002'>1002</a>
<a id='n1003' href='#n1003'>1003</a>
<a id='n1004' href='#n1004'>1004</a>
<a id='n1005' href='#n1005'>1005</a>
<a id='n1006' href='#n1006'>1006</a>
<a id='n1007' href='#n1007'>1007</a>
</pre></td>
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.highlight .il { color: #0000DD; font-weight: bold } /* Literal.Number.Integer.Long */</style><div class="highlight"><pre><span></span><span class="k">\chapter</span><span class="nb">{</span>Internal Cell Library<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>chapter:celllib<span class="nb">}</span>

Most of the passes in Yosys operate on netlists, i.e.~they only care about the RTLIL::Wire and RTLIL::Cell
objects in an RTLIL::Module. This chapter discusses the cell types used by Yosys to represent a behavioural
design internally.

This chapter is split in two parts. In the first part the internal RTL cells are covered. These cells
are used to represent the design on a coarse grain level. Like in the original HDL code on this level the
cells operate on vectors of signals and complex cells like adders exist. In the second part the internal
gate cells are covered. These cells are used to represent the design on a fine-grain gate-level. All cells
from this category operate on single bit signals.

<span class="k">\section</span><span class="nb">{</span>RTL Cells<span class="nb">}</span>

Most of the RTL cells closely resemble the operators available in HDLs such as
Verilog or VHDL. Therefore Verilog operators are used in the following sections
to define the behaviour of the RTL cells.

Note that all RTL cells have parameters indicating the size of inputs and outputs. When
passes modify RTL cells they must always keep the values of these parameters in sync with
the size of the signals connected to the inputs and outputs.

Simulation models for the RTL cells can be found in the file <span class="nb">{</span><span class="k">\tt</span> techlibs/common/simlib.v<span class="nb">}</span> in the Yosys
source tree.

<span class="k">\subsection</span><span class="nb">{</span>Unary Operators<span class="nb">}</span>

All unary RTL cells have one input port <span class="k">\B</span><span class="nb">{</span>A<span class="nb">}</span> and one output port <span class="k">\B</span><span class="nb">{</span>Y<span class="nb">}</span>. They also
have the following parameters:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>A<span class="k">\_</span>SIGNED<span class="nb">}</span> <span class="k">\\</span>
Set to a non-zero value if the input <span class="k">\B</span><span class="nb">{</span>A<span class="nb">}</span> is signed and therefore should be sign-extended
when needed.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>A<span class="k">\_</span>WIDTH<span class="nb">}</span> <span class="k">\\</span>
The width of the input port <span class="k">\B</span><span class="nb">{</span>A<span class="nb">}</span>.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>Y<span class="k">\_</span>WIDTH<span class="nb">}</span> <span class="k">\\</span>
The width of the output port <span class="k">\B</span><span class="nb">{</span>Y<span class="nb">}</span>.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

Table~<span class="k">\ref</span><span class="nb">{</span>tab:CellLib<span class="nb">_</span>unary<span class="nb">}</span> lists all cells for unary RTL operators.

<span class="k">\begin</span><span class="nb">{</span>table<span class="nb">}</span>[t!]
<span class="k">\hfil</span>
<span class="k">\begin</span><span class="nb">{</span>tabular<span class="nb">}{</span>ll<span class="nb">}</span>
Verilog <span class="nb">&amp;</span> Cell Type <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y =  ~A ; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>not<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y =  +A ; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>pos<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y =  -A ; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>neg<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y =  <span class="nb">&amp;</span>A ; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>reduce<span class="k">\_</span>and<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y =  |A ; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>reduce<span class="k">\_</span>or<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y =  <span class="nb">^</span>A ; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>reduce<span class="k">\_</span>xor<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = ~<span class="nb">^</span>A ; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>reduce<span class="k">\_</span>xnor<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y =  |A ; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>reduce<span class="k">\_</span>bool<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y =  !A ; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>logic<span class="k">\_</span>not<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>tabular<span class="nb">}</span>
<span class="k">\caption</span><span class="nb">{</span>Cell types for unary operators with their corresponding Verilog expressions.<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>tab:CellLib<span class="nb">_</span>unary<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>table<span class="nb">}</span>

For the unary cells that output a logical value (<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>reduce<span class="k">\_</span>and<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>reduce<span class="k">\_</span>or<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>reduce<span class="k">\_</span>xor<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>reduce<span class="k">\_</span>xnor<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>reduce<span class="k">\_</span>bool<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>logic<span class="k">\_</span>not<span class="nb">}</span>),
when the <span class="k">\B</span><span class="nb">{</span>Y<span class="k">\_</span>WIDTH<span class="nb">}</span> parameter is greater than 1, the output is zero-extended,
and only the least significant bit varies.

Note that <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>reduce<span class="k">\_</span>or<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>reduce<span class="k">\_</span>bool<span class="nb">}</span> actually represent the same
logic function. But the HDL frontends generate them in different situations. A
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>reduce<span class="k">\_</span>or<span class="nb">}</span> cell is generated when the prefix <span class="nb">{</span><span class="k">\tt</span> |<span class="nb">}</span> operator is being used. A
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>reduce<span class="k">\_</span>bool<span class="nb">}</span> cell is generated when a bit vector is used as a condition in
an <span class="nb">{</span><span class="k">\tt</span> if<span class="nb">}</span>-statement or <span class="nb">{</span><span class="k">\tt</span> ?:<span class="nb">}</span>-expression.

<span class="k">\subsection</span><span class="nb">{</span>Binary Operators<span class="nb">}</span>

All binary RTL cells have two input ports <span class="k">\B</span><span class="nb">{</span>A<span class="nb">}</span> and <span class="k">\B</span><span class="nb">{</span>B<span class="nb">}</span> and one output port <span class="k">\B</span><span class="nb">{</span>Y<span class="nb">}</span>. They
also have the following parameters:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>A<span class="k">\_</span>SIGNED<span class="nb">}</span> <span class="k">\\</span>
Set to a non-zero value if the input <span class="k">\B</span><span class="nb">{</span>A<span class="nb">}</span> is signed and therefore should be sign-extended
when needed.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>A<span class="k">\_</span>WIDTH<span class="nb">}</span> <span class="k">\\</span>
The width of the input port <span class="k">\B</span><span class="nb">{</span>A<span class="nb">}</span>.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>B<span class="k">\_</span>SIGNED<span class="nb">}</span> <span class="k">\\</span>
Set to a non-zero value if the input <span class="k">\B</span><span class="nb">{</span>B<span class="nb">}</span> is signed and therefore should be sign-extended
when needed.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>B<span class="k">\_</span>WIDTH<span class="nb">}</span> <span class="k">\\</span>
The width of the input port <span class="k">\B</span><span class="nb">{</span>B<span class="nb">}</span>.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>Y<span class="k">\_</span>WIDTH<span class="nb">}</span> <span class="k">\\</span>
The width of the output port <span class="k">\B</span><span class="nb">{</span>Y<span class="nb">}</span>.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

Table~<span class="k">\ref</span><span class="nb">{</span>tab:CellLib<span class="nb">_</span>binary<span class="nb">}</span> lists all cells for binary RTL operators.

<span class="k">\begin</span><span class="nb">{</span>table<span class="nb">}</span>[t!]
<span class="k">\hfil</span>
<span class="k">\begin</span><span class="nb">{</span>tabular<span class="nb">}</span>[t]<span class="nb">{</span>ll<span class="nb">}</span>
Verilog <span class="nb">&amp;</span> Cell Type <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A  <span class="nb">&amp;</span> B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>and<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A  | B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>or<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A  <span class="nb">^</span> B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>xor<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A ~<span class="nb">^</span> B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>xnor<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A &lt;&lt; B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>shl<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A &gt;&gt; B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>shr<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A &lt;&lt;&lt; B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>sshl<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A &gt;&gt;&gt; B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>sshr<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A <span class="nb">&amp;&amp;</span> B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>logic<span class="k">\_</span>and<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A || B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>logic<span class="k">\_</span>or<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A === B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>eqx<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A !== B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>nex<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\end</span><span class="nb">{</span>tabular<span class="nb">}</span>
<span class="k">\hfil</span>
<span class="k">\begin</span><span class="nb">{</span>tabular<span class="nb">}</span>[t]<span class="nb">{</span>ll<span class="nb">}</span>
Verilog <span class="nb">&amp;</span> Cell Type <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A &lt;  B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>lt<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A &lt;= B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>le<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A == B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>eq<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A != B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>ne<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A &gt;= B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>ge<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A &gt;  B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>gt<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A  + B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>add<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A  - B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>sub<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A  * B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>mul<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A  / B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>div<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A  <span class="c">% B; &amp; {\tt \$mod} \\</span>
<span class="k">\multicolumn</span><span class="nb">{</span>1<span class="nb">}{</span>c<span class="nb">}{</span><span class="k">\tt</span> [N/A]<span class="nb">}</span> <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>divfloor<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\multicolumn</span><span class="nb">{</span>1<span class="nb">}{</span>c<span class="nb">}{</span><span class="k">\tt</span> [N/A]<span class="nb">}</span> <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>modfoor<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A ** B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>pow<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\end</span><span class="nb">{</span>tabular<span class="nb">}</span>
<span class="k">\caption</span><span class="nb">{</span>Cell types for binary operators with their corresponding Verilog expressions.<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>tab:CellLib<span class="nb">_</span>binary<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>table<span class="nb">}</span>

The <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>shl<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>shr<span class="nb">}</span> cells implement logical shifts, whereas the <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>sshl<span class="nb">}</span> and
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>sshr<span class="nb">}</span> cells implement arithmetic shifts. The <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>shl<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>sshl<span class="nb">}</span> cells implement
the same operation. All four of these cells interpret the second operand as unsigned, and require
<span class="k">\B</span><span class="nb">{</span>B<span class="k">\_</span>SIGNED<span class="nb">}</span> to be zero.

Two additional shift operator cells are available that do not directly correspond to any operator
in Verilog, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>shift<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>shiftx<span class="nb">}</span>. The <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>shift<span class="nb">}</span> cell performs a right logical shift
if the second operand is positive (or unsigned), and a left logical shift if it is negative.
The <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>shiftx<span class="nb">}</span> cell performs the same operation as the <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>shift<span class="nb">}</span> cell, but the vacated bit
positions are filled with undef (x) bits, and corresponds to the Verilog indexed part-select expression.

For the binary cells that output a logical value (<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>logic<span class="k">\_</span>and<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>logic<span class="k">\_</span>or<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>eqx<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>nex<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>lt<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>le<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>eq<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>ne<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>ge<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>gt<span class="nb">}</span>), when the <span class="k">\B</span><span class="nb">{</span>Y<span class="k">\_</span>WIDTH<span class="nb">}</span> parameter is greater than 1, the output is zero-extended,
and only the least significant bit varies.

Division and modulo cells are available in two rounding modes. The original <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>div<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>mod<span class="nb">}</span>
cells are based on truncating division, and correspond to the semantics of the verilog <span class="nb">{</span><span class="k">\tt</span> /<span class="nb">}</span> and
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\%</span><span class="nb">}</span> operators. The <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>divfloor<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>modfloor<span class="nb">}</span> cells represent flooring division and
flooring modulo, the latter of which is also known as ``remainder&#39;&#39; in several languages. See
table~<span class="k">\ref</span><span class="nb">{</span>tab:CellLib<span class="nb">_</span>divmod<span class="nb">}</span> for a side-by-side comparison between the different semantics.

<span class="k">\begin</span><span class="nb">{</span>table<span class="nb">}</span>[h]
<span class="k">\hfil</span>
<span class="k">\begin</span><span class="nb">{</span>tabular<span class="nb">}{</span>lr|rr|rr<span class="nb">}</span>
<span class="k">\multirow</span><span class="nb">{</span>2<span class="nb">}{</span>*<span class="nb">}{</span>Division<span class="nb">}</span> <span class="nb">&amp;</span> <span class="k">\multirow</span><span class="nb">{</span>2<span class="nb">}{</span>*<span class="nb">}{</span>Result<span class="nb">}</span> <span class="nb">&amp;</span> <span class="k">\multicolumn</span><span class="nb">{</span>2<span class="nb">}{</span>c|<span class="nb">}{</span>Truncating<span class="nb">}</span> <span class="nb">&amp;</span> <span class="k">\multicolumn</span><span class="nb">{</span>2<span class="nb">}{</span>c<span class="nb">}{</span>Flooring<span class="nb">}</span> <span class="k">\\</span>
               <span class="nb">&amp;</span>            <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>div<span class="nb">}</span> <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>mod<span class="nb">}</span> <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>divfloor<span class="nb">}</span> <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>modfloor<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\hline</span>
<span class="nb">{</span><span class="k">\tt</span> -10 / 3<span class="nb">}</span>  <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> -3.3<span class="nb">}</span> <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> -3<span class="nb">}</span>    <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> -1<span class="nb">}</span>    <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> -4<span class="nb">}</span>         <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> 2<span class="nb">}</span> <span class="k">\\</span>
<span class="nb">{</span><span class="k">\tt</span> 10 / -3<span class="nb">}</span>  <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> -3.3<span class="nb">}</span> <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> -3<span class="nb">}</span>    <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> 1<span class="nb">}</span>     <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> -4<span class="nb">}</span>         <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> -2<span class="nb">}</span> <span class="k">\\</span>
<span class="nb">{</span><span class="k">\tt</span> -10 / -3<span class="nb">}</span> <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> 3.3<span class="nb">}</span>  <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> 3<span class="nb">}</span>     <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> -1<span class="nb">}</span>    <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> 3<span class="nb">}</span>          <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> -1<span class="nb">}</span> <span class="k">\\</span>
<span class="nb">{</span><span class="k">\tt</span> 10 / 3<span class="nb">}</span>   <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> 3.3<span class="nb">}</span>  <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> 3<span class="nb">}</span>     <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> 1<span class="nb">}</span>     <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> 3<span class="nb">}</span>          <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> 1<span class="nb">}</span> <span class="k">\\</span>
<span class="k">\end</span><span class="nb">{</span>tabular<span class="nb">}</span>
<span class="k">\caption</span><span class="nb">{</span>Comparison between different rounding modes for division and modulo cells.<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>tab:CellLib<span class="nb">_</span>divmod<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>table<span class="nb">}</span>

<span class="k">\subsection</span><span class="nb">{</span>Multiplexers<span class="nb">}</span>

Multiplexers are generated by the Verilog HDL frontend for <span class="nb">{</span><span class="k">\tt</span>
?:<span class="nb">}</span>-expressions. Multiplexers are also generated by the <span class="nb">{</span><span class="k">\tt</span> proc<span class="nb">}</span> pass to map the decision trees
from RTLIL::Process objects to logic.

The simplest multiplexer cell type is <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>mux<span class="nb">}</span>. Cells of this type have a <span class="k">\B</span><span class="nb">{</span>WIDTH<span class="nb">}</span> parameter
and data inputs <span class="k">\B</span><span class="nb">{</span>A<span class="nb">}</span> and <span class="k">\B</span><span class="nb">{</span>B<span class="nb">}</span> and a data output <span class="k">\B</span><span class="nb">{</span>Y<span class="nb">}</span>, all of the specified width. This cell also
has a single bit control input <span class="k">\B</span><span class="nb">{</span>S<span class="nb">}</span>. If <span class="k">\B</span><span class="nb">{</span>S<span class="nb">}</span> is 0 the value from the <span class="k">\B</span><span class="nb">{</span>A<span class="nb">}</span> input is sent to
the output, if it is 1 the value from the <span class="k">\B</span><span class="nb">{</span>B<span class="nb">}</span> input is sent to the output. So the <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>mux<span class="nb">}</span>
cell implements the function <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = S ? B : A;.

The <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>pmux<span class="nb">}</span> cell is used to multiplex between many inputs using a one-hot select signal. Cells
of this type have a <span class="k">\B</span><span class="nb">{</span>WIDTH<span class="nb">}</span> and a <span class="k">\B</span><span class="nb">{</span>S<span class="k">\_</span>WIDTH<span class="nb">}</span> parameter and inputs <span class="k">\B</span><span class="nb">{</span>A<span class="nb">}</span>, <span class="k">\B</span><span class="nb">{</span>B<span class="nb">}</span>, and <span class="k">\B</span><span class="nb">{</span>S<span class="nb">}</span> and
an output <span class="k">\B</span><span class="nb">{</span>Y<span class="nb">}</span>. The <span class="k">\B</span><span class="nb">{</span>S<span class="nb">}</span> input is <span class="k">\B</span><span class="nb">{</span>S<span class="k">\_</span>WIDTH<span class="nb">}</span> bits wide. The <span class="k">\B</span><span class="nb">{</span>A<span class="nb">}</span> input and the output are both
<span class="k">\B</span><span class="nb">{</span>WIDTH<span class="nb">}</span> bits wide and the <span class="k">\B</span><span class="nb">{</span>B<span class="nb">}</span> input is <span class="k">\B</span><span class="nb">{</span>WIDTH<span class="nb">}</span>*<span class="k">\B</span><span class="nb">{</span>S<span class="k">\_</span>WIDTH<span class="nb">}</span> bits wide. When all bits of
<span class="k">\B</span><span class="nb">{</span>S<span class="nb">}</span> are zero, the value from <span class="k">\B</span><span class="nb">{</span>A<span class="nb">}</span> input is sent to the output. If the <span class="s">$</span><span class="nb">n</span><span class="s">$</span>&#39;th bit from <span class="k">\B</span><span class="nb">{</span>S<span class="nb">}</span> is
set, the value <span class="s">$</span><span class="nb">n</span><span class="s">$</span>&#39;th <span class="k">\B</span><span class="nb">{</span>WIDTH<span class="nb">}</span> bits wide slice of the <span class="k">\B</span><span class="nb">{</span>B<span class="nb">}</span> input is sent to the output. When more
than one bit from <span class="k">\B</span><span class="nb">{</span>S<span class="nb">}</span> is set the output is undefined. Cells of this type are used to model
``parallel cases&#39;&#39; (defined by using the <span class="nb">{</span><span class="k">\tt</span> parallel<span class="k">\_</span>case<span class="nb">}</span> attribute or detected by
an optimization).

The <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>tribuf<span class="nb">}</span> cell is used to implement tristate logic. Cells of this type have a <span class="k">\B</span><span class="nb">{</span>WIDTH<span class="nb">}</span>
parameter and inputs <span class="k">\B</span><span class="nb">{</span>A<span class="nb">}</span> and <span class="k">\B</span><span class="nb">{</span>EN<span class="nb">}</span> and an output <span class="k">\B</span><span class="nb">{</span>Y<span class="nb">}</span>. The <span class="k">\B</span><span class="nb">{</span>A<span class="nb">}</span> input and <span class="k">\B</span><span class="nb">{</span>Y<span class="nb">}</span> output are
<span class="k">\B</span><span class="nb">{</span>WIDTH<span class="nb">}</span> bits wide, and the <span class="k">\B</span><span class="nb">{</span>EN<span class="nb">}</span> input is one bit wide. When <span class="k">\B</span><span class="nb">{</span>EN<span class="nb">}</span> is 0, the output <span class="k">\B</span><span class="nb">{</span>Y<span class="nb">}</span>
is not driven. When <span class="k">\B</span><span class="nb">{</span>EN<span class="nb">}</span> is 1, the value from <span class="k">\B</span><span class="nb">{</span>A<span class="nb">}</span> input is sent to the <span class="k">\B</span><span class="nb">{</span>Y<span class="nb">}</span> output. Therefore,
the <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>tribuf<span class="nb">}</span> cell implements the function <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = EN ? A : &#39;bz;.

Behavioural code with cascaded <span class="nb">{</span><span class="k">\tt</span> if-then-else<span class="nb">}</span>- and <span class="nb">{</span><span class="k">\tt</span> case<span class="nb">}</span>-statements
usually results in trees of multiplexer cells. Many passes (from various
optimizations to FSM extraction) heavily depend on these multiplexer trees to
understand dependencies between signals. Therefore optimizations should not
break these multiplexer trees (e.g.~by replacing a multiplexer between a
calculated signal and a constant zero with an <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>and<span class="nb">}</span> gate).

<span class="k">\subsection</span><span class="nb">{</span>Registers<span class="nb">}</span>

SR-type latches are represented by <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>sr<span class="nb">}</span> cells.  These cells have input ports
<span class="k">\B</span><span class="nb">{</span>SET<span class="nb">}</span> and <span class="k">\B</span><span class="nb">{</span>CLR<span class="nb">}</span> and an output port <span class="k">\B</span><span class="nb">{</span>Q<span class="nb">}</span>.  They have the following parameters:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>WIDTH<span class="nb">}</span> <span class="k">\\</span>
The width of inputs <span class="k">\B</span><span class="nb">{</span>SET<span class="nb">}</span> and <span class="k">\B</span><span class="nb">{</span>CLR<span class="nb">}</span> and output <span class="k">\B</span><span class="nb">{</span>Q<span class="nb">}</span>.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>SET<span class="k">\_</span>POLARITY<span class="nb">}</span> <span class="k">\\</span>
The set input bits are active-high if this parameter has the value <span class="nb">{</span><span class="k">\tt</span> 1&#39;b1<span class="nb">}</span> and active-low
if this parameter is <span class="nb">{</span><span class="k">\tt</span> 1&#39;b0<span class="nb">}</span>.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>CLR<span class="k">\_</span>POLARITY<span class="nb">}</span> <span class="k">\\</span>
The reset input bits are active-high if this parameter has the value <span class="nb">{</span><span class="k">\tt</span> 1&#39;b1<span class="nb">}</span> and active-low
if this parameter is <span class="nb">{</span><span class="k">\tt</span> 1&#39;b0<span class="nb">}</span>.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

Both set and reset inputs have separate bits for every output bit.
When both the set and reset inputs of an <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>sr<span class="nb">}</span> cell are active for a given bit
index, the reset input takes precedence.

D-type flip-flops are represented by <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>dff<span class="nb">}</span> cells. These cells have a clock port <span class="k">\B</span><span class="nb">{</span>CLK<span class="nb">}</span>,
an input port <span class="k">\B</span><span class="nb">{</span>D<span class="nb">}</span> and an output port <span class="k">\B</span><span class="nb">{</span>Q<span class="nb">}</span>. The following parameters are available for <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>dff<span class="nb">}</span>
cells:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>WIDTH<span class="nb">}</span> <span class="k">\\</span>
The width of input <span class="k">\B</span><span class="nb">{</span>D<span class="nb">}</span> and output <span class="k">\B</span><span class="nb">{</span>Q<span class="nb">}</span>.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>CLK<span class="k">\_</span>POLARITY<span class="nb">}</span> <span class="k">\\</span>
Clock is active on the positive edge if this parameter has the value <span class="nb">{</span><span class="k">\tt</span> 1&#39;b1<span class="nb">}</span> and on the negative
edge if this parameter is <span class="nb">{</span><span class="k">\tt</span> 1&#39;b0<span class="nb">}</span>.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

D-type flip-flops with asynchronous reset are represented by <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>adff<span class="nb">}</span> cells. As the <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>dff<span class="nb">}</span>
cells they have <span class="k">\B</span><span class="nb">{</span>CLK<span class="nb">}</span>, <span class="k">\B</span><span class="nb">{</span>D<span class="nb">}</span> and <span class="k">\B</span><span class="nb">{</span>Q<span class="nb">}</span> ports. In addition they also have a single-bit <span class="k">\B</span><span class="nb">{</span>ARST<span class="nb">}</span>
input port for the reset pin and the following additional two parameters:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>ARST<span class="k">\_</span>POLARITY<span class="nb">}</span> <span class="k">\\</span>
The asynchronous reset is active-high if this parameter has the value <span class="nb">{</span><span class="k">\tt</span> 1&#39;b1<span class="nb">}</span> and active-low
if this parameter is <span class="nb">{</span><span class="k">\tt</span> 1&#39;b0<span class="nb">}</span>.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>ARST<span class="k">\_</span>VALUE<span class="nb">}</span> <span class="k">\\</span>
The state of <span class="k">\B</span><span class="nb">{</span>Q<span class="nb">}</span> will be set to this value when the reset is active.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>sloppypar<span class="nb">}</span>
Usually these cells are generated by the <span class="nb">{</span><span class="k">\tt</span> proc<span class="nb">}</span> pass using the information
in the designs RTLIL::Process objects.
<span class="k">\end</span><span class="nb">{</span>sloppypar<span class="nb">}</span>

D-type flip-flops with synchronous reset are represented by <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>sdff<span class="nb">}</span> cells. As the <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>dff<span class="nb">}</span>
cells they have <span class="k">\B</span><span class="nb">{</span>CLK<span class="nb">}</span>, <span class="k">\B</span><span class="nb">{</span>D<span class="nb">}</span> and <span class="k">\B</span><span class="nb">{</span>Q<span class="nb">}</span> ports. In addition they also have a single-bit <span class="k">\B</span><span class="nb">{</span>SRST<span class="nb">}</span>
input port for the reset pin and the following additional two parameters:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>SRST<span class="k">\_</span>POLARITY<span class="nb">}</span> <span class="k">\\</span>
The synchronous reset is active-high if this parameter has the value <span class="nb">{</span><span class="k">\tt</span> 1&#39;b1<span class="nb">}</span> and active-low
if this parameter is <span class="nb">{</span><span class="k">\tt</span> 1&#39;b0<span class="nb">}</span>.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>SRST<span class="k">\_</span>VALUE<span class="nb">}</span> <span class="k">\\</span>
The state of <span class="k">\B</span><span class="nb">{</span>Q<span class="nb">}</span> will be set to this value when the reset is active.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

Note that the <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>adff<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>sdff<span class="nb">}</span> cells can only be used when the reset value is constant.

D-type flip-flops with asynchronous load are represented by <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>aldff<span class="nb">}</span> cells. As the <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>dff<span class="nb">}</span>
cells they have <span class="k">\B</span><span class="nb">{</span>CLK<span class="nb">}</span>, <span class="k">\B</span><span class="nb">{</span>D<span class="nb">}</span> and <span class="k">\B</span><span class="nb">{</span>Q<span class="nb">}</span> ports. In addition they also have a single-bit <span class="k">\B</span><span class="nb">{</span>ALOAD<span class="nb">}</span>
input port for the async load enable pin, a <span class="k">\B</span><span class="nb">{</span>AD<span class="nb">}</span> input port with the same width as data for
the async load data, and the following additional parameter:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>ALOAD<span class="k">\_</span>POLARITY<span class="nb">}</span> <span class="k">\\</span>
The asynchronous load is active-high if this parameter has the value <span class="nb">{</span><span class="k">\tt</span> 1&#39;b1<span class="nb">}</span> and active-low
if this parameter is <span class="nb">{</span><span class="k">\tt</span> 1&#39;b0<span class="nb">}</span>.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

D-type flip-flops with asynchronous set and reset are represented by <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>dffsr<span class="nb">}</span> cells.
As the <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>dff<span class="nb">}</span> cells they have <span class="k">\B</span><span class="nb">{</span>CLK<span class="nb">}</span>, <span class="k">\B</span><span class="nb">{</span>D<span class="nb">}</span> and <span class="k">\B</span><span class="nb">{</span>Q<span class="nb">}</span> ports. In addition they also have
multi-bit <span class="k">\B</span><span class="nb">{</span>SET<span class="nb">}</span> and <span class="k">\B</span><span class="nb">{</span>CLR<span class="nb">}</span> input ports and the corresponding polarity parameters, like 
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>sr<span class="nb">}</span> cells.

D-type flip-flops with enable are represented by <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>dffe<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>adffe<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>aldffe<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>dffsre<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>sdffe<span class="nb">}</span>, and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>sdffce<span class="nb">}</span> cells, which are enhanced variants of <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>dff<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>adff<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>aldff<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>dffsr<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>sdff<span class="nb">}</span> (with reset over enable) and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>sdff<span class="nb">}</span> (with enable over reset)
cells, respectively.  They have the same ports and parameters as their base cell.
In addition they also have a single-bit <span class="k">\B</span><span class="nb">{</span>EN<span class="nb">}</span> input port for the enable pin and the following parameter:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>EN<span class="k">\_</span>POLARITY<span class="nb">}</span> <span class="k">\\</span>
The enable input is active-high if this parameter has the value <span class="nb">{</span><span class="k">\tt</span> 1&#39;b1<span class="nb">}</span> and active-low
if this parameter is <span class="nb">{</span><span class="k">\tt</span> 1&#39;b0<span class="nb">}</span>.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

D-type latches are represented by <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>dlatch<span class="nb">}</span> cells.  These cells have an enable port <span class="k">\B</span><span class="nb">{</span>EN<span class="nb">}</span>,
an input port <span class="k">\B</span><span class="nb">{</span>D<span class="nb">}</span>, and an output port <span class="k">\B</span><span class="nb">{</span>Q<span class="nb">}</span>.  The following parameters are available for <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>dlatch<span class="nb">}</span> cells:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>WIDTH<span class="nb">}</span> <span class="k">\\</span>
The width of input <span class="k">\B</span><span class="nb">{</span>D<span class="nb">}</span> and output <span class="k">\B</span><span class="nb">{</span>Q<span class="nb">}</span>.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>EN<span class="k">\_</span>POLARITY<span class="nb">}</span> <span class="k">\\</span>
The enable input is active-high if this parameter has the value <span class="nb">{</span><span class="k">\tt</span> 1&#39;b1<span class="nb">}</span> and active-low
if this parameter is <span class="nb">{</span><span class="k">\tt</span> 1&#39;b0<span class="nb">}</span>.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

The latch is transparent when the <span class="k">\B</span><span class="nb">{</span>EN<span class="nb">}</span> input is active.

D-type latches with reset are represented by <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>adlatch<span class="nb">}</span> cells.  In addition to <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>dlatch<span class="nb">}</span>
ports and parameters, they also have a single-bit <span class="k">\B</span><span class="nb">{</span>ARST<span class="nb">}</span> input port for the reset pin and the following additional parameters:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>ARST<span class="k">\_</span>POLARITY<span class="nb">}</span> <span class="k">\\</span>
The asynchronous reset is active-high if this parameter has the value <span class="nb">{</span><span class="k">\tt</span> 1&#39;b1<span class="nb">}</span> and active-low
if this parameter is <span class="nb">{</span><span class="k">\tt</span> 1&#39;b0<span class="nb">}</span>.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>ARST<span class="k">\_</span>VALUE<span class="nb">}</span> <span class="k">\\</span>
The state of <span class="k">\B</span><span class="nb">{</span>Q<span class="nb">}</span> will be set to this value when the reset is active.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

D-type latches with set and reset are represented by <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>dlatchsr<span class="nb">}</span> cells.
In addition to <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>dlatch<span class="nb">}</span> ports and parameters, they also have multi-bit
<span class="k">\B</span><span class="nb">{</span>SET<span class="nb">}</span> and <span class="k">\B</span><span class="nb">{</span>CLR<span class="nb">}</span> input ports and the corresponding polarity parameters, like
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>sr<span class="nb">}</span> cells.

<span class="k">\subsection</span><span class="nb">{</span>Memories<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>sec:memcells<span class="nb">}</span>

Memories are either represented using RTLIL::Memory objects, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>memrd<span class="k">\_</span>v2<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>memwr<span class="k">\_</span>v2<span class="nb">}</span>, and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>meminit<span class="k">\_</span>v2<span class="nb">}</span>
cells, or by <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>mem<span class="k">\_</span>v2<span class="nb">}</span> cells alone.

In the first alternative the RTLIL::Memory objects hold the general metadata for the memory (bit width,
size in number of words, etc.) and for each port a <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>memrd<span class="k">\_</span>v2<span class="nb">}</span> (read port) or <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>memwr<span class="k">\_</span>v2<span class="nb">}</span> (write port)
cell is created. Having individual cells for read and write ports has the advantage that they can be
consolidated using resource sharing passes. In some cases this drastically reduces the number of required
ports on the memory cell. In this alternative, memory initialization data is represented by <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>meminit<span class="k">\_</span>v2<span class="nb">}</span> cells,
which allow delaying constant folding for initialization addresses and data until after the frontend finishes.

The <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>memrd<span class="k">\_</span>v2<span class="nb">}</span> cells have a clock input <span class="k">\B</span><span class="nb">{</span>CLK<span class="nb">}</span>, an enable input <span class="k">\B</span><span class="nb">{</span>EN<span class="nb">}</span>, an
address input <span class="k">\B</span><span class="nb">{</span>ADDR<span class="nb">}</span>, a data output <span class="k">\B</span><span class="nb">{</span>DATA<span class="nb">}</span>, an asynchronous reset input <span class="k">\B</span><span class="nb">{</span>ARST<span class="nb">}</span>,
and a synchronous reset input <span class="k">\B</span><span class="nb">{</span>SRST<span class="nb">}</span>. They also have the following parameters:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>MEMID<span class="nb">}</span> <span class="k">\\</span>
The name of the RTLIL::Memory object that is associated with this read port.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>ABITS<span class="nb">}</span> <span class="k">\\</span>
The number of address bits (width of the <span class="k">\B</span><span class="nb">{</span>ADDR<span class="nb">}</span> input port).

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>WIDTH<span class="nb">}</span> <span class="k">\\</span>
The number of data bits (width of the <span class="k">\B</span><span class="nb">{</span>DATA<span class="nb">}</span> output port).  Note that this may be a power-of-two
multiple of the underlying memory&#39;s width -- such ports are called wide ports and access an aligned
group of cells at once.  In this case, the corresponding low bits of <span class="k">\B</span><span class="nb">{</span>ADDR<span class="nb">}</span> must be tied to 0.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>CLK<span class="k">\_</span>ENABLE<span class="nb">}</span> <span class="k">\\</span>
When this parameter is non-zero, the clock is used. Otherwise this read port is asynchronous and
the <span class="k">\B</span><span class="nb">{</span>CLK<span class="nb">}</span> input is not used.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>CLK<span class="k">\_</span>POLARITY<span class="nb">}</span> <span class="k">\\</span>
Clock is active on the positive edge if this parameter has the value <span class="nb">{</span><span class="k">\tt</span> 1&#39;b1<span class="nb">}</span> and on the negative
edge if this parameter is <span class="nb">{</span><span class="k">\tt</span> 1&#39;b0<span class="nb">}</span>.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>TRANSPARENCY<span class="k">\_</span>MASK<span class="nb">}</span> <span class="k">\\</span>
This parameter is a bitmask of write ports that this read port is transparent with.  The bits
of this parameter are indexed by the write port&#39;s <span class="k">\B</span><span class="nb">{</span>PORTID<span class="nb">}</span> parameter.  Transparency can only be
enabled between synchronous ports sharing a clock domain.  When transparency is enabled for a given
port pair, a read and write to the same address in the same cycle will return the new value.
Otherwise the old value is returned.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>COLLISION<span class="k">\_</span>X<span class="k">\_</span>MASK<span class="nb">}</span> <span class="k">\\</span>
This parameter is a bitmask of write ports that have undefined collision behavior with this port.
The bits of this parameter are indexed by the write port&#39;s <span class="k">\B</span><span class="nb">{</span>PORTID<span class="nb">}</span> parameter.  This behavior can only be
enabled between synchronous ports sharing a clock domain.  When undefined collision is enabled for a given
port pair, a read and write to the same address in the same cycle will return the undefined (all-X) value.
This option is exclusive (for a given port pair) with the transparency option.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>ARST<span class="k">\_</span>VALUE<span class="nb">}</span> <span class="k">\\</span>
Whenever the <span class="k">\B</span><span class="nb">{</span>ARST<span class="nb">}</span> input is asserted, the data output will be reset to this value.
Only used for synchronous ports.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>SRST<span class="k">\_</span>VALUE<span class="nb">}</span> <span class="k">\\</span>
Whenever the <span class="k">\B</span><span class="nb">{</span>SRST<span class="nb">}</span> input is synchronously asserted, the data output will be reset to this value.
Only used for synchronous ports.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>INIT<span class="k">\_</span>VALUE<span class="nb">}</span> <span class="k">\\</span>
The initial value of the data output, for synchronous ports.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>CE<span class="k">\_</span>OVER<span class="k">\_</span>SRST<span class="nb">}</span> <span class="k">\\</span>
If this parameter is non-zero, the <span class="k">\B</span><span class="nb">{</span>SRST<span class="nb">}</span> input is only recognized when <span class="k">\B</span><span class="nb">{</span>EN<span class="nb">}</span> is true.
Otherwise, <span class="k">\B</span><span class="nb">{</span>SRST<span class="nb">}</span> is recognized regardless of <span class="k">\B</span><span class="nb">{</span>EN<span class="nb">}</span>.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

The <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>memwr<span class="k">\_</span>v2<span class="nb">}</span> cells have a clock input <span class="k">\B</span><span class="nb">{</span>CLK<span class="nb">}</span>, an enable input <span class="k">\B</span><span class="nb">{</span>EN<span class="nb">}</span> (one
enable bit for each data bit), an address input <span class="k">\B</span><span class="nb">{</span>ADDR<span class="nb">}</span> and a data input
<span class="k">\B</span><span class="nb">{</span>DATA<span class="nb">}</span>. They also have the following parameters:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>MEMID<span class="nb">}</span> <span class="k">\\</span>
The name of the RTLIL::Memory object that is associated with this write port.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>ABITS<span class="nb">}</span> <span class="k">\\</span>
The number of address bits (width of the <span class="k">\B</span><span class="nb">{</span>ADDR<span class="nb">}</span> input port).

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>WIDTH<span class="nb">}</span> <span class="k">\\</span>
The number of data bits (width of the <span class="k">\B</span><span class="nb">{</span>DATA<span class="nb">}</span> output port). Like with <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>memrd<span class="k">\_</span>v2<span class="nb">}</span> cells,
the width is allowed to be any power-of-two multiple of memory width, with the corresponding
restriction on address.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>CLK<span class="k">\_</span>ENABLE<span class="nb">}</span> <span class="k">\\</span>
When this parameter is non-zero, the clock is used. Otherwise this write port is asynchronous and
the <span class="k">\B</span><span class="nb">{</span>CLK<span class="nb">}</span> input is not used.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>CLK<span class="k">\_</span>POLARITY<span class="nb">}</span> <span class="k">\\</span>
Clock is active on positive edge if this parameter has the value <span class="nb">{</span><span class="k">\tt</span> 1&#39;b1<span class="nb">}</span> and on the negative
edge if this parameter is <span class="nb">{</span><span class="k">\tt</span> 1&#39;b0<span class="nb">}</span>.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>PORTID<span class="nb">}</span> <span class="k">\\</span>
An identifier for this write port, used to index write port bit mask parameters.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>PRIORITY<span class="k">\_</span>MASK<span class="nb">}</span> <span class="k">\\</span>
This parameter is a bitmask of write ports that this write port has priority over in case of writing
to the same address.  The bits of this parameter are indexed by the other write port&#39;s <span class="k">\B</span><span class="nb">{</span>PORTID<span class="nb">}</span> parameter.
Write ports can only have priority over write ports with lower port ID.  When two ports write to the same
address and neither has priority over the other, the result is undefined.  Priority can only be set between
two synchronous ports sharing the same clock domain.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

The <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>meminit<span class="k">\_</span>v2<span class="nb">}</span> cells have an address input <span class="k">\B</span><span class="nb">{</span>ADDR<span class="nb">}</span>, a data input <span class="k">\B</span><span class="nb">{</span>DATA<span class="nb">}</span>, with the width
of the <span class="k">\B</span><span class="nb">{</span>DATA<span class="nb">}</span> port equal to <span class="k">\B</span><span class="nb">{</span>WIDTH<span class="nb">}</span> parameter times <span class="k">\B</span><span class="nb">{</span>WORDS<span class="nb">}</span> parameter, and a bit enable mask input
<span class="k">\B</span><span class="nb">{</span>EN<span class="nb">}</span> with width equal to <span class="k">\B</span><span class="nb">{</span>WIDTH<span class="nb">}</span> parameter. All three of the inputs
must resolve to a constant for synthesis to succeed.

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>MEMID<span class="nb">}</span> <span class="k">\\</span>
The name of the RTLIL::Memory object that is associated with this initialization cell.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>ABITS<span class="nb">}</span> <span class="k">\\</span>
The number of address bits (width of the <span class="k">\B</span><span class="nb">{</span>ADDR<span class="nb">}</span> input port).

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>WIDTH<span class="nb">}</span> <span class="k">\\</span>
The number of data bits per memory location.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>WORDS<span class="nb">}</span> <span class="k">\\</span>
The number of consecutive memory locations initialized by this cell.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>PRIORITY<span class="nb">}</span> <span class="k">\\</span>
The cell with the higher integer value in this parameter wins an initialization conflict.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

The HDL frontend models a memory using RTLIL::Memory objects and asynchronous
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>memrd<span class="k">\_</span>v2<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>memwr<span class="k">\_</span>v2<span class="nb">}</span> cells. The <span class="nb">{</span><span class="k">\tt</span> memory<span class="nb">}</span> pass (i.e.~its various sub-passes) migrates
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>dff<span class="nb">}</span> cells into the <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>memrd<span class="k">\_</span>v2<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>memwr<span class="k">\_</span>v2<span class="nb">}</span> cells making them synchronous, then
converts them to a single <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>mem<span class="k">\_</span>v2<span class="nb">}</span> cell and (optionally) maps this cell type
to <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>dff<span class="nb">}</span> cells for the individual words and multiplexer-based address decoders for the read and
write interfaces. When the last step is disabled or not possible, a <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>mem<span class="k">\_</span>v2<span class="nb">}</span> cell is left in the design.

The <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>mem<span class="k">\_</span>v2<span class="nb">}</span> cell provides the following parameters:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>MEMID<span class="nb">}</span> <span class="k">\\</span>
The name of the original RTLIL::Memory object that became this <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>mem<span class="k">\_</span>v2<span class="nb">}</span> cell.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>SIZE<span class="nb">}</span> <span class="k">\\</span>
The number of words in the memory.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>ABITS<span class="nb">}</span> <span class="k">\\</span>
The number of address bits.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>WIDTH<span class="nb">}</span> <span class="k">\\</span>
The number of data bits per word.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>INIT<span class="nb">}</span> <span class="k">\\</span>
The initial memory contents.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>PORTS<span class="nb">}</span> <span class="k">\\</span>
The number of read ports on this memory cell.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>WIDE<span class="k">\_</span>CONTINUATION<span class="nb">}</span> <span class="k">\\</span>
This parameter is <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>PORTS<span class="nb">}</span> bits wide, containing a bitmask of ``wide continuation&#39;&#39; read ports.
Such ports are used to represent the extra data bits of wide ports in the combined cell, and must
have all control signals identical with the preceding port, except for address, which must have
the proper sub-cell address encoded in the low bits.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>CLK<span class="k">\_</span>ENABLE<span class="nb">}</span> <span class="k">\\</span>
This parameter is <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>PORTS<span class="nb">}</span> bits wide, containing a clock enable bit for each read port.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>CLK<span class="k">\_</span>POLARITY<span class="nb">}</span> <span class="k">\\</span>
This parameter is <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>PORTS<span class="nb">}</span> bits wide, containing a clock polarity bit for each read port.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>TRANSPARENCY<span class="k">\_</span>MASK<span class="nb">}</span> <span class="k">\\</span>
This parameter is <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>PORTS*WR<span class="k">\_</span>PORTS<span class="nb">}</span> bits wide, containing a concatenation of all
<span class="k">\B</span><span class="nb">{</span>TRANSPARENCY<span class="k">\_</span>MASK<span class="nb">}</span> values of the original <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>memrd<span class="k">\_</span>v2<span class="nb">}</span> cells.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>COLLISION<span class="k">\_</span>X<span class="k">\_</span>MASK<span class="nb">}</span> <span class="k">\\</span>
This parameter is <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>PORTS*WR<span class="k">\_</span>PORTS<span class="nb">}</span> bits wide, containing a concatenation of all
<span class="k">\B</span><span class="nb">{</span>COLLISION<span class="k">\_</span>X<span class="k">\_</span>MASK<span class="nb">}</span> values of the original <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>memrd<span class="k">\_</span>v2<span class="nb">}</span> cells.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>CE<span class="k">\_</span>OVER<span class="k">\_</span>SRST<span class="nb">}</span> <span class="k">\\</span>
This parameter is <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>PORTS<span class="nb">}</span> bits wide, determining relative synchronous reset and enable priority for each read port.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>INIT<span class="k">\_</span>VALUE<span class="nb">}</span> <span class="k">\\</span>
This parameter is <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>PORTS*WIDTH<span class="nb">}</span> bits wide, containing the initial value for each synchronous read port.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>ARST<span class="k">\_</span>VALUE<span class="nb">}</span> <span class="k">\\</span>
This parameter is <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>PORTS*WIDTH<span class="nb">}</span> bits wide, containing the asynchronous reset value for each synchronous read port.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>SRST<span class="k">\_</span>VALUE<span class="nb">}</span> <span class="k">\\</span>
This parameter is <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>PORTS*WIDTH<span class="nb">}</span> bits wide, containing the synchronous reset value for each synchronous read port.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>WR<span class="k">\_</span>PORTS<span class="nb">}</span> <span class="k">\\</span>
The number of write ports on this memory cell.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>WR<span class="k">\_</span>WIDE<span class="k">\_</span>CONTINUATION<span class="nb">}</span> <span class="k">\\</span>
This parameter is <span class="k">\B</span><span class="nb">{</span>WR<span class="k">\_</span>PORTS<span class="nb">}</span> bits wide, containing a bitmask of ``wide continuation&#39;&#39; write ports.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>WR<span class="k">\_</span>CLK<span class="k">\_</span>ENABLE<span class="nb">}</span> <span class="k">\\</span>
This parameter is <span class="k">\B</span><span class="nb">{</span>WR<span class="k">\_</span>PORTS<span class="nb">}</span> bits wide, containing a clock enable bit for each write port.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>WR<span class="k">\_</span>CLK<span class="k">\_</span>POLARITY<span class="nb">}</span> <span class="k">\\</span>
This parameter is <span class="k">\B</span><span class="nb">{</span>WR<span class="k">\_</span>PORTS<span class="nb">}</span> bits wide, containing a clock polarity bit for each write port.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>WR<span class="k">\_</span>PRIORITY<span class="k">\_</span>MASK<span class="nb">}</span> <span class="k">\\</span>
This parameter is <span class="k">\B</span><span class="nb">{</span>WR<span class="k">\_</span>PORTS*WR<span class="k">\_</span>PORTS<span class="nb">}</span> bits wide, containing a concatenation of all
<span class="k">\B</span><span class="nb">{</span>PRIORITY<span class="k">\_</span>MASK<span class="nb">}</span> values of the original <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>memwr<span class="k">\_</span>v2<span class="nb">}</span> cells.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

The <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>mem<span class="k">\_</span>v2<span class="nb">}</span> cell has the following ports:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>CLK<span class="nb">}</span> <span class="k">\\</span>
This input is <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>PORTS<span class="nb">}</span> bits wide, containing all clock signals for the read ports.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>EN<span class="nb">}</span> <span class="k">\\</span>
This input is <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>PORTS<span class="nb">}</span> bits wide, containing all enable signals for the read ports.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>ADDR<span class="nb">}</span> <span class="k">\\</span>
This input is <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>PORTS<span class="nb">}</span>*<span class="k">\B</span><span class="nb">{</span>ABITS<span class="nb">}</span> bits wide, containing all address signals for the read ports.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>DATA<span class="nb">}</span> <span class="k">\\</span>
This input is <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>PORTS<span class="nb">}</span>*<span class="k">\B</span><span class="nb">{</span>WIDTH<span class="nb">}</span> bits wide, containing all data signals for the read ports.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>ARST<span class="nb">}</span> <span class="k">\\</span>
This input is <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>PORTS<span class="nb">}</span> bits wide, containing all asynchronous reset signals for the read ports.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>SRST<span class="nb">}</span> <span class="k">\\</span>
This input is <span class="k">\B</span><span class="nb">{</span>RD<span class="k">\_</span>PORTS<span class="nb">}</span> bits wide, containing all synchronous reset signals for the read ports.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>WR<span class="k">\_</span>CLK<span class="nb">}</span> <span class="k">\\</span>
This input is <span class="k">\B</span><span class="nb">{</span>WR<span class="k">\_</span>PORTS<span class="nb">}</span> bits wide, containing all clock signals for the write ports.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>WR<span class="k">\_</span>EN<span class="nb">}</span> <span class="k">\\</span>
This input is <span class="k">\B</span><span class="nb">{</span>WR<span class="k">\_</span>PORTS<span class="nb">}</span>*<span class="k">\B</span><span class="nb">{</span>WIDTH<span class="nb">}</span> bits wide, containing all enable signals for the write ports.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>WR<span class="k">\_</span>ADDR<span class="nb">}</span> <span class="k">\\</span>
This input is <span class="k">\B</span><span class="nb">{</span>WR<span class="k">\_</span>PORTS<span class="nb">}</span>*<span class="k">\B</span><span class="nb">{</span>ABITS<span class="nb">}</span> bits wide, containing all address signals for the write ports.

<span class="k">\item</span> <span class="k">\B</span><span class="nb">{</span>WR<span class="k">\_</span>DATA<span class="nb">}</span> <span class="k">\\</span>
This input is <span class="k">\B</span><span class="nb">{</span>WR<span class="k">\_</span>PORTS<span class="nb">}</span>*<span class="k">\B</span><span class="nb">{</span>WIDTH<span class="nb">}</span> bits wide, containing all data signals for the write ports.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

The <span class="nb">{</span><span class="k">\tt</span> memory<span class="k">\_</span>collect<span class="nb">}</span> pass can be used to convert discrete <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>memrd<span class="k">\_</span>v2<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>memwr<span class="k">\_</span>v2<span class="nb">}</span>, and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>meminit<span class="k">\_</span>v2<span class="nb">}</span> cells
belonging to the same memory to a single <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>mem<span class="k">\_</span>v2<span class="nb">}</span> cell, whereas the <span class="nb">{</span><span class="k">\tt</span> memory<span class="k">\_</span>unpack<span class="nb">}</span> pass performs the inverse operation.
The <span class="nb">{</span><span class="k">\tt</span> memory<span class="k">\_</span>dff<span class="nb">}</span> pass can combine asynchronous memory ports that are fed by or feeding registers into synchronous memory ports.
The <span class="nb">{</span><span class="k">\tt</span> memory<span class="k">\_</span>bram<span class="nb">}</span> pass can be used to recognize <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>mem<span class="k">\_</span>v2<span class="nb">}</span> cells that can be implemented with a block RAM resource on an FPGA.
The <span class="nb">{</span><span class="k">\tt</span> memory<span class="k">\_</span>map<span class="nb">}</span> pass can be used to implement <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>mem<span class="k">\_</span>v2<span class="nb">}</span> cells as basic logic: word-wide DFFs and address decoders.

<span class="k">\subsection</span><span class="nb">{</span>Finite State Machines<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>fixme<span class="nb">}</span>
Add a brief description of the <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>fsm<span class="nb">}</span> cell type.
<span class="k">\end</span><span class="nb">{</span>fixme<span class="nb">}</span>

<span class="k">\subsection</span><span class="nb">{</span>Specify rules<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>fixme<span class="nb">}</span>
Add information about <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>specify2<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>specify3<span class="nb">}</span>, and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>specrule<span class="nb">}</span> cells.
<span class="k">\end</span><span class="nb">{</span>fixme<span class="nb">}</span>

<span class="k">\subsection</span><span class="nb">{</span>Formal verification cells<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>fixme<span class="nb">}</span>
Add information about <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>assert<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>assume<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>live<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>fair<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>cover<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>equiv<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>initstate<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>anyconst<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>anyseq<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>allconst<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>allseq<span class="nb">}</span> cells.
<span class="k">\end</span><span class="nb">{</span>fixme<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>fixme<span class="nb">}</span>
Add information about <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$</span>ff<span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>FF<span class="k">\_</span><span class="nb">}</span> cells.
<span class="k">\end</span><span class="nb">{</span>fixme<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>Gates<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>sec:celllib<span class="nb">_</span>gates<span class="nb">}</span>

For gate level logic networks, fixed function single bit cells are used that do
not provide any parameters.

Simulation models for these cells can be found in the file <span class="nb">{</span><span class="k">\tt</span> techlibs/common/simcells.v<span class="nb">}</span> in the Yosys
source tree.

<span class="k">\begin</span><span class="nb">{</span>table<span class="nb">}</span>[t]
<span class="k">\hfil</span>
<span class="k">\begin</span><span class="nb">{</span>tabular<span class="nb">}</span>[t]<span class="nb">{</span>ll<span class="nb">}</span>
Verilog <span class="nb">&amp;</span> Cell Type <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A;     <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>BUF<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = ~A;    <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>NOT<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A <span class="nb">&amp;</span> B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>AND<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = ~(A <span class="nb">&amp;</span> B); <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>NAND<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A <span class="nb">&amp;</span> ~B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>ANDNOT<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A | B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>OR<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = ~(A | B); <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>NOR<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A | ~B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>ORNOT<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = A <span class="nb">^</span> B; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>XOR<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = ~(A <span class="nb">^</span> B); <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>XNOR<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = ~((A <span class="nb">&amp;</span> B) | C); <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>AOI3<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = ~((A | B) <span class="nb">&amp;</span> C); <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>OAI3<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = ~((A <span class="nb">&amp;</span> B) | (C <span class="nb">&amp;</span> D)); <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>AOI4<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = ~((A | B) <span class="nb">&amp;</span> (C | D)); <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>OAI4<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = S ? B : A; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>MUX<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = ~(S ? B : A); <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>NMUX<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
(see below) <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>MUX4<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
(see below) <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>MUX8<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
(see below) <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>MUX16<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; Y = EN ? A : 1&#39;bz; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>TBUF<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; always @(negedge C) Q &lt;= D; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>N<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; always @(posedge C) Q &lt;= D; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>P<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; always @* if (!E) Q &lt;= D; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DLATCH<span class="k">\_</span>N<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>; always @* if (E)  Q &lt;= D; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DLATCH<span class="k">\_</span>P<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\end</span><span class="nb">{</span>tabular<span class="nb">}</span>
<span class="k">\caption</span><span class="nb">{</span>Cell types for gate level logic networks (main list)<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>tab:CellLib<span class="nb">_</span>gates<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>table<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>table<span class="nb">}</span>[t]
<span class="k">\hfil</span>
<span class="k">\begin</span><span class="nb">{</span>tabular<span class="nb">}</span>[t]<span class="nb">{</span>llll<span class="nb">}</span>
<span class="s">$</span><span class="nb">ClkEdge</span><span class="s">$</span> <span class="nb">&amp;</span> <span class="s">$</span><span class="nb">RstLvl</span><span class="s">$</span> <span class="nb">&amp;</span> <span class="s">$</span><span class="nb">RstVal</span><span class="s">$</span> <span class="nb">&amp;</span> Cell Type <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;negedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>NN0<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFF<span class="k">\_</span>NN0<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;negedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>NN1<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFF<span class="k">\_</span>NN1<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;negedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>NP0<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFF<span class="k">\_</span>NP0<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;negedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>NP1<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFF<span class="k">\_</span>NP1<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;posedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>PN0<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFF<span class="k">\_</span>PN0<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;posedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>PN1<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFF<span class="k">\_</span>PN1<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;posedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>PP0<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFF<span class="k">\_</span>PP0<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;posedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFF<span class="k">\_</span>PP1<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFF<span class="k">\_</span>PP1<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\end</span><span class="nb">{</span>tabular<span class="nb">}</span>
<span class="k">\caption</span><span class="nb">{</span>Cell types for gate level logic networks (FFs with reset)<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>tab:CellLib<span class="nb">_</span>gates<span class="nb">_</span>adff<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>table<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>table<span class="nb">}</span>[t]
<span class="k">\hfil</span>
<span class="k">\begin</span><span class="nb">{</span>tabular<span class="nb">}</span>[t]<span class="nb">{</span>lll<span class="nb">}</span>
<span class="s">$</span><span class="nb">ClkEdge</span><span class="s">$</span> <span class="nb">&amp;</span> <span class="s">$</span><span class="nb">EnLvl</span><span class="s">$</span> <span class="nb">&amp;</span> Cell Type <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;negedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFE<span class="k">\_</span>NN<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;negedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFE<span class="k">\_</span>NP<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;posedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFE<span class="k">\_</span>PN<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;posedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFE<span class="k">\_</span>PP<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\end</span><span class="nb">{</span>tabular<span class="nb">}</span>
<span class="k">\caption</span><span class="nb">{</span>Cell types for gate level logic networks (FFs with enable)<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>tab:CellLib<span class="nb">_</span>gates<span class="nb">_</span>dffe<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>table<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>table<span class="nb">}</span>[t]
<span class="k">\begin</span><span class="nb">{</span>tabular<span class="nb">}</span>[t]<span class="nb">{</span>lllll<span class="nb">}</span>
<span class="s">$</span><span class="nb">ClkEdge</span><span class="s">$</span> <span class="nb">&amp;</span> <span class="s">$</span><span class="nb">RstLvl</span><span class="s">$</span> <span class="nb">&amp;</span> <span class="s">$</span><span class="nb">RstVal</span><span class="s">$</span> <span class="nb">&amp;</span> <span class="s">$</span><span class="nb">EnLvl</span><span class="s">$</span> <span class="nb">&amp;</span> Cell Type <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;negedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFE<span class="k">\_</span>NN0N<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFFE<span class="k">\_</span>NN0N<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFFCE<span class="k">\_</span>NN0N<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;negedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFE<span class="k">\_</span>NN0P<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFFE<span class="k">\_</span>NN0P<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFFCE<span class="k">\_</span>NN0P<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;negedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFE<span class="k">\_</span>NN1N<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFFE<span class="k">\_</span>NN1N<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFFCE<span class="k">\_</span>NN1N<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;negedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFE<span class="k">\_</span>NN1P<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFFE<span class="k">\_</span>NN1P<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFFCE<span class="k">\_</span>NN1P<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;negedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFE<span class="k">\_</span>NP0N<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFFE<span class="k">\_</span>NP0N<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFFCE<span class="k">\_</span>NP0N<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;negedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFE<span class="k">\_</span>NP0P<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFFE<span class="k">\_</span>NP0P<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFFCE<span class="k">\_</span>NP0P<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;negedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFE<span class="k">\_</span>NP1N<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFFE<span class="k">\_</span>NP1N<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFFCE<span class="k">\_</span>NP1N<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;negedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFE<span class="k">\_</span>NP1P<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFFE<span class="k">\_</span>NP1P<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFFCE<span class="k">\_</span>NP1P<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;posedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFE<span class="k">\_</span>PN0N<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFFE<span class="k">\_</span>PN0N<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFFCE<span class="k">\_</span>PN0N<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;posedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFE<span class="k">\_</span>PN0P<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFFE<span class="k">\_</span>PN0P<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFFCE<span class="k">\_</span>PN0P<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;posedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFE<span class="k">\_</span>PN1N<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFFE<span class="k">\_</span>PN1N<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFFCE<span class="k">\_</span>PN1N<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;posedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFE<span class="k">\_</span>PN1P<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFFE<span class="k">\_</span>PN1P<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFFCE<span class="k">\_</span>PN1P<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;posedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFE<span class="k">\_</span>PP0N<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFFE<span class="k">\_</span>PP0N<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFFCE<span class="k">\_</span>PP0N<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;posedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFE<span class="k">\_</span>PP0P<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFFE<span class="k">\_</span>PP0P<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFFCE<span class="k">\_</span>PP0P<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;posedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFE<span class="k">\_</span>PP1N<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFFE<span class="k">\_</span>PP1N<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFFCE<span class="k">\_</span>PP1N<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;posedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFE<span class="k">\_</span>PP1P<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFFE<span class="k">\_</span>PP1P<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SDFFCE<span class="k">\_</span>PP1P<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\end</span><span class="nb">{</span>tabular<span class="nb">}</span>
<span class="k">\caption</span><span class="nb">{</span>Cell types for gate level logic networks (FFs with reset and enable)<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>tab:CellLib<span class="nb">_</span>gates<span class="nb">_</span>adffe<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>table<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>table<span class="nb">}</span>[t]
<span class="k">\hfil</span>
<span class="k">\begin</span><span class="nb">{</span>tabular<span class="nb">}</span>[t]<span class="nb">{</span>llll<span class="nb">}</span>
<span class="s">$</span><span class="nb">ClkEdge</span><span class="s">$</span> <span class="nb">&amp;</span> <span class="s">$</span><span class="nb">SetLvl</span><span class="s">$</span> <span class="nb">&amp;</span> <span class="s">$</span><span class="nb">RstLvl</span><span class="s">$</span> <span class="nb">&amp;</span> Cell Type <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;negedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFSR<span class="k">\_</span>NNN<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;negedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFSR<span class="k">\_</span>NNP<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;negedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFSR<span class="k">\_</span>NPN<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;negedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFSR<span class="k">\_</span>NPP<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;posedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFSR<span class="k">\_</span>PNN<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;posedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFSR<span class="k">\_</span>PNP<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;posedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFSR<span class="k">\_</span>PPN<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;posedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFSR<span class="k">\_</span>PPP<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\end</span><span class="nb">{</span>tabular<span class="nb">}</span>
<span class="k">\caption</span><span class="nb">{</span>Cell types for gate level logic networks (FFs with set and reset)<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>tab:CellLib<span class="nb">_</span>gates<span class="nb">_</span>dffsr<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>table<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>table<span class="nb">}</span>[t]
<span class="k">\hfil</span>
<span class="k">\begin</span><span class="nb">{</span>tabular<span class="nb">}</span>[t]<span class="nb">{</span>lllll<span class="nb">}</span>
<span class="s">$</span><span class="nb">ClkEdge</span><span class="s">$</span> <span class="nb">&amp;</span> <span class="s">$</span><span class="nb">SetLvl</span><span class="s">$</span> <span class="nb">&amp;</span> <span class="s">$</span><span class="nb">RstLvl</span><span class="s">$</span> <span class="nb">&amp;</span> <span class="s">$</span><span class="nb">EnLvl</span><span class="s">$</span> <span class="nb">&amp;</span> Cell Type <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;negedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFSRE<span class="k">\_</span>NNNN<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;negedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFSRE<span class="k">\_</span>NNNP<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;negedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFSRE<span class="k">\_</span>NNPN<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;negedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFSRE<span class="k">\_</span>NNPP<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;negedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFSRE<span class="k">\_</span>NPNN<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;negedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFSRE<span class="k">\_</span>NPNP<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;negedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFSRE<span class="k">\_</span>NPPN<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;negedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFSRE<span class="k">\_</span>NPPP<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;posedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFSRE<span class="k">\_</span>PNNN<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;posedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFSRE<span class="k">\_</span>PNNP<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;posedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFSRE<span class="k">\_</span>PNPN<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;posedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFSRE<span class="k">\_</span>PNPP<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;posedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFSRE<span class="k">\_</span>PPNN<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;posedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFSRE<span class="k">\_</span>PPNP<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;posedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFSRE<span class="k">\_</span>PPPN<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;posedge; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DFFSRE<span class="k">\_</span>PPPP<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\end</span><span class="nb">{</span>tabular<span class="nb">}</span>
<span class="k">\caption</span><span class="nb">{</span>Cell types for gate level logic networks (FFs with set and reset and enable)<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>tab:CellLib<span class="nb">_</span>gates<span class="nb">_</span>dffsre<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>table<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>table<span class="nb">}</span>[t]
<span class="k">\hfil</span>
<span class="k">\begin</span><span class="nb">{</span>tabular<span class="nb">}</span>[t]<span class="nb">{</span>llll<span class="nb">}</span>
<span class="s">$</span><span class="nb">EnLvl</span><span class="s">$</span> <span class="nb">&amp;</span> <span class="s">$</span><span class="nb">RstLvl</span><span class="s">$</span> <span class="nb">&amp;</span> <span class="s">$</span><span class="nb">RstVal</span><span class="s">$</span> <span class="nb">&amp;</span> Cell Type <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DLATCH<span class="k">\_</span>NN0<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DLATCH<span class="k">\_</span>NN1<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DLATCH<span class="k">\_</span>NP0<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DLATCH<span class="k">\_</span>NP1<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DLATCH<span class="k">\_</span>PN0<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DLATCH<span class="k">\_</span>PN1<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DLATCH<span class="k">\_</span>PP0<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DLATCH<span class="k">\_</span>PP1<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\end</span><span class="nb">{</span>tabular<span class="nb">}</span>
<span class="k">\caption</span><span class="nb">{</span>Cell types for gate level logic networks (latches with reset)<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>tab:CellLib<span class="nb">_</span>gates<span class="nb">_</span>adlatch<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>table<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>table<span class="nb">}</span>[t]
<span class="k">\hfil</span>
<span class="k">\begin</span><span class="nb">{</span>tabular<span class="nb">}</span>[t]<span class="nb">{</span>llll<span class="nb">}</span>
<span class="s">$</span><span class="nb">EnLvl</span><span class="s">$</span> <span class="nb">&amp;</span> <span class="s">$</span><span class="nb">SetLvl</span><span class="s">$</span> <span class="nb">&amp;</span> <span class="s">$</span><span class="nb">RstLvl</span><span class="s">$</span> <span class="nb">&amp;</span> Cell Type <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DLATCHSR<span class="k">\_</span>NNN<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DLATCHSR<span class="k">\_</span>NNP<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DLATCHSR<span class="k">\_</span>NPN<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DLATCHSR<span class="k">\_</span>NPP<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DLATCHSR<span class="k">\_</span>PNN<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DLATCHSR<span class="k">\_</span>PNP<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DLATCHSR<span class="k">\_</span>PPN<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>DLATCHSR<span class="k">\_</span>PPP<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\end</span><span class="nb">{</span>tabular<span class="nb">}</span>
<span class="k">\caption</span><span class="nb">{</span>Cell types for gate level logic networks (latches with set and reset)<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>tab:CellLib<span class="nb">_</span>gates<span class="nb">_</span>dlatchsr<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>table<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>table<span class="nb">}</span>[t]
<span class="k">\hfil</span>
<span class="k">\begin</span><span class="nb">{</span>tabular<span class="nb">}</span>[t]<span class="nb">{</span>llll<span class="nb">}</span>
<span class="s">$</span><span class="nb">SetLvl</span><span class="s">$</span> <span class="nb">&amp;</span> <span class="s">$</span><span class="nb">RstLvl</span><span class="s">$</span> <span class="nb">&amp;</span> Cell Type <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SR<span class="k">\_</span>NN<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SR<span class="k">\_</span>NP<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;0; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SR<span class="k">\_</span>PN<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;1; <span class="nb">&amp;</span> <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>SR<span class="k">\_</span>PP<span class="k">\_</span><span class="nb">}</span> <span class="k">\\</span>
<span class="k">\end</span><span class="nb">{</span>tabular<span class="nb">}</span>
<span class="k">\caption</span><span class="nb">{</span>Cell types for gate level logic networks (SR latches)<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>tab:CellLib<span class="nb">_</span>gates<span class="nb">_</span>sr<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>table<span class="nb">}</span>

Tables~<span class="k">\ref</span><span class="nb">{</span>tab:CellLib<span class="nb">_</span>gates<span class="nb">}</span>, <span class="k">\ref</span><span class="nb">{</span>tab:CellLib<span class="nb">_</span>gates<span class="nb">_</span>dffe<span class="nb">}</span>, <span class="k">\ref</span><span class="nb">{</span>tab:CellLib<span class="nb">_</span>gates<span class="nb">_</span>adff<span class="nb">}</span>, <span class="k">\ref</span><span class="nb">{</span>tab:CellLib<span class="nb">_</span>gates<span class="nb">_</span>adffe<span class="nb">}</span>, <span class="k">\ref</span><span class="nb">{</span>tab:CellLib<span class="nb">_</span>gates<span class="nb">_</span>dffsr<span class="nb">}</span>, <span class="k">\ref</span><span class="nb">{</span>tab:CellLib<span class="nb">_</span>gates<span class="nb">_</span>dffsre<span class="nb">}</span>, <span class="k">\ref</span><span class="nb">{</span>tab:CellLib<span class="nb">_</span>gates<span class="nb">_</span>adlatch<span class="nb">}</span>, <span class="k">\ref</span><span class="nb">{</span>tab:CellLib<span class="nb">_</span>gates<span class="nb">_</span>dlatchsr<span class="nb">}</span> and <span class="k">\ref</span><span class="nb">{</span>tab:CellLib<span class="nb">_</span>gates<span class="nb">_</span>sr<span class="nb">}</span> list all cell types used for gate level logic. The cell types
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>BUF<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>NOT<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>AND<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>NAND<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>ANDNOT<span class="k">\_</span><span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>OR<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>NOR<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>ORNOT<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>XOR<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>XNOR<span class="k">\_</span><span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>AOI3<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>OAI3<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>AOI4<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>OAI4<span class="k">\_</span><span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>MUX<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>MUX4<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>MUX8<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>MUX16<span class="k">\_</span><span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>NMUX<span class="k">\_</span><span class="nb">}</span> are used to model combinatorial logic.
The cell type <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>TBUF<span class="k">\_</span><span class="nb">}</span> is used to model tristate logic.

The <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>MUX4<span class="k">\_</span><span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>MUX8<span class="k">\_</span><span class="nb">}</span> and <span class="nb">{</span><span class="k">\tt</span> <span class="k">\$\_</span>MUX16<span class="k">\_</span><span class="nb">}</span> cells are used to model wide muxes, and correspond to the following Verilog code:

<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[language=Verilog]
// <span class="s">$</span><span class="nb">_MUX</span><span class="m">4</span><span class="nb">_</span>
<span class="nb">assign Y </span><span class="o">=</span><span class="nb"> T ? </span><span class="o">(</span><span class="nb">S ? D : C</span><span class="o">)</span><span class="nb"> :</span>
<span class="nb">               </span><span class="o">(</span><span class="nb">S ? B : A</span><span class="o">)</span><span class="nb">;</span>
<span class="o">//</span><span class="nb"> </span><span class="s">$</span><span class="nb">_</span>MUX8<span class="nb">_</span>
assign Y = U ? T ? (S ? H : G) :
                   (S ? F : E) :
               T ? (S ? D : C) :
                   (S ? B : A);
// <span class="s">$</span><span class="nb">_MUX</span><span class="m">16</span><span class="nb">_</span>
<span class="nb">assign Y </span><span class="o">=</span><span class="nb"> V ? U ? T ? </span><span class="o">(</span><span class="nb">S ? P : O</span><span class="o">)</span><span class="nb"> :</span>
<span class="nb">                       </span><span class="o">(</span><span class="nb">S ? N : M</span><span class="o">)</span><span class="nb"> :</span>
<span class="nb">                   T ? </span><span class="o">(</span><span class="nb">S ? L : K</span><span class="o">)</span><span class="nb"> :</span>
<span class="nb">                       </span><span class="o">(</span><span class="nb">S ? J : I</span><span class="o">)</span><span class="nb"> :</span>
<span class="nb">               U ? T ? </span><span class="o">(</span><span class="nb">S ? H : G</span><span class="o">)</span><span class="nb"> :</span>
<span class="nb">                       </span><span class="o">(</span><span class="nb">S ? F : E</span><span class="o">)</span><span class="nb"> :</span>
<span class="nb">                   T ? </span><span class="o">(</span><span class="nb">S ? D : C</span><span class="o">)</span><span class="nb"> :</span>
<span class="nb">                       </span><span class="o">(</span><span class="nb">S ? B : A</span><span class="o">)</span><span class="nb">;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nb">The cell types {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$\_</span><span class="nb">DFF</span><span class="nv">\_</span><span class="nb">N</span><span class="nv">\_</span><span class="nb">} and {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$\_</span><span class="nb">DFF</span><span class="nv">\_</span><span class="nb">P</span><span class="nv">\_</span><span class="nb">} represent d</span><span class="o">-</span><span class="nb">type flip</span><span class="o">-</span><span class="nb">flops.</span>

<span class="nb">The cell types {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$\_</span><span class="nb">DFFE</span><span class="nv">\_</span><span class="o">[</span><span class="nb">NP</span><span class="o">][</span><span class="nb">NP</span><span class="o">]</span><span class="nv">\_</span><span class="nb">}</span>
<span class="nb">implement d</span><span class="o">-</span><span class="nb">type flip</span><span class="o">-</span><span class="nb">flops with enable. The values in the table for these cell types relate to the</span>
<span class="nb">following Verilog code template.</span>

<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">mathescape,language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb"></span>
<span class="nb">	always @</span><span class="o">(</span><span class="s">$</span>ClkEdge<span class="s">$</span><span class="nb"> C</span><span class="o">)</span><span class="nb"></span>
<span class="nb">		if </span><span class="o">(</span><span class="nb">EN </span><span class="o">==</span><span class="nb"> </span><span class="s">$</span>EnLvl<span class="s">$</span><span class="o">)</span><span class="nb"></span>
<span class="nb">			Q &lt;</span><span class="o">=</span><span class="nb"> D;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nb">The cell types {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$\_</span><span class="nb">DFF</span><span class="nv">\_</span><span class="o">[</span><span class="nb">NP</span><span class="o">][</span><span class="nb">NP</span><span class="o">][</span><span class="m">01</span><span class="o">]</span><span class="nv">\_</span><span class="nb">} implement</span>
<span class="nb">d</span><span class="o">-</span><span class="nb">type flip</span><span class="o">-</span><span class="nb">flops with asynchronous reset. The values in the table for these cell types relate to the</span>
<span class="nb">following Verilog code template, where </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">mathescape,language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">;</span><span class="s">$</span>RstEdge<span class="s">$</span><span class="nb">; is </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">;posedge;</span>
<span class="nb">if </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">mathescape,language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">;</span><span class="s">$</span>RstLvl<span class="s">$</span><span class="nb">; if </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">;</span><span class="m">1</span><span class="nb">;, and </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">;negedge;</span>
<span class="nb">otherwise.</span>

<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">mathescape,language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb"></span>
<span class="nb">	always @</span><span class="o">(</span><span class="s">$</span>ClkEdge<span class="s">$</span><span class="nb"> C, </span><span class="s">$</span>RstEdge<span class="s">$</span><span class="nb"> R</span><span class="o">)</span><span class="nb"></span>
<span class="nb">		if </span><span class="o">(</span><span class="nb">R </span><span class="o">==</span><span class="nb"> </span><span class="s">$</span>RstLvl<span class="s">$</span><span class="o">)</span><span class="nb"></span>
<span class="nb">			Q &lt;</span><span class="o">=</span><span class="nb"> </span><span class="s">$</span>RstVal<span class="s">$</span><span class="nb">;</span>
<span class="nb">		else</span>
<span class="nb">			Q &lt;</span><span class="o">=</span><span class="nb"> D;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nb">The cell types {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$\_</span><span class="nb">SDFF</span><span class="nv">\_</span><span class="o">[</span><span class="nb">NP</span><span class="o">][</span><span class="nb">NP</span><span class="o">][</span><span class="m">01</span><span class="o">]</span><span class="nv">\_</span><span class="nb">} implement</span>
<span class="nb">d</span><span class="o">-</span><span class="nb">type flip</span><span class="o">-</span><span class="nb">flops with synchronous reset. The values in the table for these cell types relate to the</span>
<span class="nb">following Verilog code template:</span>

<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">mathescape,language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb"></span>
<span class="nb">	always @</span><span class="o">(</span><span class="s">$</span>ClkEdge<span class="s">$</span><span class="nb"> C</span><span class="o">)</span><span class="nb"></span>
<span class="nb">		if </span><span class="o">(</span><span class="nb">R </span><span class="o">==</span><span class="nb"> </span><span class="s">$</span>RstLvl<span class="s">$</span><span class="o">)</span><span class="nb"></span>
<span class="nb">			Q &lt;</span><span class="o">=</span><span class="nb"> </span><span class="s">$</span>RstVal<span class="s">$</span><span class="nb">;</span>
<span class="nb">		else</span>
<span class="nb">			Q &lt;</span><span class="o">=</span><span class="nb"> D;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nb">The cell types {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$\_</span><span class="nb">DFFE</span><span class="nv">\_</span><span class="o">[</span><span class="nb">NP</span><span class="o">][</span><span class="nb">NP</span><span class="o">][</span><span class="m">01</span><span class="o">][</span><span class="nb">NP</span><span class="o">]</span><span class="nv">\_</span><span class="nb">} implement</span>
<span class="nb">d</span><span class="o">-</span><span class="nb">type flip</span><span class="o">-</span><span class="nb">flops with asynchronous reset and enable.  The values in the table for these cell types relate to the</span>
<span class="nb">following Verilog code template, where </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">mathescape,language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">;</span><span class="s">$</span>RstEdge<span class="s">$</span><span class="nb">; is </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">;posedge;</span>
<span class="nb">if </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">mathescape,language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">;</span><span class="s">$</span>RstLvl<span class="s">$</span><span class="nb">; if </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">;</span><span class="m">1</span><span class="nb">;, and </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">;negedge;</span>
<span class="nb">otherwise.</span>

<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">mathescape,language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb"></span>
<span class="nb">	always @</span><span class="o">(</span><span class="s">$</span>ClkEdge<span class="s">$</span><span class="nb"> C, </span><span class="s">$</span>RstEdge<span class="s">$</span><span class="nb"> R</span><span class="o">)</span><span class="nb"></span>
<span class="nb">		if </span><span class="o">(</span><span class="nb">R </span><span class="o">==</span><span class="nb"> </span><span class="s">$</span>RstLvl<span class="s">$</span><span class="o">)</span><span class="nb"></span>
<span class="nb">			Q &lt;</span><span class="o">=</span><span class="nb"> </span><span class="s">$</span>RstVal<span class="s">$</span><span class="nb">;</span>
<span class="nb">		else if </span><span class="o">(</span><span class="nb">EN </span><span class="o">==</span><span class="nb"> </span><span class="s">$</span>EnLvl<span class="s">$</span><span class="o">)</span><span class="nb"></span>
<span class="nb">			Q &lt;</span><span class="o">=</span><span class="nb"> D;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nb">The cell types {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$\_</span><span class="nb">SDFFE</span><span class="nv">\_</span><span class="o">[</span><span class="nb">NP</span><span class="o">][</span><span class="nb">NP</span><span class="o">][</span><span class="m">01</span><span class="o">][</span><span class="nb">NP</span><span class="o">]</span><span class="nv">\_</span><span class="nb">} implement d</span><span class="o">-</span><span class="nb">type flip</span><span class="o">-</span><span class="nb">flops</span>
<span class="nb">with synchronous reset and enable, with reset having priority over enable.</span>
<span class="nb">The values in the table for these cell types relate to the</span>
<span class="nb">following Verilog code template:</span>

<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">mathescape,language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb"></span>
<span class="nb">	always @</span><span class="o">(</span><span class="s">$</span>ClkEdge<span class="s">$</span><span class="nb"> C</span><span class="o">)</span><span class="nb"></span>
<span class="nb">		if </span><span class="o">(</span><span class="nb">R </span><span class="o">==</span><span class="nb"> </span><span class="s">$</span>RstLvl<span class="s">$</span><span class="o">)</span><span class="nb"></span>
<span class="nb">			Q &lt;</span><span class="o">=</span><span class="nb"> </span><span class="s">$</span>RstVal<span class="s">$</span><span class="nb">;</span>
<span class="nb">		else if </span><span class="o">(</span><span class="nb">EN </span><span class="o">==</span><span class="nb"> </span><span class="s">$</span>EnLvl<span class="s">$</span><span class="o">)</span><span class="nb"></span>
<span class="nb">			Q &lt;</span><span class="o">=</span><span class="nb"> D;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nb">The cell types {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$\_</span><span class="nb">SDFFCE</span><span class="nv">\_</span><span class="o">[</span><span class="nb">NP</span><span class="o">][</span><span class="nb">NP</span><span class="o">][</span><span class="m">01</span><span class="o">][</span><span class="nb">NP</span><span class="o">]</span><span class="nv">\_</span><span class="nb">} implement d</span><span class="o">-</span><span class="nb">type flip</span><span class="o">-</span><span class="nb">flops</span>
<span class="nb">with synchronous reset and enable, with enable having priority over reset.</span>
<span class="nb">The values in the table for these cell types relate to the</span>
<span class="nb">following Verilog code template:</span>

<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">mathescape,language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb"></span>
<span class="nb">	always @</span><span class="o">(</span><span class="s">$</span>ClkEdge<span class="s">$</span><span class="nb"> C</span><span class="o">)</span><span class="nb"></span>
<span class="nb">		if </span><span class="o">(</span><span class="nb">EN </span><span class="o">==</span><span class="nb"> </span><span class="s">$</span>EnLvl<span class="s">$</span><span class="o">)</span><span class="nb"></span>
<span class="nb">			if </span><span class="o">(</span><span class="nb">R </span><span class="o">==</span><span class="nb"> </span><span class="s">$</span>RstLvl<span class="s">$</span><span class="o">)</span><span class="nb"></span>
<span class="nb">				Q &lt;</span><span class="o">=</span><span class="nb"> </span><span class="s">$</span>RstVal<span class="s">$</span><span class="nb">;</span>
<span class="nb">			else</span>
<span class="nb">				Q &lt;</span><span class="o">=</span><span class="nb"> D;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nb">The cell types {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$\_</span><span class="nb">DFFSR</span><span class="nv">\_</span><span class="o">[</span><span class="nb">NP</span><span class="o">][</span><span class="nb">NP</span><span class="o">][</span><span class="nb">NP</span><span class="o">]</span><span class="nv">\_</span><span class="nb">} implement</span>
<span class="nb">d</span><span class="o">-</span><span class="nb">type flip</span><span class="o">-</span><span class="nb">flops with asynchronous set and reset. The values in the table for these cell types relate to the</span>
<span class="nb">following Verilog code template, where </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">mathescape,language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">;</span><span class="s">$</span>RstEdge<span class="s">$</span><span class="nb">; is </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">;posedge;</span>
<span class="nb">if </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">mathescape,language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">;</span><span class="s">$</span>RstLvl<span class="s">$</span><span class="nb">; if </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">;</span><span class="m">1</span><span class="nb">;, </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">;negedge;</span>
<span class="nb">otherwise, and </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">mathescape,language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">;</span><span class="s">$</span>SetEdge<span class="s">$</span><span class="nb">; is </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">;posedge;</span>
<span class="nb">if </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">mathescape,language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">;</span><span class="s">$</span>SetLvl<span class="s">$</span><span class="nb">; if </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">;</span><span class="m">1</span><span class="nb">;, </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">;negedge;</span>
<span class="nb">otherwise.</span>

<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">mathescape,language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb"></span>
<span class="nb">	always @</span><span class="o">(</span><span class="s">$</span>ClkEdge<span class="s">$</span><span class="nb"> C, </span><span class="s">$</span>RstEdge<span class="s">$</span><span class="nb"> R, </span><span class="s">$</span>SetEdge<span class="s">$</span><span class="nb"> S</span><span class="o">)</span><span class="nb"></span>
<span class="nb">		if </span><span class="o">(</span><span class="nb">R </span><span class="o">==</span><span class="nb"> </span><span class="s">$</span>RstLvl<span class="s">$</span><span class="o">)</span><span class="nb"></span>
<span class="nb">			Q &lt;</span><span class="o">=</span><span class="nb"> </span><span class="m">0</span><span class="nb">;</span>
<span class="nb">		else if </span><span class="o">(</span><span class="nb">S </span><span class="o">==</span><span class="nb"> </span><span class="s">$</span>SetLvl<span class="s">$</span><span class="o">)</span><span class="nb"></span>
<span class="nb">			Q &lt;</span><span class="o">=</span><span class="nb"> </span><span class="m">1</span><span class="nb">;</span>
<span class="nb">		else</span>
<span class="nb">			Q &lt;</span><span class="o">=</span><span class="nb"> D;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nb">The cell types {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$\_</span><span class="nb">DFFSRE</span><span class="nv">\_</span><span class="o">[</span><span class="nb">NP</span><span class="o">][</span><span class="nb">NP</span><span class="o">][</span><span class="nb">NP</span><span class="o">][</span><span class="nb">NP</span><span class="o">]</span><span class="nv">\_</span><span class="nb">} implement</span>
<span class="nb">d</span><span class="o">-</span><span class="nb">type flip</span><span class="o">-</span><span class="nb">flops with asynchronous set and reset and enable. The values in the table for these cell types relate to the</span>
<span class="nb">following Verilog code template, where </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">mathescape,language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">;</span><span class="s">$</span>RstEdge<span class="s">$</span><span class="nb">; is </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">;posedge;</span>
<span class="nb">if </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">mathescape,language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">;</span><span class="s">$</span>RstLvl<span class="s">$</span><span class="nb">; if </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">;</span><span class="m">1</span><span class="nb">;, </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">;negedge;</span>
<span class="nb">otherwise, and </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">mathescape,language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">;</span><span class="s">$</span>SetEdge<span class="s">$</span><span class="nb">; is </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">;posedge;</span>
<span class="nb">if </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">mathescape,language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">;</span><span class="s">$</span>SetLvl<span class="s">$</span><span class="nb">; if </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">;</span><span class="m">1</span><span class="nb">;, </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">;negedge;</span>
<span class="nb">otherwise.</span>

<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">mathescape,language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb"></span>
<span class="nb">	always @</span><span class="o">(</span><span class="s">$</span>ClkEdge<span class="s">$</span><span class="nb"> C, </span><span class="s">$</span>RstEdge<span class="s">$</span><span class="nb"> R, </span><span class="s">$</span>SetEdge<span class="s">$</span><span class="nb"> S</span><span class="o">)</span><span class="nb"></span>
<span class="nb">		if </span><span class="o">(</span><span class="nb">R </span><span class="o">==</span><span class="nb"> </span><span class="s">$</span>RstLvl<span class="s">$</span><span class="o">)</span><span class="nb"></span>
<span class="nb">			Q &lt;</span><span class="o">=</span><span class="nb"> </span><span class="m">0</span><span class="nb">;</span>
<span class="nb">		else if </span><span class="o">(</span><span class="nb">S </span><span class="o">==</span><span class="nb"> </span><span class="s">$</span>SetLvl<span class="s">$</span><span class="o">)</span><span class="nb"></span>
<span class="nb">			Q &lt;</span><span class="o">=</span><span class="nb"> </span><span class="m">1</span><span class="nb">;</span>
<span class="nb">		else if </span><span class="o">(</span><span class="nb">E </span><span class="o">==</span><span class="nb"> </span><span class="s">$</span>EnLvl<span class="s">$</span><span class="o">)</span><span class="nb"></span>
<span class="nb">			Q &lt;</span><span class="o">=</span><span class="nb"> D;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nb">The cell types {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$\_</span><span class="nb">DLATCH</span><span class="nv">\_</span><span class="nb">N</span><span class="nv">\_</span><span class="nb">} and {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$\_</span><span class="nb">DLATCH</span><span class="nv">\_</span><span class="nb">P</span><span class="nv">\_</span><span class="nb">} represent d</span><span class="o">-</span><span class="nb">type latches.</span>

<span class="nb">The cell types {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$\_</span><span class="nb">DLATCH</span><span class="nv">\_</span><span class="o">[</span><span class="nb">NP</span><span class="o">][</span><span class="nb">NP</span><span class="o">][</span><span class="m">01</span><span class="o">]</span><span class="nv">\_</span><span class="nb">} implement</span>
<span class="nb">d</span><span class="o">-</span><span class="nb">type latches with reset. The values in the table for these cell types relate to the</span>
<span class="nb">following Verilog code template:</span>

<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">mathescape,language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb"></span>
<span class="nb">	always @</span><span class="o">*</span><span class="nb"></span>
<span class="nb">		if </span><span class="o">(</span><span class="nb">R </span><span class="o">==</span><span class="nb"> </span><span class="s">$</span>RstLvl<span class="s">$</span><span class="o">)</span><span class="nb"></span>
<span class="nb">			Q &lt;</span><span class="o">=</span><span class="nb"> </span><span class="s">$</span>RstVal<span class="s">$</span><span class="nb">;</span>
<span class="nb">		else if </span><span class="o">(</span><span class="nb">E </span><span class="o">==</span><span class="nb"> </span><span class="s">$</span>EnLvl<span class="s">$</span><span class="o">)</span><span class="nb"></span>
<span class="nb">			Q &lt;</span><span class="o">=</span><span class="nb"> D;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nb">The cell types {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$\_</span><span class="nb">DLATCHSR</span><span class="nv">\_</span><span class="o">[</span><span class="nb">NP</span><span class="o">][</span><span class="nb">NP</span><span class="o">][</span><span class="nb">NP</span><span class="o">]</span><span class="nv">\_</span><span class="nb">} implement</span>
<span class="nb">d</span><span class="o">-</span><span class="nb">type latches with set and reset. The values in the table for these cell types relate to the</span>
<span class="nb">following Verilog code template:</span>

<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">mathescape,language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb"></span>
<span class="nb">	always @</span><span class="o">*</span><span class="nb"></span>
<span class="nb">		if </span><span class="o">(</span><span class="nb">R </span><span class="o">==</span><span class="nb"> </span><span class="s">$</span>RstLvl<span class="s">$</span><span class="o">)</span><span class="nb"></span>
<span class="nb">			Q &lt;</span><span class="o">=</span><span class="nb"> </span><span class="m">0</span><span class="nb">;</span>
<span class="nb">		else if </span><span class="o">(</span><span class="nb">S </span><span class="o">==</span><span class="nb"> </span><span class="s">$</span>SetLvl<span class="s">$</span><span class="o">)</span><span class="nb"></span>
<span class="nb">			Q &lt;</span><span class="o">=</span><span class="nb"> </span><span class="m">1</span><span class="nb">;</span>
<span class="nb">		else if </span><span class="o">(</span><span class="nb">E </span><span class="o">==</span><span class="nb"> </span><span class="s">$</span>EnLvl<span class="s">$</span><span class="o">)</span><span class="nb"></span>
<span class="nb">			Q &lt;</span><span class="o">=</span><span class="nb"> D;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nb">The cell types {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$\_</span><span class="nb">SR</span><span class="nv">\_</span><span class="o">[</span><span class="nb">NP</span><span class="o">][</span><span class="nb">NP</span><span class="o">]</span><span class="nv">\_</span><span class="nb">} implement</span>
<span class="nb">sr</span><span class="o">-</span><span class="nb">type latches. The values in the table for these cell types relate to the</span>
<span class="nb">following Verilog code template:</span>

<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">mathescape,language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb"></span>
<span class="nb">	always @</span><span class="o">*</span><span class="nb"></span>
<span class="nb">		if </span><span class="o">(</span><span class="nb">R </span><span class="o">==</span><span class="nb"> </span><span class="s">$</span>RstLvl<span class="s">$</span><span class="o">)</span><span class="nb"></span>
<span class="nb">			Q &lt;</span><span class="o">=</span><span class="nb"> </span><span class="m">0</span><span class="nb">;</span>
<span class="nb">		else if </span><span class="o">(</span><span class="nb">S </span><span class="o">==</span><span class="nb"> </span><span class="s">$</span>SetLvl<span class="s">$</span><span class="o">)</span><span class="nb"></span>
<span class="nb">			Q &lt;</span><span class="o">=</span><span class="nb"> </span><span class="m">1</span><span class="nb">;</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nb">In most cases gate level logic networks are created from RTL networks using the {</span><span class="nv">\tt</span><span class="nb"> techmap} pass. The flip</span><span class="o">-</span><span class="nb">flop cells</span>
<span class="nb">from the gate level logic network can be mapped to physical flip</span><span class="o">-</span><span class="nb">flop cells from a Liberty file using the {</span><span class="nv">\tt</span><span class="nb"> dfflibmap}</span>
<span class="nb">pass. The combinatorial logic cells can be mapped to physical cells from a Liberty file via ABC </span><span class="nv">\citeweblink</span><span class="nb">{ABC}</span>
<span class="nb">using the {</span><span class="nv">\tt</span><span class="nb"> abc} pass.</span>

<span class="nv">\begin</span><span class="nb">{fixme}</span>
<span class="nb">Add information about {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$</span><span class="nb">slice} and {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$</span><span class="nb">concat} cells.</span>
<span class="nv">\end</span><span class="nb">{fixme}</span>

<span class="nv">\begin</span><span class="nb">{fixme}</span>
<span class="nb">Add information about {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$</span><span class="nb">lut} and {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$</span><span class="nb">sop} cells.</span>
<span class="nv">\end</span><span class="nb">{fixme}</span>

<span class="nv">\begin</span><span class="nb">{fixme}</span>
<span class="nb">Add information about {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$</span><span class="nb">alu}, {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$</span><span class="nb">macc}, {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$</span><span class="nb">fa}, and {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$</span><span class="nb">lcu} cells.</span>
<span class="nv">\end</span><span class="nb">{fixme}</span>
</pre></div>
</code></pre></td></tr></table>
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