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.highlight .il { color: #0000DD; font-weight: bold } /* Literal.Number.Integer.Long */</style><div class="highlight"><pre><span></span><span class="k">\chapter</span><span class="nb">{</span>Application Notes<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>chapter:appnotes<span class="nb">}</span>

<span class="c">% \begin{fixme}</span>
<span class="c">% This appendix will cover some typical use-cases of Yosys in the form of application notes.</span>
<span class="c">% \end{fixme}</span>
<span class="c">%</span>
<span class="c">% \section{Synthesizing using a Cell Library in Liberty Format}</span>
<span class="c">% \section{Reverse Engineering the MOS6502 from an NMOS Transistor Netlist}</span>
<span class="c">% \section{Reconfigurable Coarse-Grain Synthesis using Intersynth}</span>

This appendix contains copies of the Yosys application notes.

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> Yosys AppNote 010: Converting Verilog to BLIF <span class="k">\dotfill</span> Page <span class="k">\pageref</span><span class="nb">{</span>app:010<span class="nb">}</span> <span class="k">\hskip</span>2cm<span class="k">\null</span>
<span class="k">\item</span> Yosys AppNote 011: Interactive Design Investigation <span class="k">\dotfill</span> Page <span class="k">\pageref</span><span class="nb">{</span>app:011<span class="nb">}</span> <span class="k">\hskip</span>2cm<span class="k">\null</span>
<span class="k">\item</span> Yosys AppNote 012: Converting Verilog to BTOR <span class="k">\dotfill</span> Page <span class="k">\pageref</span><span class="nb">{</span>app:012<span class="nb">}</span> <span class="k">\hskip</span>2cm<span class="k">\null</span>
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

<span class="k">\eject\label</span><span class="nb">{</span>app:010<span class="nb">}</span>
<span class="k">\includepdf</span><span class="na">[pages=-,pagecommand=\thispagestyle{plain}]</span><span class="nb">{</span>APPNOTE<span class="nb">_</span>010<span class="nb">_</span>Verilog<span class="nb">_</span>to<span class="nb">_</span>BLIF.pdf<span class="nb">}</span>

<span class="k">\eject\label</span><span class="nb">{</span>app:011<span class="nb">}</span>
<span class="k">\includepdf</span><span class="na">[pages=-,pagecommand=\thispagestyle{plain}]</span><span class="nb">{</span>APPNOTE<span class="nb">_</span>011<span class="nb">_</span>Design<span class="nb">_</span>Investigation.pdf<span class="nb">}</span>

<span class="k">\eject\label</span><span class="nb">{</span>app:012<span class="nb">}</span>
<span class="k">\includepdf</span><span class="na">[pages=-,pagecommand=\thispagestyle{plain}]</span><span class="nb">{</span>APPNOTE<span class="nb">_</span>012<span class="nb">_</span>Verilog<span class="nb">_</span>to<span class="nb">_</span>BTOR.pdf<span class="nb">}</span>
</pre></div>
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