# -*- Makefile -*- for the VHDL libraries. # Copyright (C) 2002, 2003, 2004, 2005 Tristan Gingold # # GHDL is free software; you can redistribute it and/or modify it under # the terms of the GNU General Public License as published by the Free # Software Foundation; either version 2, or (at your option) any later # version. # # GHDL is distributed in the hope that it will be useful, but WITHOUT ANY # WARRANTY; without even the implied warranty of MERCHANTABILITY or # FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License # for more details. # # You should have received a copy of the GNU General Public License # along with GCC; see the file COPYING. If not, write to the Free # Software Foundation, 59 Temple Place - Suite 330, Boston, MA # 02111-1307, USA. # Variable to be defined: # LIBSRC_DIR: path to the libraries sources # LIBDST_DIR: path to the build/destination dir. # GHDL # GHDL_FLAGS # LN # CP # MKDIR # VHDLLIBS_COPY_OBJS: must be set to 'no' for jit vhdl.libs.all: vhdl.libs.v87 vhdl.libs.v93 vhdl.libs.v08 enable_openieee=false ifeq ($(enable_openieee),false) # Full libraries vhdl.libs.v87: std.v87 ieee.v87 vhdl.libs.v93: std.v93 ieee.v93 vhdl.libs.v08: std.v08 ieee.v08 $(LIBDST_DIR)/src/ieee2008/LICENSE else # GPL compatible vhdl.libs.v87: std.v87 ieee.v87 vhdl.libs.v93: std.v93 ieee.v93 vhdl.libs.v08: std.v08 ieee.v08 endif STD_SRCS := textio.vhdl textio-body.vhdl SYNOPSYS_BSRCS := std_logic_arith.vhdl \ std_logic_unsigned.vhdl std_logic_signed.vhdl SYNOPSYS_V_BSRCS := std_logic_misc.vhdl std_logic_misc-body.vhdl SYNOPSYS8793_BSRCS := std_logic_textio.vhdl UPF_SRCS := openieee/upf.vhdl openieee/upf-body.vhdl ifeq ($(enable_openieee),false) IEEE_SRCS := std_logic_1164.vhdl std_logic_1164-body.vhdl \ numeric_bit.vhdl numeric_bit-body.vhdl \ numeric_std.vhdl numeric_std-body.vhdl MATH_SRCS := math_real.vhdl math_real-body.vhdl \ math_complex.vhdl math_complex-body.vhdl VITAL95_BSRCS := vital95/vital_timing.vhdl vital95/vital_timing-body.vhdl \ vital95/vital_primitives.vhdl vital95/vital_primitives-body.vhdl VITAL2000_BSRCS := vital2000/timing_p.vhdl vital2000/timing_b.vhdl \ vital2000/prmtvs_p.vhdl vital2000/prmtvs_b.vhdl \ vital2000/memory_p.vhdl vital2000/memory_b.vhdl IEEE08_BSRCS := \ ieee2008/std_logic_1164.vhdl ieee2008/std_logic_1164-body.vhdl \ ieee2008/std_logic_textio.vhdl \ ieee2008/math_real.vhdl ieee2008/math_real-body.vhdl \ ieee2008/math_complex.vhdl ieee2008/math_complex-body.vhdl \ ieee2008/numeric_bit.vhdl ieee2008/numeric_bit-body.vhdl \ ieee2008/numeric_bit_unsigned.vhdl ieee2008/numeric_bit_unsigned-body.vhdl \ ieee2008/numeric_std.vhdl ieee2008/numeric_std-body.vhdl \ ieee2008/numeric_std_unsigned.vhdl ieee2008/numeric_std_unsigned-body.vhdl \ ieee2008/fixed_float_types.vhdl \ ieee2008/fixed_generic_pkg.vhdl ieee2008/fixed_generic_pkg-body.vhdl \ ieee2008/fixed_pkg.vhdl \ ieee2008/float_generic_pkg.vhdl ieee2008/float_generic_pkg-body.vhdl \ ieee2008/float_pkg.vhdl \ ieee2008/ieee_bit_context.vhdl ieee2008/ieee_std_context.vhdl \ $(UPF_SRCS) IEEE87_BSRCS := $(addprefix ieee/v87/,$(IEEE_SRCS)) $(UPF_SRCS) IEEE93_BSRCS := $(addprefix ieee/v93/,$(IEEE_SRCS)) $(addprefix ieee/,$(MATH_SRCS)) $(UPF_SRCS) else IEEE_SRCS := std_logic_1164.vhdl std_logic_1164-body.vhdl \ numeric_bit.vhdl numeric_bit-body.vhdl \ numeric_std.vhdl numeric_std-body.vhdl MATH_SRCS := math_real.vhdl math_real-body.vhdl VITAL95_BSRCS := VITAL2000_BSRCS := IEEE08_BSRCS := v08/std_logic_1164.vhdl v08/std_logic_1164-body.vhdl \ math_real.vhdl math_real-body.vhdl IEEE87_BSRCS := $(addprefix openieee/v87/,$(IEEE_SRCS)) $(UPF_SRCS) IEEE93_BSRCS := $(addprefix openieee/v93/,$(IEEE_SRCS)) $(addprefix openieee/,$(MATH_SRCS)) $(UPF_SRCS) IEEE08_BSRCS := $(addprefix openieee/,$(IEEE08_BSRCS)) $(UPF_SRCS) endif ANALYZE=$(GHDL) -a $(GHDL_FLAGS) ANALYZE_DEP=$(GHDL) STD87_BSRCS := $(addprefix std/v87/,$(STD_SRCS)) STD93_BSRCS := $(addprefix std/v93/,$(STD_SRCS)) STD08_BSRCS := $(addprefix std/v08/,$(STD_SRCS)) std/env.vhdl std/env-body.vhdl SYNOPSYS87_BSRCS := $(addprefix synopsys/,$(SYNOPSYS_BSRCS) $(SYNOPSYS_V_BSRCS) $(SYNOPSYS8793_BSRCS)) SYNOPSYS93_BSRCS := $(addprefix synopsys/,$(SYNOPSYS_BSRCS) $(SYNOPSYS_V_BSRCS) $(SYNOPSYS8793_BSRCS)) SYNOPSYS08_BSRCS := $(addprefix synopsys/,$(SYNOPSYS_BSRCS)) $(addprefix synopsys/v08/,$(SYNOPSYS_V_BSRCS)) .PREFIXES: .vhdl SED_V93:= sed -e '/--V87/s/^/ --/' \ -e '/--START-V08/,/--END-V08/s/^/--/' SED_V87:= sed -e '/--!V87/s/^/ --/' -e '/--START-!V87/,/--END-!V87/s/^/--/' \ -e '/--START-V08/,/--END-V08/s/^/--/' SED_V08:= sed -e '/--V87/s/^/ --/' -e '/--!
# verbose

graph macc22
	node mul_1 mul A 32 B 32 Y 32
	node mul_2 mul A 32 B 32 Y 32
	node add_1 add A 32 B 32 Y 32
	connect mul_1 Y add_1 A
	connect mul_2 Y add_1 B
	extern mul_1 A B
	extern mul_2 A B
	extern add_1 Y
endgraph

graph macc4x2
	node mul_1 mul A 32 B 32 Y 32
	node mul_2 mul A 32 B 32 Y 32
	node mul_3 mul A 32 B 32 Y 32
	node mul_4 mul A 32 B 32 Y 32
	node add_1 add A 32 B 32 Y 32
	node add_2 add A 32 B 32 Y 32
	node add_3 add A 32 B 32 Y 32
	connect mul_1 Y add_1 A
	connect mul_2 Y add_1 B
	connect mul_3 Y add_2 A
	connect mul_4 Y add_2 B
	connect add_1 Y add_3 A
	connect add_2 Y add_3 B
	extern mul_1 A B
	extern mul_2 A B
	extern mul_3 A B
	extern mul_4 A B
	extern add_3 Y
endgraph

solve macc22 macc4x2
expect 2

swapgroup mul A B

solve macc22 macc4x2
expect 2

swapperm add A B : B A

solve macc22 macc4x2
expect 4
generated by cgit v1.2.3 (git 2.25.1) at 2025-07-23 12:29:08 +0000