aboutsummaryrefslogtreecommitdiffstats
path: root/tools/xenfb/vncfb.c
diff options
context:
space:
mode:
authorSteven Smith <ssmith@xensource.com>2006-12-01 09:48:32 +0000
committerSteven Smith <ssmith@xensource.com>2006-12-01 09:48:32 +0000
commita5ae44fcdf672966b1b31949dd3a142f75e7f90a (patch)
tree40d31c3651ee2c0dc1ed60166a8f91e75e84ed70 /tools/xenfb/vncfb.c
parentb4f5b27478ed1a82018f28dbd2a696701a286052 (diff)
downloadxen-a5ae44fcdf672966b1b31949dd3a142f75e7f90a.tar.gz
xen-a5ae44fcdf672966b1b31949dd3a142f75e7f90a.tar.bz2
xen-a5ae44fcdf672966b1b31949dd3a142f75e7f90a.zip
This is Anthony Liguori's virtual framebuffer forward ported and
extensively hacked based on feedback from xen-devel. Its architecture is comparable to the common split device driver architecture: xenfb and xenkbd modules serve as frontend in domU, and the user space vncfb or sdlfb process serves as backend in dom0. Signed-off-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Diffstat (limited to 'tools/xenfb/vncfb.c')
-rw-r--r--tools/xenfb/vncfb.c393
1 files changed, 393 insertions, 0 deletions
diff --git a/tools/xenfb/vncfb.c b/tools/xenfb/vncfb.c
new file mode 100644
index 0000000000..2fc970e0cc
--- /dev/null
+++ b/tools/xenfb/vncfb.c
@@ -0,0 +1,393 @@
+#define _GNU_SOURCE
+#include <errno.h>
+#include <getopt.h>
+#include <stdlib.h>
+#include <signal.h>
+#include <unistd.h>
+#include <malloc.h>
+#include <rfb/rfb.h>
+#include <rfb/keysym.h>
+#include <linux/input.h>
+#include <xs.h>
+#include "xenfb.h"
+
+static int xk2linux[0x10000] = {
+ [XK_a] = KEY_A,
+ [XK_b] = KEY_B,
+ [XK_c] = KEY_C,
+ [XK_d] = KEY_D,
+ [XK_e] = KEY_E,
+ [XK_f] = KEY_F,
+ [XK_g] = KEY_G,
+ [XK_h] = KEY_H,
+ [XK_i] = KEY_I,
+ [XK_j] = KEY_J,
+ [XK_k] = KEY_K,
+ [XK_l] = KEY_L,
+ [XK_m] = KEY_M,
+ [XK_n] = KEY_N,
+ [XK_o] = KEY_O,
+ [XK_p] = KEY_P,
+ [XK_q] = KEY_Q,
+ [XK_r] = KEY_R,
+ [XK_s] = KEY_S,
+ [XK_t] = KEY_T,
+ [XK_u] = KEY_U,
+ [XK_v] = KEY_V,
+ [XK_w] = KEY_W,
+ [XK_x] = KEY_X,
+ [XK_y] = KEY_Y,
+ [XK_z] = KEY_Z,
+ [XK_A] = KEY_A,
+ [XK_B] = KEY_B,
+ [XK_C] = KEY_C,
+ [XK_D] = KEY_D,
+ [XK_E] = KEY_E,
+ [XK_F] = KEY_F,
+ [XK_G] = KEY_G,
+ [XK_H] = KEY_H,
+ [XK_I] = KEY_I,
+ [XK_J] = KEY_J,
+ [XK_K] = KEY_K,
+ [XK_L] = KEY_L,
+ [XK_M] = KEY_M,
+ [XK_N] = KEY_N,
+ [XK_O] = KEY_O,
+ [XK_P] = KEY_P,
+ [XK_Q] = KEY_Q,
+ [XK_R] = KEY_R,
+ [XK_S] = KEY_S,
+ [XK_T] = KEY_T,
+ [XK_U] = KEY_U,
+ [XK_V] = KEY_V,
+ [XK_W] = KEY_W,
+ [XK_X] = KEY_X,
+ [XK_Y] = KEY_Y,
+ [XK_Z] = KEY_Z,
+ [XK_0] = KEY_0,
+ [XK_1] = KEY_1,
+ [XK_2] = KEY_2,
+ [XK_3] = KEY_3,
+ [XK_4] = KEY_4,
+ [XK_5] = KEY_5,
+ [XK_6] = KEY_6,
+ [XK_7] = KEY_7,
+ [XK_8] = KEY_8,
+ [XK_9] = KEY_9,
+ [XK_Return] = KEY_ENTER,
+ [XK_BackSpace] = KEY_BACKSPACE,
+ [XK_Tab] = KEY_TAB,
+ [XK_Pause] = KEY_PAUSE,
+ [XK_Delete] = KEY_DELETE,
+ [XK_slash] = KEY_SLASH,
+ [XK_minus] = KEY_MINUS,
+ [XK_equal] = KEY_EQUAL,
+ [XK_Escape] = KEY_ESC,
+ [XK_braceleft] = KEY_LEFTBRACE,
+ [XK_braceright] = KEY_RIGHTBRACE,
+ [XK_bracketleft] = KEY_LEFTMETA,
+ [XK_bracketright] = KEY_RIGHTMETA,
+ [XK_Control_L] = KEY_LEFTCTRL,
+ [XK_Control_R] = KEY_RIGHTCTRL,
+ [XK_Shift_L] = KEY_LEFTSHIFT,
+ [XK_Shift_R] = KEY_RIGHTSHIFT,
+ [XK_Alt_L] = KEY_LEFTALT,
+ [XK_Alt_R] = KEY_RIGHTALT,
+ [XK_semicolon] = KEY_SEMICOLON,
+ [XK_apostrophe] = KEY_APOSTROPHE,
+ [XK_grave] = KEY_GRAVE,
+ [XK_backslash] = KEY_BACKSLASH,
+ [XK_comma] = KEY_COMMA,
+ [XK_period] = KEY_DOT,
+ [XK_space] = KEY_SPACE,
+ [XK_Caps_Lock] = KEY_CAPSLOCK,
+ [XK_Num_Lock] = KEY_NUMLOCK,
+ [XK_Scroll_Lock] = KEY_SCROLLLOCK,
+ [XK_Sys_Req] = KEY_SYSRQ,
+ [XK_Linefeed] = KEY_LINEFEED,
+ [XK_Home] = KEY_HOME,
+ [XK_Pause] = KEY_PAUSE,
+ [XK_F1] = KEY_F1,
+ [XK_F2] = KEY_F2,
+ [XK_F3] = KEY_F3,
+ [XK_F4] = KEY_F4,
+ [XK_F5] = KEY_F5,
+ [XK_F6] = KEY_F6,
+ [XK_F7] = KEY_F7,
+ [XK_F8] = KEY_F8,
+ [XK_F9] = KEY_F9,
+ [XK_F10] = KEY_F10,
+ [XK_F11] = KEY_F11,
+ [XK_F12] = KEY_F12,
+ [XK_Up] = KEY_UP,
+ [XK_Page_Up] = KEY_PAGEUP,
+ [XK_Left] = KEY_LEFT,
+ [XK_Right] = KEY_RIGHT,
+ [XK_End] = KEY_END,
+ [XK_Down] = KEY_DOWN,
+ [XK_Page_Down] = KEY_PAGEDOWN,
+ [XK_Insert] = KEY_INSERT,
+ [XK_colon] = KEY_SEMICOLON,
+ [XK_quotedbl] = KEY_APOSTROPHE,
+ [XK_less] = KEY_COMMA,
+ [XK_greater] = KEY_DOT,
+ [XK_question] = KEY_SLASH,
+ [XK_bar] = KEY_BACKSLASH,
+ [XK_asciitilde] = KEY_GRAVE,
+ [XK_exclam] = KEY_1,
+ [XK_at] = KEY_2,
+ [XK_numbersign] = KEY_3,
+ [XK_dollar] = KEY_4,
+ [XK_percent] = KEY_5,
+ [XK_asciicircum] = KEY_6,
+ [XK_ampersand] = KEY_7,
+ [XK_asterisk] = KEY_8,
+ [XK_parenleft] = KEY_9,
+ [XK_parenright] = KEY_0,
+ [XK_underscore] = KEY_MINUS,
+ [XK_plus] = KEY_EQUAL,
+};
+
+static void on_kbd_event(rfbBool down, rfbKeySym keycode, rfbClientPtr cl)
+{
+ /*
+ * We need to map to the key's Linux input layer keycode.
+ * Unfortunately, we don't get the key here, only the
+ * rfbKeySym, which is what the key is mapped to. Mapping
+ * back to the key is impossible in general, even when you
+ * know the keymap. For instance, the standard German keymap
+ * maps both KEY_COMMA and KEY_102ND to XK_less. We simply
+ * assume standard US layout. This sucks.
+ */
+ rfbScreenInfoPtr server = cl->screen;
+ struct xenfb *xenfb = server->screenData;
+ if (keycode >= sizeof(xk2linux) / sizeof(*xk2linux))
+ return;
+ if (xk2linux[keycode] == 0)
+ return;
+ if (xenfb_send_key(xenfb, down, xk2linux[keycode]) < 0)
+ fprintf(stderr, "Key %d %s lost (%s)\n",
+ xk2linux[keycode], down ? "down" : "up",
+ strerror(errno));
+}
+
+static void on_ptr_event(int buttonMask, int x, int y, rfbClientPtr cl)
+{
+ /* initial pointer state: at (0,0), buttons up */
+ static int last_x, last_y, last_button;
+ rfbScreenInfoPtr server = cl->screen;
+ struct xenfb *xenfb = server->screenData;
+ int i, last_down, down, ret;
+
+ for (i = 0; i < 8; i++) {
+ last_down = last_button & (1 << i);
+ down = buttonMask & (1 << i);
+ if (down == last_down)
+ continue;
+ /* FIXME this assumes buttons are numbered the same; verify they are */
+ if (xenfb_send_key(xenfb, down != 0, BTN_MOUSE + i) < 0)
+ fprintf(stderr, "Button %d %s lost (%s)\n",
+ i, down ? "down" : "up", strerror(errno));
+ }
+
+ if (x != last_x || y != last_y) {
+ if (xenfb->abs_pointer_wanted)
+ ret = xenfb_send_position(xenfb, x, y);
+ else
+ ret = xenfb_send_motion(xenfb, x - last_x, y - last_y);
+ if (ret < 0)
+ fprintf(stderr, "Pointer to %d,%d lost (%s)\n",
+ x, y, strerror(errno));
+ }
+
+ last_button = buttonMask;
+ last_x = x;
+ last_y = y;
+}
+
+static void xenstore_write_vncport(int port, int domid)
+{
+ char *buf = NULL, *path;
+ char portstr[10];
+ struct xs_handle *xsh = NULL;
+
+ xsh = xs_daemon_open();
+ if (xsh == NULL)
+ return;
+
+ path = xs_get_domain_path(xsh, domid);
+ if (path == NULL) {
+ fprintf(stderr, "Can't get domain path (%s)\n",
+ strerror(errno));
+ goto out;
+ }
+
+ if (asprintf(&buf, "%s/console/vnc-port", path) == -1) {
+ fprintf(stderr, "Can't make vncport path\n");
+ goto out;
+ }
+
+ if (snprintf(portstr, sizeof(portstr), "%d", port) == -1) {
+ fprintf(stderr, "Can't make vncport value\n");
+ goto out;
+ }
+
+ if (!xs_write(xsh, XBT_NULL, buf, portstr, strlen(portstr)))
+ fprintf(stderr, "Can't set vncport (%s)\n",
+ strerror(errno));
+
+ out:
+ free(buf);
+}
+
+
+static void vnc_update(struct xenfb *xenfb, int x, int y, int w, int h)
+{
+ rfbScreenInfoPtr server = xenfb->user_data;
+ rfbMarkRectAsModified(server, x, y, x + w, y + h);
+}
+
+static struct option options[] = {
+ { "domid", 1, NULL, 'd' },
+ { "vncport", 1, NULL, 'p' },
+ { "title", 1, NULL, 't' },
+ { "unused", 0, NULL, 'u' },
+ { "listen", 1, NULL, 'l' },
+};
+
+int main(int argc, char **argv)
+{
+ rfbScreenInfoPtr server;
+ char *fake_argv[7] = { "vncfb", "-rfbport", "5901",
+ "-desktop", "xen-vncfb",
+ "-listen", "127.0.0.1" };
+ int fake_argc = sizeof(fake_argv) / sizeof(fake_argv[0]);
+ int domid = -1, port = -1;
+ char *title = NULL;
+ char *listen = NULL;
+ bool unused = false;
+ int opt;
+ struct xenfb *xenfb;
+ fd_set readfds;
+ int nfds;
+ char portstr[10];
+ char *endp;
+
+ while ((opt = getopt_long(argc, argv, "d:p:t:u", options,
+ NULL)) != -1) {
+ switch (opt) {
+ case 'd':
+ errno = 0;
+ domid = strtol(optarg, &endp, 10);
+ if (endp == optarg || *endp || errno) {
+ fprintf(stderr, "Invalid domain id specified\n");
+ exit(1);
+ }
+ break;
+ case 'p':
+ errno = 0;
+ port = strtol(optarg, &endp, 10);
+ if (endp == optarg || *endp || errno) {
+ fprintf(stderr, "Invalid port specified\n");
+ exit(1);
+ }
+ break;
+ case 't':
+ title = strdup(optarg);
+ break;
+ case 'u':
+ unused = true;
+ break;
+ case 'l':
+ listen = strdup(optarg);
+ break;
+ }
+ }
+ if (optind != argc) {
+ fprintf(stderr, "Invalid options!\n");
+ exit(1);
+ }
+ if (domid <= 0) {
+ fprintf(stderr, "Domain ID must be specified!\n");
+ exit(1);
+ }
+
+ if (port <= 0)
+ port = 5900 + domid;
+ if (snprintf(portstr, sizeof(portstr), "%d", port) == -1) {
+ fprintf(stderr, "Invalid port specified\n");
+ exit(1);
+ }
+
+ fake_argv[2] = portstr;
+
+ if (title != NULL)
+ fake_argv[4] = title;
+
+ if (listen != NULL)
+ fake_argv[6] = listen;
+
+ signal(SIGPIPE, SIG_IGN);
+
+ xenfb = xenfb_new();
+ if (xenfb == NULL) {
+ fprintf(stderr, "Could not create framebuffer (%s)\n",
+ strerror(errno));
+ exit(1);
+ }
+
+ if (xenfb_attach_dom(xenfb, domid) < 0) {
+ fprintf(stderr, "Could not connect to domain (%s)\n",
+ strerror(errno));
+ exit(1);
+ }
+
+ server = rfbGetScreen(&fake_argc, fake_argv,
+ xenfb->width, xenfb->height,
+ 8, 3, xenfb->depth / 8);
+ if (server == NULL) {
+ fprintf(stderr, "Could not create VNC server\n");
+ exit(1);
+ }
+
+ xenfb->user_data = server;
+ xenfb->update = vnc_update;
+
+ if (unused)
+ server->autoPort = true;
+
+ server->serverFormat.redShift = 16;
+ server->serverFormat.greenShift = 8;
+ server->serverFormat.blueShift = 0;
+ server->kbdAddEvent = on_kbd_event;
+ server->ptrAddEvent = on_ptr_event;
+ server->frameBuffer = xenfb->pixels;
+ server->screenData = xenfb;
+ server->cursor = NULL;
+ rfbInitServer(server);
+
+ rfbRunEventLoop(server, -1, true);
+
+ xenstore_write_vncport(server->port, domid);
+
+ for (;;) {
+ FD_ZERO(&readfds);
+ nfds = xenfb_select_fds(xenfb, &readfds);
+
+ if (select(nfds, &readfds, NULL, NULL, NULL) < 0) {
+ if (errno == EINTR)
+ continue;
+ fprintf(stderr,
+ "Can't select() on event channel (%s)\n",
+ strerror(errno));
+ break;
+ }
+
+ xenfb_poll(xenfb, &readfds);
+ }
+
+ rfbScreenCleanup(server);
+ xenfb_delete(xenfb);
+
+ return 0;
+}
704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810
/*
 *  yosys -- Yosys Open SYnthesis Suite
 *
 *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
 *
 *  Permission to use, copy, modify, and/or distribute this software for any
 *  purpose with or without fee is hereby granted, provided that the above
 *  copyright notice and this permission notice appear in all copies.
 *
 *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */

#include "kernel/yosys.h"
#include "kernel/sigtools.h"
#include "kernel/utils.h"

USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN

struct HierDirtyFlags;

static pool<string> reserved_cids;
static dict<IdString, string> id2cid;

static string cid(IdString id)
{
	if (id2cid.count(id) == 0)
	{
		string s = id.str();
		if (GetSize(s) < 2) log_abort();

		if (s[0] == '\\')
			s = s.substr(1);

		if ('0' <= s[0] && s[0] <= '9') {
			s = "_" + s;
		}

		for (int i = 0; i < GetSize(s); i++) {
			if ('0' <= s[i] && s[i] <= '9') continue;
			if ('A' <= s[i] && s[i] <= 'Z') continue;
			if ('a' <= s[i] && s[i] <= 'z') continue;
			s[i] = '_';
		}

		while (reserved_cids.count(s))
			s += "_";

		reserved_cids.insert(s);
		id2cid[id] = s;
	}

	return id2cid.at(id);
}

struct HierDirtyFlags
{
	int dirty;
	Module *module;
	IdString hiername;
	HierDirtyFlags *parent;
	pool<SigBit> dirty_bits;
	pool<Cell*> dirty_cells;
	pool<SigBit> sticky_dirty_bits;
	dict<IdString, HierDirtyFlags*> children;
	string prefix, log_prefix;

	HierDirtyFlags(Module *module, IdString hiername, HierDirtyFlags *parent, const string &prefix, const string &log_prefix) :
			dirty(0), module(module), hiername(hiername), parent(parent), prefix(prefix), log_prefix(log_prefix)
	{
		for (Cell *cell : module->cells()) {
			Module *mod = module->design->module(cell->type);
			if (mod) children[cell->name] = new HierDirtyFlags(mod, cell->name, this,
					prefix + cid(cell->name) + ".", log_prefix + "." + prefix + log_id(cell->name));
		}
	}

	~HierDirtyFlags()
	{
		for (auto &child : children)
			delete child.second;
	}

	void set_dirty(SigBit bit)
	{
		if (dirty_bits.count(bit))
			return;

		dirty_bits.insert(bit);
		sticky_dirty_bits.insert(bit);

		HierDirtyFlags *p = this;
		while (p != nullptr) {
			p->dirty++;
			p = p->parent;
		}
	}

	void unset_dirty(SigBit bit)
	{
		if (dirty_bits.count(bit) == 0)
			return;

		dirty_bits.erase(bit);

		HierDirtyFlags *p = this;
		while (p != nullptr) {
			p->dirty--;
			log_assert(p->dirty >= 0);
			p = p->parent;
		}
	}

	void set_dirty(Cell *cell)
	{
		if (dirty_cells.count(cell))
			return;

		dirty_cells.insert(cell);

		HierDirtyFlags *p = this;
		while (p != nullptr) {
			p->dirty++;
			p = p->parent;
		}
	}

	void unset_dirty(Cell *cell)
	{
		if (dirty_cells.count(cell) == 0)
			return;

		dirty_cells.erase(cell);

		HierDirtyFlags *p = this;
		while (p != nullptr) {
			p->dirty--;
			log_assert(p->dirty >= 0);
			p = p->parent;
		}
	}
};

struct SimplecWorker
{
	bool verbose = false;
	int max_uintsize = 32;

	Design *design;
	dict<Module*, SigMap> sigmaps;

	vector<string> signal_declarations;
	pool<int> generated_sigtypes;

	vector<string> util_declarations;
	pool<string> generated_utils;

	vector<string> struct_declarations;
	pool<IdString> generated_structs;

	vector<string> funct_declarations;

	dict<Module*, dict<SigBit, pool<tuple<Cell*, IdString, int>>>> bit2cell;
	dict<Module*, dict<SigBit, pool<SigBit>>> bit2output;
	dict<Module*, pool<SigBit>> driven_bits;

	dict<Cell*, int> topoidx;

	pool<string> activated_cells;
	pool<string> reactivated_cells;

	SimplecWorker(Design *design) : design(design)
	{
	}

	string sigtype(int n)
	{
		string struct_name = stringf("signal%d_t", n);

		if (generated_sigtypes.count(n) == 0)
		{
			signal_declarations.push_back("");
			signal_declarations.push_back(stringf("#ifndef YOSYS_SIMPLEC_SIGNAL%d_T", n));
			signal_declarations.push_back(stringf("#define YOSYS_SIMPLEC_SIGNAL%d_T", n));
			signal_declarations.push_back(stringf("typedef struct {"));

			for (int k = 8; k <= max_uintsize; k = 2*k)
				if (n <= k && k <= max_uintsize) {
					signal_declarations.push_back(stringf("  uint%d_t value_%d_0 : %d;", k, n-1, n));
					goto end_struct;
				}

			for (int k = 0; k < n; k += max_uintsize) {
				int bits = std::min(max_uintsize, n-k);
				signal_declarations.push_back(stringf("  uint%d_t value_%d_%d : %d;", max_uintsize, k+bits-1, k, bits));
			}

		end_struct:
			signal_declarations.push_back(stringf("} signal%d_t;", n));
			signal_declarations.push_back(stringf("#endif"));
			generated_sigtypes.insert(n);
		}

		return struct_name;
	}

	void util_ifdef_guard(string s)
	{
		for (int i = 0; i < GetSize(s); i++)
			if ('a' <= s[i] && s[i] <= 'z')
				s[i] -= 'a' - 'A';

		util_declarations.push_back("");
		util_declarations.push_back(stringf("#ifndef %s", s.c_str()));
		util_declarations.push_back(stringf("#define %s", s.c_str()));
	}

	string util_get_bit(const string &signame, int n, int idx)
	{
		if (n == 1 && idx == 0)
			return signame + ".value_0_0";

		string util_name = stringf("yosys_simplec_get_bit_%d_of_%d", idx, n);

		if (generated_utils.count(util_name) == 0)
		{
			util_ifdef_guard(util_name);
			util_declarations.push_back(stringf("static inline bool %s(const %s *sig)", util_name.c_str(), sigtype(n).c_str()));
			util_declarations.push_back(stringf("{"));

			int word_idx = idx / max_uintsize, word_offset = idx % max_uintsize;
			string value_name = stringf("value_%d_%d", std::min(n-1, (word_idx+1)*max_uintsize-1), word_idx*max_uintsize);

			util_declarations.push_back(stringf("  return (sig->%s >> %d) & 1;", value_name.c_str(), word_offset));

			util_declarations.push_back(stringf("}"));
			util_declarations.push_back(stringf("#endif"));
			generated_utils.insert(util_name);
		}

		return stringf("%s(&%s)", util_name.c_str(), signame.c_str());
	}

	string util_set_bit(const string &signame, int n, int idx, const string &expr)
	{
		if (n == 1 && idx == 0)
			return stringf("  %s.value_0_0 = %s;", signame.c_str(), expr.c_str());

		string util_name = stringf("yosys_simplec_set_bit_%d_of_%d", idx, n);

		if (generated_utils.count(util_name) == 0)
		{
			util_ifdef_guard(util_name);
			util_declarations.push_back(stringf("static inline void %s(%s *sig, bool value)", util_name.c_str(), sigtype(n).c_str()));
			util_declarations.push_back(stringf("{"));

			int word_idx = idx / max_uintsize, word_offset = idx % max_uintsize;
			string value_name = stringf("value_%d_%d", std::min(n-1, (word_idx+1)*max_uintsize-1), word_idx*max_uintsize);

		#if 0
			util_declarations.push_back(stringf("  if (value)"));
			util_declarations.push_back(stringf("    sig->%s |= 1UL << %d;", value_name.c_str(), word_offset));
			util_declarations.push_back(stringf("  else"));
			util_declarations.push_back(stringf("    sig->%s &= ~(1UL << %d);", value_name.c_str(), word_offset));
		#else
			util_declarations.push_back(stringf("    sig->%s = (sig->%s & ~((uint%d_t)1 << %d)) | ((uint%d_t)value << %d);",
					value_name.c_str(), value_name.c_str(), max_uintsize, word_offset, max_uintsize, word_offset));
		#endif

			util_declarations.push_back(stringf("}"));
			util_declarations.push_back(stringf("#endif"));
			generated_utils.insert(util_name);
		}

		return stringf("  %s(&%s, %s);", util_name.c_str(), signame.c_str(), expr.c_str());
	}

	void create_module_struct(Module *mod)
	{
		if (generated_structs.count(mod->name))
			return;

		generated_structs.insert(mod->name);
		sigmaps[mod].set(mod);

		for (Wire *w : mod->wires())
		{
			if (w->port_output)
				for (auto bit : SigSpec(w))
					bit2output[mod][sigmaps.at(mod)(bit)].insert(bit);
		}

		for (Cell *c : mod->cells())
		{
			for (auto &conn : c->connections())
			{
				if (!c->input(conn.first)) {
					for (auto bit : sigmaps.at(mod)(conn.second))
						driven_bits[mod].insert(bit);
					continue;
				}

				int idx = 0;
				for (auto bit : sigmaps.at(mod)(conn.second))
					bit2cell[mod][bit].insert(tuple<Cell*, IdString, int>(c, conn.first, idx++));
			}

			if (design->module(c->type))
				create_module_struct(design->module(c->type));
		}

		TopoSort<IdString> topo;

		for (Cell *c : mod->cells())
		{
			topo.node(c->name);

			for (auto &conn : c->connections())
			{
				if (!c->input(conn.first))
					continue;

				for (auto bit : sigmaps.at(mod)(conn.second))
				for (auto &it : bit2cell[mod][bit])
					topo.edge(c->name, std::get<0>(it)->name);
			}
		}

		topo.analyze_loops = false;
		topo.sort();

		for (int i = 0; i < GetSize(topo.sorted); i++)
			topoidx[mod->cell(topo.sorted[i])] = i;

		string ifdef_name = stringf("yosys_simplec_%s_state_t", cid(mod->name).c_str());

		for (int i = 0; i < GetSize(ifdef_name); i++)
			if ('a' <= ifdef_name[i] && ifdef_name[i] <= 'z')
				ifdef_name[i] -= 'a' - 'A';

		struct_declarations.push_back("");
		struct_declarations.push_back(stringf("#ifndef %s", ifdef_name.c_str()));
		struct_declarations.push_back(stringf("#define %s", ifdef_name.c_str()));
		struct_declarations.push_back(stringf("struct %s_state_t", cid(mod->name).c_str()));
		struct_declarations.push_back("{");

		struct_declarations.push_back("  // Input Ports");
		for (Wire *w : mod->wires())
			if (w->port_input)
				struct_declarations.push_back(stringf("  %s %s; // %s", sigtype(w->width).c_str(), cid(w->name).c_str(), log_id(w)));

		struct_declarations.push_back("");
		struct_declarations.push_back("  // Output Ports");
		for (Wire *w : mod->wires())
			if (!w->port_input && w->port_output)
				struct_declarations.push_back(stringf("  %s %s; // %s", sigtype(w->width).c_str(), cid(w->name).c_str(), log_id(w)));

		struct_declarations.push_back("");
		struct_declarations.push_back("  // Internal Wires");
		for (Wire *w : mod->wires())
			if (!w->port_input && !w->port_output)
				struct_declarations.push_back(stringf("  %s %s; // %s", sigtype(w->width).c_str(), cid(w->name).c_str(), log_id(w)));

		for (Cell *c : mod->cells())
			if (design->module(c->type))
				struct_declarations.push_back(stringf("  struct %s_state_t %s; // %s", cid(c->type).c_str(), cid(c->name).c_str(), log_id(c)));

		struct_declarations.push_back(stringf("};"));
		struct_declarations.push_back("#endif");
	}

	void eval_cell(HierDirtyFlags *work, Cell *cell)
	{
		if (cell->type.in("$_BUF_", "$_NOT_"))
		{
			SigBit a = sigmaps.at(work->module)(cell->getPort("\\A"));
			SigBit y = sigmaps.at(work->module)(cell->getPort("\\Y"));

			string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
			string expr;

			if (cell->type == "$_BUF_")  expr = a_expr;
			if (cell->type == "$_NOT_")  expr = "!" + a_expr;

			log_assert(y.wire);
			funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) +
					stringf(" // %s (%s)", log_id(cell), log_id(cell->type)));

			work->set_dirty(y);
			return;
		}

		if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_"))
		{
			SigBit a = sigmaps.at(work->module)(cell->getPort("\\A"));
			SigBit b = sigmaps.at(work->module)(cell->getPort("\\B"));
			SigBit y = sigmaps.at(work->module)(cell->getPort("\\Y"));

			string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
			string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0";
			string expr;

			if (cell->type == "$_AND_")    expr = stringf("%s & %s",    a_expr.c_str(), b_expr.c_str());
			if (cell->type == "$_NAND_")   expr = stringf("!(%s & %s)", a_expr.c_str(), b_expr.c_str());
			if (cell->type == "$_OR_")     expr = stringf("%s | %s",    a_expr.c_str(), b_expr.c_str());
			if (cell->type == "$_NOR_")    expr = stringf("!(%s | %s)", a_expr.c_str(), b_expr.c_str());
			if (cell->type == "$_XOR_")    expr = stringf("%s ^ %s",    a_expr.c_str(), b_expr.c_str());
			if (cell->type == "$_XNOR_")   expr = stringf("!(%s ^ %s)", a_expr.c_str(), b_expr.c_str());
			if (cell->type == "$_ANDNOT_") expr = stringf("%s & (!%s)", a_expr.c_str(), b_expr.c_str());
			if (cell->type == "$_ORNOT_")  expr = stringf("%s | (!%s)", a_expr.c_str(), b_expr.c_str());

			log_assert(y.wire);
			funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) +
					stringf(" // %s (%s)", log_id(cell), log_id(cell->type)));

			work->set_dirty(y);
			return;
		}

		if (cell->type.in("$_AOI3_", "$_OAI3_"))
		{
			SigBit a = sigmaps.at(work->module)(cell->getPort("\\A"));
			SigBit b = sigmaps.at(work->module)(cell->getPort("\\B"));
			SigBit c = sigmaps.at(work->module)(cell->getPort("\\C"));
			SigBit y = sigmaps.at(work->module)(cell->getPort("\\Y"));

			string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
			string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0";
			string c_expr = c.wire ? util_get_bit(work->prefix + cid(c.wire->name), c.wire->width, c.offset) : c.data ? "1" : "0";
			string expr;

			if (cell->type == "$_AOI3_") expr = stringf("!((%s & %s) | %s)", a_expr.c_str(), b_expr.c_str(), c_expr.c_str());
			if (cell->type == "$_OAI3_") expr = stringf("!((%s | %s) & %s)", a_expr.c_str(), b_expr.c_str(), c_expr.c_str());

			log_assert(y.wire);
			funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) +
					stringf(" // %s (%s)", log_id(cell), log_id(cell->type)));

			work->set_dirty(y);
			return;
		}

		if (cell->type.in("$_AOI4_", "$_OAI4_"))
		{
			SigBit a = sigmaps.at(work->module)(cell->getPort("\\A"));
			SigBit b = sigmaps.at(work->module)(cell->getPort("\\B"));
			SigBit c = sigmaps.at(work->module)(cell->getPort("\\C"));
			SigBit d = sigmaps.at(work->module)(cell->getPort("\\D"));
			SigBit y = sigmaps.at(work->module)(cell->getPort("\\Y"));

			string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
			string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0";
			string c_expr = c.wire ? util_get_bit(work->prefix + cid(c.wire->name), c.wire->width, c.offset) : c.data ? "1" : "0";
			string d_expr = d.wire ? util_get_bit(work->prefix + cid(d.wire->name), d.wire->width, d.offset) : d.data ? "1" : "0";
			string expr;

			if (cell->type == "$_AOI4_") expr = stringf("!((%s & %s) | (%s & %s))", a_expr.c_str(), b_expr.c_str(), c_expr.c_str(), d_expr.c_str());
			if (cell->type == "$_OAI4_") expr = stringf("!((%s | %s) & (%s | %s))", a_expr.c_str(), b_expr.c_str(), c_expr.c_str(), d_expr.c_str());

			log_assert(y.wire);
			funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) +
					stringf(" // %s (%s)", log_id(cell), log_id(cell->type)));

			work->set_dirty(y);
			return;
		}

		if (cell->type == "$_MUX_")
		{
			SigBit a = sigmaps.at(work->module)(cell->getPort("\\A"));
			SigBit b = sigmaps.at(work->module)(cell->getPort("\\B"));
			SigBit s = sigmaps.at(work->module)(cell->getPort("\\S"));
			SigBit y = sigmaps.at(work->module)(cell->getPort("\\Y"));

			string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
			string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0";
			string s_expr = s.wire ? util_get_bit(work->prefix + cid(s.wire->name), s.wire->width, s.offset) : s.data ? "1" : "0";

			// casts to bool are a workaround for CBMC bug (https://github.com/diffblue/cbmc/issues/933)
			string expr = stringf("%s ? (bool)%s : (bool)%s", s_expr.c_str(), b_expr.c_str(), a_expr.c_str());

			log_assert(y.wire);
			funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) +
					stringf(" // %s (%s)", log_id(cell), log_id(cell->type)));

			work->set_dirty(y);
			return;
		}

		log_error("No C model for %s available at the moment (FIXME).\n", log_id(cell->type));
	}

	void eval_dirty(HierDirtyFlags *work)
	{
		while (work->dirty)
		{
			if (verbose && (!work->dirty_bits.empty() || !work->dirty_cells.empty()))
				log("  In %s:\n", work->log_prefix.c_str());

			while (!work->dirty_bits.empty() || !work->dirty_cells.empty())
			{
				if (!work->dirty_bits.empty())
				{
					SigSpec dirtysig(work->dirty_bits);
					dirtysig.sort_and_unify();

					for (SigChunk chunk : dirtysig.chunks()) {
						if (chunk.wire == nullptr)
							continue;
						if (verbose)
							log("    Propagating %s.%s[%d:%d].\n", work->log_prefix.c_str(), log_id(chunk.wire), chunk.offset+chunk.width-1, chunk.offset);
						funct_declarations.push_back(stringf("  // Updated signal in %s: %s", work->log_prefix.c_str(), log_signal(chunk)));
					}

					for (SigBit bit : dirtysig)
					{
						if (bit2output[work->module].count(bit) && work->parent)
							for (auto outbit : bit2output[work->module][bit])
							{
								Module *parent_mod = work->parent->module;
								Cell *parent_cell = parent_mod->cell(work->hiername);

								IdString port_name = outbit.wire->name;
								int port_offset = outbit.offset;
								SigBit parent_bit = sigmaps.at(parent_mod)(parent_cell->getPort(port_name)[port_offset]);

								log_assert(bit.wire && parent_bit.wire);
								funct_declarations.push_back(util_set_bit(work->parent->prefix + cid(parent_bit.wire->name), parent_bit.wire->width, parent_bit.offset,
										util_get_bit(work->prefix + cid(bit.wire->name), bit.wire->width, bit.offset)));
								work->parent->set_dirty(parent_bit);

								if (verbose)
									log("      Propagating %s.%s[%d] -> %s.%s[%d].\n", work->log_prefix.c_str(), log_id(bit.wire), bit.offset,
											work->parent->log_prefix.c_str(), log_id(parent_bit.wire), parent_bit.offset);
							}

						for (auto &port : bit2cell[work->module][bit])
						{
							if (work->children.count(std::get<0>(port)->name))
							{
								HierDirtyFlags *child = work->children.at(std::get<0>(port)->name);
								SigBit child_bit = sigmaps.at(child->module)(SigBit(child->module->wire(std::get<1>(port)), std::get<2>(port)));
								log_assert(bit.wire && child_bit.wire);

								funct_declarations.push_back(util_set_bit(work->prefix + cid(child->hiername) + "." + cid(child_bit.wire->name),
										child_bit.wire->width, child_bit.offset, util_get_bit(work->prefix + cid(bit.wire->name), bit.wire->width, bit.offset)));
								child->set_dirty(child_bit);

								if (verbose)
									log("      Propagating %s.%s[%d] -> %s.%s.%s[%d].\n", work->log_prefix.c_str(), log_id(bit.wire), bit.offset,
											work->log_prefix.c_str(), log_id(std::get<0>(port)), log_id(child_bit.wire), child_bit.offset);
							} else {
								if (verbose)
									log("      Marking cell %s.%s (via %s.%s[%d]).\n", work->log_prefix.c_str(), log_id(std::get<0>(port)),
											work->log_prefix.c_str(), log_id(bit.wire), bit.offset);
								work->set_dirty(std::get<0>(port));
							}
						}
						work->unset_dirty(bit);
					}
				}

				if (!work->dirty_cells.empty())
				{
					Cell *cell = nullptr;
					for (auto c : work->dirty_cells)
						if (cell == nullptr || topoidx.at(cell) < topoidx.at(c))
							cell = c;

					string hiername = work->log_prefix + "." + log_id(cell);

					if (verbose)
						log("    Evaluating %s (%s, best of %d).\n", hiername.c_str(), log_id(cell->type), GetSize(work->dirty_cells));

					if (activated_cells.count(hiername))
						reactivated_cells.insert(hiername);
					activated_cells.insert(hiername);

					eval_cell(work, cell);
					work->unset_dirty(cell);
				}
			}

			for (auto &child : work->children)
				eval_dirty(child.second);
		}
	}

	void eval_sticky_dirty(HierDirtyFlags *work)
	{
		Module *mod = work->module;

		for (Wire *w : mod->wires())
		for (SigBit bit : SigSpec(w))
		{
			SigBit canonical_bit = sigmaps.at(mod)(bit);

			if (canonical_bit == bit)
				continue;

			if (work->sticky_dirty_bits.count(canonical_bit) == 0)
				continue;

			if (bit.wire == nullptr || canonical_bit.wire == nullptr)
				continue;

			funct_declarations.push_back(util_set_bit(work->prefix + cid(bit.wire->name), bit.wire->width, bit.offset,
					util_get_bit(work->prefix + cid(canonical_bit.wire->name), canonical_bit.wire->width, canonical_bit.offset).c_str()));

			if (verbose)
				log("  Propagating alias %s.%s[%d] -> %s.%s[%d].\n",
						work->log_prefix.c_str(), log_id(canonical_bit.wire), canonical_bit.offset,
						work->log_prefix.c_str(), log_id(bit.wire), bit.offset);
		}

		work->sticky_dirty_bits.clear();

		for (auto &child : work->children)
			eval_sticky_dirty(child.second);
	}

	void make_func(HierDirtyFlags *work, const string &func_name, const vector<string> &preamble)
	{
		log("Generating function %s():\n", func_name.c_str());

		activated_cells.clear();
		reactivated_cells.clear();

		funct_declarations.push_back("");
		funct_declarations.push_back(stringf("static void %s(struct %s_state_t *state)", func_name.c_str(), cid(work->module->name).c_str()));
		funct_declarations.push_back("{");
		for (auto &line : preamble)
			funct_declarations.push_back(line);
		eval_dirty(work);
		eval_sticky_dirty(work);
		funct_declarations.push_back("}");

		log("  Activated %d cells (%d activated more than once).\n", GetSize(activated_cells), GetSize(reactivated_cells));
	}

	void eval_init(HierDirtyFlags *work, vector<string> &preamble)
	{
		Module *module = work->module;

		for (Wire *w : module->wires())
		{
			if (w->attributes.count("\\init"))
			{
				SigSpec sig = sigmaps.at(module)(w);
				Const val = w->attributes.at("\\init");
				val.bits.resize(GetSize(sig), State::Sx);

				for (int i = 0; i < GetSize(sig); i++)
					if (val[i] == State::S0 || val[i] == State::S1) {
						SigBit bit = sig[i];
						preamble.push_back(util_set_bit(work->prefix + cid(bit.wire->name), bit.wire->width, bit.offset, val == State::S1 ? "true" : "false"));
						work->set_dirty(bit);
					}
			}

			for (SigBit bit : SigSpec(w))
			{
				SigBit val = sigmaps.at(module)(bit);

				if (val == State::S0 || val == State::S1)
					preamble.push_back(util_set_bit(work->prefix + cid(bit.wire->name), bit.wire->width, bit.offset, val == State::S1 ? "true" : "false"));

				if (driven_bits.at(module).count(val) == 0)
					work->set_dirty(val);
			}
		}

		work->set_dirty(State::S0);
		work->set_dirty(State::S1);

		for (auto &child : work->children)
			eval_init(child.second, preamble);
	}

	void make_init_func(HierDirtyFlags *work)
	{
		vector<string> preamble;
		eval_init(work, preamble);
		make_func(work, cid(work->module->name) + "_init", preamble);
	}

	void make_eval_func(HierDirtyFlags *work)
	{
		Module *mod = work->module;
		vector<string> preamble;

		for (Wire *w : mod->wires()) {
			if (w->port_input)
				for (SigBit bit : sigmaps.at(mod)(w))
					work->set_dirty(bit);
		}

		make_func(work, cid(work->module->name) + "_eval", preamble);
	}

	void make_tick_func(HierDirtyFlags* /* work */)
	{
		// FIXME
	}

	void run(Module *mod)
	{
		create_module_struct(mod);

		HierDirtyFlags work(mod, IdString(), nullptr, "state->", log_id(mod->name));

		make_init_func(&work);
		make_eval_func(&work);
		make_tick_func(&work);
	}

	void write(std::ostream &f)
	{
		f << "#include <stdint.h>" << std::endl;
		f << "#include <stdbool.h>" << std::endl;

		for (auto &line : signal_declarations)
			f << line << std::endl;

		for (auto &line : util_declarations)
			f << line << std::endl;

		for (auto &line : struct_declarations)
			f << line << std::endl;

		for (auto &line : funct_declarations)
			f << line << std::endl;
	}
};

struct SimplecBackend : public Backend {
	SimplecBackend() : Backend("simplec", "convert design to simple C code") { }
	void help() YS_OVERRIDE
	{
		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
		log("\n");
		log("    write_simplec [options] [filename]\n");
		log("\n");
		log("Write simple C code for simulating the design. The C code writen can be used to\n");
		log("simulate the design in a C environment, but the purpose of this command is to\n");
		log("generate code that works well with C-based formal verification.\n");
		log("\n");
		log("    -verbose\n");
		log("        this will print the recursive walk used to export the modules.\n");
		log("\n");
		log("    -i8, -i16, -i32, -i64\n");
		log("        set the maximum integer bit width to use in the generated code.\n");
		log("\n");
		log("THIS COMMAND IS UNDER CONSTRUCTION\n");
		log("\n");
	}
	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
	{
		reserved_cids.clear();
		id2cid.clear();

		SimplecWorker worker(design);

		log_header(design, "Executing SIMPLEC backend.\n");

		size_t argidx;
		for (argidx = 1; argidx < args.size(); argidx++)
		{
			if (args[argidx] == "-verbose") {
				worker.verbose = true;
				continue;
			}
			if (args[argidx] == "-i8") {
				worker.max_uintsize = 8;
				continue;
			}
			if (args[argidx] == "-i16") {
				worker.max_uintsize = 16;
				continue;
			}
			if (args[argidx] == "-i32") {
				worker.max_uintsize = 32;
				continue;
			}
			if (args[argidx] == "-i64") {
				worker.max_uintsize = 64;
				continue;
			}
			break;
		}
		extra_args(f, filename, args, argidx);

		Module *topmod = design->top_module();

		if (topmod == nullptr)
			log_error("Current design has no top module.\n");

		worker.run(topmod);
		worker.write(*f);
	}
} SimplecBackend;

PRIVATE_NAMESPACE_END