From e41c0be293502619b6a072fb9bcd8bbd8694b86a Mon Sep 17 00:00:00 2001 From: Maximilian Hils Date: Thu, 27 Nov 2014 01:40:26 +0100 Subject: format code --- web/src/js/actions.js | 4 +- web/src/js/components/eventlog.jsx.js | 24 +++++----- web/src/js/components/flowtable-columns.jsx.js | 50 +++++++++++---------- web/src/js/components/flowtable.jsx.js | 56 ++++++++++++----------- web/src/js/components/footer.jsx.js | 2 +- web/src/js/components/header.jsx.js | 23 +++++----- web/src/js/components/utils.jsx.js | 52 ++++++++++----------- web/src/js/connection.js | 12 ++--- web/src/js/dispatcher.js | 2 +- web/src/js/stores/eventlogstore.js | 62 +++++++++++++------------- web/src/js/stores/flowstore.js | 10 ++--- web/src/js/utils.js | 4 +- 12 files changed, 153 insertions(+), 148 deletions(-) (limited to 'web/src/js') diff --git a/web/src/js/actions.js b/web/src/js/actions.js index 9211403f..3e7510ad 100644 --- a/web/src/js/actions.js +++ b/web/src/js/actions.js @@ -25,13 +25,13 @@ var SettingsActions = { var event_id = 0; var EventLogActions = { - add_event: function(message){ + add_event: function (message) { AppDispatcher.dispatchViewAction({ type: ActionTypes.ADD_EVENT, data: { message: message, level: "web", - id: "viewAction-"+event_id++ + id: "viewAction-" + event_id++ } }); } diff --git a/web/src/js/components/eventlog.jsx.js b/web/src/js/components/eventlog.jsx.js index 34d84cdf..4d61a39c 100644 --- a/web/src/js/components/eventlog.jsx.js +++ b/web/src/js/components/eventlog.jsx.js @@ -1,8 +1,8 @@ var LogMessage = React.createClass({ - render: function(){ + render: function () { var entry = this.props.entry; var indicator; - switch(entry.level){ + switch (entry.level) { case "web": indicator = ; break; @@ -18,13 +18,13 @@ var LogMessage = React.createClass({ ); }, - shouldComponentUpdate: function(){ + shouldComponentUpdate: function () { return false; // log entries are immutable. } }); var EventLogContents = React.createClass({ - mixins:[AutoScrollMixin], + mixins: [AutoScrollMixin], getInitialState: function () { return { log: [] @@ -44,8 +44,8 @@ var EventLogContents = React.createClass({ }); }, render: function () { - var messages = this.state.log.map(function(row) { - if(!this.props.filter[row.level]){ + var messages = this.state.log.map(function (row) { + if (!this.props.filter[row.level]) { return null; } return ; @@ -55,11 +55,11 @@ var EventLogContents = React.createClass({ }); var ToggleFilter = React.createClass({ - toggle: function(e){ + toggle: function (e) { e.preventDefault(); return this.props.toggleLevel(this.props.name); }, - render: function(){ + render: function () { var className = "label "; if (this.props.active) { className += "label-primary"; @@ -74,11 +74,11 @@ var ToggleFilter = React.createClass({ {this.props.name} ); - } + } }); var EventLog = React.createClass({ - getInitialState: function(){ + getInitialState: function () { return { filter: { "debug": false, @@ -92,7 +92,7 @@ var EventLog = React.createClass({ showEventLog: false }); }, - toggleLevel: function(level){ + toggleLevel: function (level) { var filter = this.state.filter; filter[level] = !filter[level]; this.setState({filter: filter}); @@ -101,7 +101,7 @@ var EventLog = React.createClass({ return (
- Eventlog + Eventlog
diff --git a/web/src/js/components/flowtable-columns.jsx.js b/web/src/js/components/flowtable-columns.jsx.js index 8a44c072..1aa256c4 100644 --- a/web/src/js/components/flowtable-columns.jsx.js +++ b/web/src/js/components/flowtable-columns.jsx.js @@ -1,14 +1,14 @@ var TLSColumn = React.createClass({ statics: { - renderTitle: function(){ + renderTitle: function () { return ; } }, - render: function(){ + render: function () { var flow = this.props.flow; var ssl = (flow.request.scheme == "https"); var classes; - if(ssl){ + if (ssl) { classes = "col-tls col-tls-https"; } else { classes = "col-tls col-tls-http"; @@ -20,23 +20,23 @@ var TLSColumn = React.createClass({ var IconColumn = React.createClass({ statics: { - renderTitle: function(){ + renderTitle: function () { return ; } }, - render: function(){ + render: function () { var flow = this.props.flow; var icon; - if(flow.response){ + if (flow.response) { var contentType = ResponseUtils.getContentType(flow.response); //TODO: We should assign a type to the flow somewhere else. - if(flow.response.code == 304) { + if (flow.response.code == 304) { icon = "resource-icon-not-modified"; - } else if(300 <= flow.response.code && flow.response.code < 400) { + } else if (300 <= flow.response.code && flow.response.code < 400) { icon = "resource-icon-redirect"; - } else if(contentType && contentType.indexOf("image") >= 0) { + } else if (contentType && contentType.indexOf("image") >= 0) { icon = "resource-icon-image"; } else if (contentType && contentType.indexOf("javascript") >= 0) { icon = "resource-icon-js"; @@ -46,23 +46,25 @@ var IconColumn = React.createClass({ icon = "resource-icon-document"; } } - if(!icon){ + if (!icon) { icon = "resource-icon-plain"; } icon += " resource-icon"; - return
; + return +
+ ; } }); var PathColumn = React.createClass({ statics: { - renderTitle: function(){ + renderTitle: function () { return Path; } }, - render: function(){ + render: function () { var flow = this.props.flow; return {flow.request.scheme + "://" + flow.request.host + flow.request.path}; } @@ -71,11 +73,11 @@ var PathColumn = React.createClass({ var MethodColumn = React.createClass({ statics: { - renderTitle: function(){ + renderTitle: function () { return Method; } }, - render: function(){ + render: function () { var flow = this.props.flow; return {flow.request.method}; } @@ -84,14 +86,14 @@ var MethodColumn = React.createClass({ var StatusColumn = React.createClass({ statics: { - renderTitle: function(){ + renderTitle: function () { return Status; } }, - render: function(){ + render: function () { var flow = this.props.flow; var status; - if(flow.response){ + if (flow.response) { status = flow.response.code; } else { status = null; @@ -103,15 +105,15 @@ var StatusColumn = React.createClass({ var SizeColumn = React.createClass({ statics: { - renderTitle: function(){ + renderTitle: function () { return Size; } }, - render: function(){ + render: function () { var flow = this.props.flow; var total = flow.request.contentLength; - if(flow.response){ + if (flow.response) { total += flow.response.contentLength || 0; } var size = formatSize(total); @@ -122,14 +124,14 @@ var SizeColumn = React.createClass({ var TimeColumn = React.createClass({ statics: { - renderTitle: function(){ + renderTitle: function () { return Time; } }, - render: function(){ + render: function () { var flow = this.props.flow; var time; - if(flow.response){ + if (flow.response) { time = formatTimeDelta(1000 * (flow.response.timestamp_end - flow.request.timestamp_start)); } else { time = "..."; diff --git a/web/src/js/components/flowtable.jsx.js b/web/src/js/components/flowtable.jsx.js index 2baf728f..6b56e512 100644 --- a/web/src/js/components/flowtable.jsx.js +++ b/web/src/js/components/flowtable.jsx.js @@ -1,11 +1,11 @@ var FlowRow = React.createClass({ - render: function(){ + render: function () { var flow = this.props.flow; - var columns = this.props.columns.map(function(Column){ + var columns = this.props.columns.map(function (Column) { return ; }.bind(this)); var className = ""; - if(this.props.selected){ + if (this.props.selected) { className += "selected"; } return ( @@ -13,35 +13,37 @@ var FlowRow = React.createClass({ {columns} ); }, - shouldComponentUpdate: function(nextProps){ + shouldComponentUpdate: function (nextProps) { var isEqual = ( - this.props.columns.length === nextProps.columns.length && - this.props.selected === nextProps.selected && - this.props.flow.response === nextProps.flow.response); + this.props.columns.length === nextProps.columns.length && + this.props.selected === nextProps.selected && + this.props.flow.response === nextProps.flow.response); return !isEqual; } }); var FlowTableHead = React.createClass({ - render: function(){ - var columns = this.props.columns.map(function(column){ + render: function () { + var columns = this.props.columns.map(function (column) { return column.renderTitle(); }.bind(this)); - return {columns}; + return + {columns} + ; } }); var FlowTableBody = React.createClass({ - render: function(){ - var rows = this.props.flows.map(function(flow){ + render: function () { + var rows = this.props.flows.map(function (flow) { var selected = (flow == this.props.selected); return ; + ref={flow.id} + flow={flow} + columns={this.props.columns} + selected={selected} + selectFlow={this.props.selectFlow} + />; }.bind(this)); return {rows}; } @@ -55,7 +57,7 @@ var FlowTable = React.createClass({ columns: all_columns }; }, - scrollIntoView: function(flow){ + scrollIntoView: function (flow) { // Now comes the fun part: Scroll the flow into the view. var viewport = this.getDOMNode(); var flowNode = this.refs.body.refs[flow.id].getDOMNode(); @@ -68,9 +70,9 @@ var FlowTable = React.createClass({ // -thead_height pixel earlier. flowNode_top -= this.refs.body.getDOMNode().offsetTop; - if(flowNode_top < viewport_top){ + if (flowNode_top < viewport_top) { viewport.scrollTop = flowNode_top; - } else if(flowNode_bottom > viewport_bottom) { + } else if (flowNode_bottom > viewport_bottom) { viewport.scrollTop = flowNode_bottom - viewport.offsetHeight; } }, @@ -79,14 +81,14 @@ var FlowTable = React.createClass({
+ columns={this.state.columns}/> + flows={this.props.flows} + selected={this.props.selected} + selectFlow={this.props.selectFlow} + columns={this.state.columns}/>
- ); + ); } }); diff --git a/web/src/js/components/footer.jsx.js b/web/src/js/components/footer.jsx.js index 6ba253bf..73fadef2 100644 --- a/web/src/js/components/footer.jsx.js +++ b/web/src/js/components/footer.jsx.js @@ -5,6 +5,6 @@ var Footer = React.createClass({
{mode != "regular" ? {mode} mode : null}
- ); + ); } }); diff --git a/web/src/js/components/header.jsx.js b/web/src/js/components/header.jsx.js index 5c905889..e50c4274 100644 --- a/web/src/js/components/header.jsx.js +++ b/web/src/js/components/header.jsx.js @@ -12,10 +12,11 @@ var MainMenu = React.createClass({ return (
- ); + ); } }); @@ -61,25 +62,25 @@ var Header = React.createClass({ console.log("File click"); }, render: function () { - var header = header_entries.map(function(entry, i){ + var header = header_entries.map(function (entry, i) { var classes = React.addons.classSet({ active: entry == this.state.active }); return ( - { entry.title} - ); + ); }.bind(this)); - + return (
- mitmproxy { this.props.settings.version } + mitmproxy { this.props.settings.version }
- ); + ); } }); diff --git a/web/src/js/components/utils.jsx.js b/web/src/js/components/utils.jsx.js index 22aca577..b1d9a006 100644 --- a/web/src/js/components/utils.jsx.js +++ b/web/src/js/components/utils.jsx.js @@ -6,85 +6,85 @@ var Splitter = React.createClass({ axis: "x" }; }, - getInitialState: function(){ + getInitialState: function () { return { applied: false, startX: false, startY: false }; }, - onMouseDown: function(e){ + onMouseDown: function (e) { this.setState({ startX: e.pageX, startY: e.pageY }); - window.addEventListener("mousemove",this.onMouseMove); - window.addEventListener("mouseup",this.onMouseUp); + window.addEventListener("mousemove", this.onMouseMove); + window.addEventListener("mouseup", this.onMouseUp); // Occasionally, only a dragEnd event is triggered, but no mouseUp. - window.addEventListener("dragend",this.onDragEnd); + window.addEventListener("dragend", this.onDragEnd); }, - onDragEnd: function(){ - this.getDOMNode().style.transform=""; - window.removeEventListener("dragend",this.onDragEnd); - window.removeEventListener("mouseup",this.onMouseUp); - window.removeEventListener("mousemove",this.onMouseMove); + onDragEnd: function () { + this.getDOMNode().style.transform = ""; + window.removeEventListener("dragend", this.onDragEnd); + window.removeEventListener("mouseup", this.onMouseUp); + window.removeEventListener("mousemove", this.onMouseMove); }, - onMouseUp: function(e){ + onMouseUp: function (e) { this.onDragEnd(); var node = this.getDOMNode(); var prev = node.previousElementSibling; var next = node.nextElementSibling; - var dX = e.pageX-this.state.startX; - var dY = e.pageY-this.state.startY; + var dX = e.pageX - this.state.startX; + var dY = e.pageY - this.state.startY; var flexBasis; - if(this.props.axis === "x"){ + if (this.props.axis === "x") { flexBasis = prev.offsetWidth + dX; } else { flexBasis = prev.offsetHeight + dY; } - prev.style.flex = "0 0 "+Math.max(0, flexBasis)+"px"; + prev.style.flex = "0 0 " + Math.max(0, flexBasis) + "px"; next.style.flex = "1 1 auto"; this.setState({ applied: true }); }, - onMouseMove: function(e){ + onMouseMove: function (e) { var dX = 0, dY = 0; - if(this.props.axis === "x"){ - dX = e.pageX-this.state.startX; + if (this.props.axis === "x") { + dX = e.pageX - this.state.startX; } else { - dY = e.pageY-this.state.startY; + dY = e.pageY - this.state.startY; } - this.getDOMNode().style.transform = "translate("+dX+"px,"+dY+"px)"; + this.getDOMNode().style.transform = "translate(" + dX + "px," + dY + "px)"; }, - reset: function(willUnmount) { + reset: function (willUnmount) { if (!this.state.applied) { return; } var node = this.getDOMNode(); var prev = node.previousElementSibling; var next = node.nextElementSibling; - + prev.style.flex = ""; next.style.flex = ""; - if(!willUnmount){ + if (!willUnmount) { this.setState({ applied: false }); } }, - componentWillUnmount: function(){ + componentWillUnmount: function () { this.reset(true); }, - render: function(){ + render: function () { var className = "splitter"; - if(this.props.axis === "x"){ + if (this.props.axis === "x") { className += " splitter-x"; } else { className += " splitter-y"; diff --git a/web/src/js/connection.js b/web/src/js/connection.js index 64d550bf..d511270d 100644 --- a/web/src/js/connection.js +++ b/web/src/js/connection.js @@ -1,20 +1,20 @@ function Connection(url) { - if(url[0] != "/"){ + if (url[0] != "/") { this.url = url; } else { this.url = location.origin.replace("http", "ws") + url; } var ws = new WebSocket(this.url); - ws.onopen = function(){ + ws.onopen = function () { this.onopen.apply(this, arguments); }.bind(this); - ws.onmessage = function(){ + ws.onmessage = function () { this.onmessage.apply(this, arguments); }.bind(this); - ws.onerror = function(){ + ws.onerror = function () { this.onerror.apply(this, arguments); }.bind(this); - ws.onclose = function(){ + ws.onclose = function () { this.onclose.apply(this, arguments); }.bind(this); this.ws = ws; @@ -33,6 +33,6 @@ Connection.prototype.onclose = function (close) { EventLogActions.add_event("WebSocket Connection closed."); console.debug("onclose", this, arguments); }; -Connection.prototype.close = function(){ +Connection.prototype.close = function () { this.ws.close(); }; \ No newline at end of file diff --git a/web/src/js/dispatcher.js b/web/src/js/dispatcher.js index 4fe23447..7fa97481 100644 --- a/web/src/js/dispatcher.js +++ b/web/src/js/dispatcher.js @@ -18,7 +18,7 @@ Dispatcher.prototype.unregister = function (callback) { }; Dispatcher.prototype.dispatch = function (payload) { console.debug("dispatch", payload); - for(var i = 0; i < this.callbacks.length; i++){ + for (var i = 0; i < this.callbacks.length; i++) { this.callbacks[i](payload); } }; diff --git a/web/src/js/stores/eventlogstore.js b/web/src/js/stores/eventlogstore.js index e356959a..439c2360 100644 --- a/web/src/js/stores/eventlogstore.js +++ b/web/src/js/stores/eventlogstore.js @@ -26,7 +26,7 @@ _.extend(EventLogView.prototype, EventEmitter.prototype, { }, add: function (entry) { this.log.push(entry); - if(this.log.length > 200){ + if (this.log.length > 200) { this.log.shift(); } this.emit("change"); @@ -51,37 +51,37 @@ _.extend(_EventLogStore.prototype, EventEmitter.prototype, { var view = new EventLogView(this, !since); return view; /* - //TODO: Really do bulk retrieval of last messages. - window.setTimeout(function () { - view.add_bulk([ - { - id: 1, - message: "Hello World" - }, - { - id: 2, - message: "I was already transmitted as an event." - } - ]); - }, 100); + //TODO: Really do bulk retrieval of last messages. + window.setTimeout(function () { + view.add_bulk([ + { + id: 1, + message: "Hello World" + }, + { + id: 2, + message: "I was already transmitted as an event." + } + ]); + }, 100); - var id = 2; - view.add({ - id: id++, - message: "I was already transmitted as an event." - }); - view.add({ - id: id++, - message: "I was only transmitted as an event before the bulk was added.." - }); - window.setInterval(function () { - view.add({ - id: id++, - message: "." - }); - }, 1000); - return view; - */ + var id = 2; + view.add({ + id: id++, + message: "I was already transmitted as an event." + }); + view.add({ + id: id++, + message: "I was only transmitted as an event before the bulk was added.." + }); + window.setInterval(function () { + view.add({ + id: id++, + message: "." + }); + }, 1000); + return view; + */ }, handle: function (action) { switch (action.type) { diff --git a/web/src/js/stores/flowstore.js b/web/src/js/stores/flowstore.js index 91a5d9ec..60cd2605 100644 --- a/web/src/js/stores/flowstore.js +++ b/web/src/js/stores/flowstore.js @@ -37,7 +37,7 @@ _.extend(FlowStore.prototype, { this._pos_map[flow.id] = i; } }, - get: function(flow_id){ + get: function (flow_id) { return this._flow_list[this._pos_map[flow_id]]; } }); @@ -55,12 +55,12 @@ function LiveFlowStore(endpoint) { }.bind(this); } _.extend(LiveFlowStore.prototype, FlowStore.prototype, { - close: function(){ + close: function () { this.conn.close(); }, - add: function(flow) { + add: function (flow) { // Make sure that deferred adds don't add an element twice. - if(!this._pos_map[flow.id]){ + if (!this._pos_map[flow.id]) { FlowStore.prototype.add.call(this, flow); } }, @@ -117,7 +117,7 @@ function FlowView(store, filt, sort) { } _.extend(FlowView.prototype, EventEmitter.prototype, { - close: function(){ + close: function () { this.store._views = _.without(this.store._views, this); }, recalculate: function (flows, filt, sort) { diff --git a/web/src/js/utils.js b/web/src/js/utils.js index fa15db8c..5ac522ac 100644 --- a/web/src/js/utils.js +++ b/web/src/js/utils.js @@ -41,8 +41,8 @@ var Key = { var formatSize = function (bytes) { var size = bytes; var prefix = ["B", "KB", "MB", "GB", "TB"]; - var i=0; - while (Math.abs(size) >= 1024 && i < prefix.length-1) { + var i = 0; + while (Math.abs(size) >= 1024 && i < prefix.length - 1) { i++; size = size / 1024; } -- cgit v1.2.3 0'>700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 
/*
 *  yosys -- Yosys Open SYnthesis Suite
 *
 *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
 *
 *  Permission to use, copy, modify, and/or distribute this software for any
 *  purpose with or without fee is hereby granted, provided that the above
 *  copyright notice and this permission notice appear in all copies.
 *
 *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */

#include "kernel/rtlil.h"
#include "kernel/register.h"
#include "kernel/sigtools.h"
#include "kernel/celltypes.h"
#include "kernel/log.h"
#include <string>

USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN

struct BtorWorker
{
	std::ostream &f;
	SigMap sigmap;
	RTLIL::Module *module;
	bool verbose;
	bool single_bad;

	int next_nid = 1;
	int initstate_nid = -1;

	// <width> => <sid>
	dict<int, int> sorts_bv;

	// (<address-width>, <data-width>) => <sid>
	dict<pair<int, int>, int> sorts_mem;

	// SigBit => (<nid>, <bitidx>)
	dict<SigBit, pair<int, int>> bit_nid;

	// <nid> => <bvwidth>
	dict<int, int> nid_width;

	// SigSpec => <nid>
	dict<SigSpec, int> sig_nid;

	// bit to driving cell
	dict<SigBit, Cell*> bit_cell;

	// nids for constants
	dict<Const, int> consts;

	// ff inputs that need to be evaluated (<nid>, <ff_cell>)
	vector<pair<int, Cell*>> ff_todo;

	pool<Cell*> cell_recursion_guard;
	vector<int> bad_properties;
	dict<SigBit, bool> initbits;
	pool<Wire*> statewires;
	string indent;

	void btorf(const char *fmt, ...)
	{
		va_list ap;
		va_start(ap, fmt);
		f << indent << vstringf(fmt, ap);
		va_end(ap);
	}

	void btorf_push(const string &id)
	{
		if (verbose) {
			f << indent << stringf("  ; begin %s\n", id.c_str());
			indent += "    ";
		}
	}

	void btorf_pop(const string &id)
	{
		if (verbose) {
			indent = indent.substr(4);
			f << indent << stringf("  ; end %s\n", id.c_str());
		}
	}

	int get_bv_sid(int width)
	{
		if (sorts_bv.count(width) == 0) {
			int nid = next_nid++;
			btorf("%d sort bitvec %d\n", nid, width);
			sorts_bv[width] = nid;
		}
		return sorts_bv.at(width);
	}

	int get_mem_sid(int abits, int dbits)
	{
		pair<int, int> key(abits, dbits);
		if (sorts_mem.count(key) == 0) {
			int addr_sid = get_bv_sid(abits);
			int data_sid = get_bv_sid(dbits);
			int nid = next_nid++;
			btorf("%d sort array %d %d\n", nid, addr_sid, data_sid);
			sorts_mem[key] = nid;
		}
		return sorts_mem.at(key);
	}

	void add_nid_sig(int nid, const SigSpec &sig)
	{
		if (verbose)
			f << indent << stringf("; %d %s\n", nid, log_signal(sig));

		for (int i = 0; i < GetSize(sig); i++)
			bit_nid[sig[i]] = make_pair(nid, i);

		sig_nid[sig] = nid;
		nid_width[nid] = GetSize(sig);
	}

	void export_cell(Cell *cell)
	{
		log_assert(cell_recursion_guard.count(cell) == 0);
		cell_recursion_guard.insert(cell);
		btorf_push(log_id(cell));

		if (cell->type.in("$add", "$sub", "$mul", "$and", "$or", "$xor", "$xnor", "$shl", "$sshl", "$shr", "$sshr", "$shift", "$shiftx",
				"$concat", "$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_"))
		{
			string btor_op;
			if (cell->type == "$add") btor_op = "add";
			if (cell->type == "$sub") btor_op = "sub";
			if (cell->type == "$mul") btor_op = "mul";
			if (cell->type.in("$shl", "$sshl")) btor_op = "sll";
			if (cell->type == "$shr") btor_op = "srl";
			if (cell->type == "$sshr") btor_op = "sra";
			if (cell->type.in("$shift", "$shiftx")) btor_op = "shift";
			if (cell->type.in("$and", "$_AND_")) btor_op = "and";
			if (cell->type.in("$or", "$_OR_")) btor_op = "or";
			if (cell->type.in("$xor", "$_XOR_")) btor_op = "xor";
			if (cell->type == "$concat") btor_op = "concat";
			if (cell->type == "$_NAND_") btor_op = "nand";
			if (cell->type == "$_NOR_") btor_op = "nor";
			if (cell->type.in("$xnor", "$_XNOR_")) btor_op = "xnor";
			log_assert(!btor_op.empty());

			int width = GetSize(cell->getPort("\\Y"));
			width = std::max(width, GetSize(cell->getPort("\\A")));
			width = std::max(width, GetSize(cell->getPort("\\B")));

			bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false;
			bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false;

			if (btor_op == "shift" && !b_signed)
				btor_op = "srl";

			if (cell->type.in("$shl", "$sshl", "$shr", "$sshr"))
				b_signed = false;

			if (cell->type == "$sshr" && !a_signed)
				btor_op = "srl";

			int sid = get_bv_sid(width);
			int nid;

			if (btor_op == "shift")
			{
				int nid_a = get_sig_nid(cell->getPort("\\A"), width, false);
				int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed);

				int nid_r = next_nid++;
				btorf("%d srl %d %d %d\n", nid_r, sid, nid_a, nid_b);

				int nid_b_neg = next_nid++;
				btorf("%d neg %d %d\n", nid_b_neg, sid, nid_b);

				int nid_l = next_nid++;
				btorf("%d sll %d %d %d\n", nid_l, sid, nid_a, nid_b_neg);

				int sid_bit = get_bv_sid(1);
				int nid_zero = get_sig_nid(Const(0, width));
				int nid_b_ltz = next_nid++;
				btorf("%d slt %d %d %d\n", nid_b_ltz, sid_bit, nid_b, nid_zero);

				nid = next_nid++;
				btorf("%d ite %d %d %d %d\n", nid, sid, nid_b_ltz, nid_l, nid_r);
			}
			else
			{
				int nid_a = get_sig_nid(cell->getPort("\\A"), width, a_signed);
				int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed);

				nid = next_nid++;
				btorf("%d %s %d %d %d\n", nid, btor_op.c_str(), sid, nid_a, nid_b);
			}

			SigSpec sig = sigmap(cell->getPort("\\Y"));

			if (GetSize(sig) < width) {
				int sid = get_bv_sid(GetSize(sig));
				int nid2 = next_nid++;
				btorf("%d slice %d %d %d 0\n", nid2, sid, nid, GetSize(sig)-1);
				nid = nid2;
			}

			add_nid_sig(nid, sig);
			goto okay;
		}

		if (cell->type.in("$div", "$mod"))
		{
			string btor_op;
			if (cell->type == "$div") btor_op = "div";
			if (cell->type == "$mod") btor_op = "rem";
			log_assert(!btor_op.empty());

			int width = GetSize(cell->getPort("\\Y"));
			width = std::max(width, GetSize(cell->getPort("\\A")));
			width = std::max(width, GetSize(cell->getPort("\\B")));

			bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false;
			bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false;

			int nid_a = get_sig_nid(cell->getPort("\\A"), width, a_signed);
			int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed);

			int sid = get_bv_sid(width);
			int nid = next_nid++;
			btorf("%d %c%s %d %d %d\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b);

			SigSpec sig = sigmap(cell->getPort("\\Y"));

			if (GetSize(sig) < width) {
				int sid = get_bv_sid(GetSize(sig));
				int nid2 = next_nid++;
				btorf("%d slice %d %d %d 0\n", nid2, sid, nid, GetSize(sig)-1);
				nid = nid2;
			}

			add_nid_sig(nid, sig);
			goto okay;
		}

		if (cell->type.in("$_ANDNOT_", "$_ORNOT_"))
		{
			int sid = get_bv_sid(1);
			int nid_a = get_sig_nid(cell->getPort("\\A"));
			int nid_b = get_sig_nid(cell->getPort("\\B"));

			int nid1 = next_nid++;
			int nid2 = next_nid++;

			if (cell->type == "$_ANDNOT_") {
				btorf("%d not %d %d\n", nid1, sid, nid_b);
				btorf("%d and %d %d %d\n", nid2, sid, nid_a, nid1);
			}

			if (cell->type == "$_ORNOT_") {
				btorf("%d not %d %d\n", nid1, sid, nid_b);
				btorf("%d or %d %d %d\n", nid2, sid, nid_a, nid1);
			}

			SigSpec sig = sigmap(cell->getPort("\\Y"));
			add_nid_sig(nid2, sig);
			goto okay;
		}

		if (cell->type.in("$_OAI3_", "$_AOI3_"))
		{
			int sid = get_bv_sid(1);
			int nid_a = get_sig_nid(cell->getPort("\\A"));
			int nid_b = get_sig_nid(cell->getPort("\\B"));
			int nid_c = get_sig_nid(cell->getPort("\\C"));

			int nid1 = next_nid++;
			int nid2 = next_nid++;
			int nid3 = next_nid++;

			if (cell->type == "$_OAI3_") {
				btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
				btorf("%d and %d %d %d\n", nid2, sid, nid1, nid_c);
				btorf("%d not %d %d\n", nid3, sid, nid2);
			}

			if (cell->type == "$_AOI3_") {
				btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
				btorf("%d or %d %d %d\n", nid2, sid, nid1, nid_c);
				btorf("%d not %d %d\n", nid3, sid, nid2);
			}

			SigSpec sig = sigmap(cell->getPort("\\Y"));
			add_nid_sig(nid3, sig);
			goto okay;
		}

		if (cell->type.in("$_OAI4_", "$_AOI4_"))
		{
			int sid = get_bv_sid(1);
			int nid_a = get_sig_nid(cell->getPort("\\A"));
			int nid_b = get_sig_nid(cell->getPort("\\B"));
			int nid_c = get_sig_nid(cell->getPort("\\C"));
			int nid_d = get_sig_nid(cell->getPort("\\D"));

			int nid1 = next_nid++;
			int nid2 = next_nid++;
			int nid3 = next_nid++;
			int nid4 = next_nid++;

			if (cell->type == "$_OAI4_") {
				btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
				btorf("%d or %d %d %d\n", nid2, sid, nid_c, nid_d);
				btorf("%d and %d %d %d\n", nid3, sid, nid1, nid2);
				btorf("%d not %d %d\n", nid4, sid, nid3);
			}

			if (cell->type == "$_AOI4_") {
				btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
				btorf("%d and %d %d %d\n", nid2, sid, nid_c, nid_d);
				btorf("%d or %d %d %d\n", nid3, sid, nid1, nid2);
				btorf("%d not %d %d\n", nid4, sid, nid3);
			}

			SigSpec sig = sigmap(cell->getPort("\\Y"));
			add_nid_sig(nid4, sig);
			goto okay;
		}

		if (cell->type.in("$lt", "$le", "$eq", "$eqx", "$ne", "$nex", "$ge", "$gt"))
		{
			string btor_op;
			if (cell->type == "$lt") btor_op = "lt";
			if (cell->type == "$le") btor_op = "lte";
			if (cell->type.in("$eq", "$eqx")) btor_op = "eq";
			if (cell->type.in("$ne", "$nex")) btor_op = "ne";
			if (cell->type == "$ge") btor_op = "gte";
			if (cell->type == "$gt") btor_op = "gt";
			log_assert(!btor_op.empty());

			int width = 1;
			width = std::max(width, GetSize(cell->getPort("\\A")));
			width = std::max(width, GetSize(cell->getPort("\\B")));

			bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false;
			bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false;

			int sid = get_bv_sid(1);
			int nid_a = get_sig_nid(cell->getPort("\\A"), width, a_signed);
			int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed);

			int nid = next_nid++;
			if (cell->type.in("$lt", "$le", "$ge", "$gt")) {
				btorf("%d %c%s %d %d %d\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b);
			} else {
				btorf("%d %s %d %d %d\n", nid, btor_op.c_str(), sid, nid_a, nid_b);
			}

			SigSpec sig = sigmap(cell->getPort("\\Y"));

			if (GetSize(sig) > 1) {
				int sid = get_bv_sid(GetSize(sig));
				int nid2 = next_nid++;
				btorf("%d uext %d %d %d\n", nid2, sid, nid, GetSize(sig) - 1);
				nid = nid2;
			}

			add_nid_sig(nid, sig);
			goto okay;
		}

		if (cell->type.in("$not", "$neg", "$_NOT_"))
		{
			string btor_op;
			if (cell->type.in("$not", "$_NOT_")) btor_op = "not";
			if (cell->type == "$neg") btor_op = "neg";
			log_assert(!btor_op.empty());

			int width = GetSize(cell->getPort("\\Y"));
			width = std::max(width, GetSize(cell->getPort("\\A")));

			bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false;

			int sid = get_bv_sid(width);
			int nid_a = get_sig_nid(cell->getPort("\\A"), width, a_signed);

			int nid = next_nid++;
			btorf("%d %s %d %d\n", nid, btor_op.c_str(), sid, nid_a);

			SigSpec sig = sigmap(cell->getPort("\\Y"));

			if (GetSize(sig) < width) {
				int sid = get_bv_sid(GetSize(sig));
				int nid2 = next_nid++;
				btorf("%d slice %d %d %d 0\n", nid2, sid, nid, GetSize(sig)-1);
				nid = nid2;
			}

			add_nid_sig(nid, sig);
			goto okay;
		}

		if (cell->type.in("$logic_and", "$logic_or", "$logic_not"))
		{
			string btor_op;
			if (cell->type == "$logic_and") btor_op = "and";
			if (cell->type == "$logic_or")  btor_op = "or";
			if (cell->type == "$logic_not") btor_op = "not";
			log_assert(!btor_op.empty());

			int sid = get_bv_sid(1);
			int nid_a = get_sig_nid(cell->getPort("\\A"));
			int nid_b = btor_op != "not" ? get_sig_nid(cell->getPort("\\B")) : 0;

			if (GetSize(cell->getPort("\\A")) > 1) {
				int nid_red_a = next_nid++;
				btorf("%d redor %d %d\n", nid_red_a, sid, nid_a);
				nid_a = nid_red_a;
			}

			if (btor_op != "not" && GetSize(cell->getPort("\\B")) > 1) {
				int nid_red_b = next_nid++;
				btorf("%d redor %d %d\n", nid_red_b, sid, nid_b);
				nid_b = nid_red_b;
			}

			int nid = next_nid++;
			if (btor_op != "not")
				btorf("%d %s %d %d %d\n", nid, btor_op.c_str(), sid, nid_a, nid_b);
			else
				btorf("%d %s %d %d\n", nid, btor_op.c_str(), sid, nid_a);

			SigSpec sig = sigmap(cell->getPort("\\Y"));

			if (GetSize(sig) > 1) {
				int sid = get_bv_sid(GetSize(sig));
				int zeros_nid = get_sig_nid(Const(0, GetSize(sig)-1));
				int nid2 = next_nid++;
				btorf("%d concat %d %d %d\n", nid2, sid, zeros_nid, nid);
				nid = nid2;
			}

			add_nid_sig(nid, sig);
			goto okay;
		}

		if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_bool", "$reduce_xor", "$reduce_xnor"))
		{
			string btor_op;
			if (cell->type == "$reduce_and") btor_op = "redand";
			if (cell->type.in("$reduce_or", "$reduce_bool")) btor_op = "redor";
			if (cell->type.in("$reduce_xor", "$reduce_xnor")) btor_op = "redxor";
			log_assert(!btor_op.empty());

			int sid = get_bv_sid(1);
			int nid_a = get_sig_nid(cell->getPort("\\A"));

			int nid = next_nid++;
			btorf("%d %s %d %d\n", nid, btor_op.c_str(), sid, nid_a);

			if (cell->type == "$reduce_xnor") {
				int nid2 = next_nid++;
				btorf("%d not %d %d %d\n", nid2, sid, nid);
				nid = nid2;
			}

			SigSpec sig = sigmap(cell->getPort("\\Y"));

			if (GetSize(sig) > 1) {
				int sid = get_bv_sid(GetSize(sig));
				int zeros_nid = get_sig_nid(Const(0, GetSize(sig)-1));
				int nid2 = next_nid++;
				btorf("%d concat %d %d %d\n", nid2, sid, zeros_nid, nid);
				nid = nid2;
			}

			add_nid_sig(nid, sig);
			goto okay;
		}

		if (cell->type.in("$mux", "$_MUX_"))
		{
			SigSpec sig_a = sigmap(cell->getPort("\\A"));
			SigSpec sig_b = sigmap(cell->getPort("\\B"));
			SigSpec sig_s = sigmap(cell->getPort("\\S"));
			SigSpec sig_y = sigmap(cell->getPort("\\Y"));

			int nid_a = get_sig_nid(sig_a);
			int nid_b = get_sig_nid(sig_b);
			int nid_s = get_sig_nid(sig_s);

			int sid = get_bv_sid(GetSize(sig_y));
			int nid = next_nid++;
			btorf("%d ite %d %d %d %d\n", nid, sid, nid_s, nid_b, nid_a);

			add_nid_sig(nid, sig_y);
			goto okay;
		}

		if (cell->type == "$pmux")
		{
			SigSpec sig_a = sigmap(cell->getPort("\\A"));
			SigSpec sig_b = sigmap(cell->getPort("\\B"));
			SigSpec sig_s = sigmap(cell->getPort("\\S"));
			SigSpec sig_y = sigmap(cell->getPort("\\Y"));

			int width = GetSize(sig_a);
			int sid = get_bv_sid(width);
			int nid = get_sig_nid(sig_a);

			for (int i = 0; i < GetSize(sig_s); i++) {
				int nid_b = get_sig_nid(sig_b.extract(i*width, width));
				int nid_s = get_sig_nid(sig_s.extract(i));
				int nid2 = next_nid++;
				btorf("%d ite %d %d %d %d\n", nid2, sid, nid_s, nid_b, nid);
				nid = nid2;
			}

			add_nid_sig(nid, sig_y);
			goto okay;
		}

		if (cell->type.in("$dff", "$ff", "$_DFF_P_", "$_DFF_N", "$_FF_"))
		{
			SigSpec sig_d = sigmap(cell->getPort("\\D"));
			SigSpec sig_q = sigmap(cell->getPort("\\Q"));

			IdString symbol;

			if (sig_q.is_wire()) {
				Wire *w = sig_q.as_wire();
				if (w->port_id == 0) {
					statewires.insert(w);
					symbol = w->name;
				}
			}

			Const initval;
			for (int i = 0; i < GetSize(sig_q); i++)
				if (initbits.count(sig_q[i]))
					initval.bits.push_back(initbits.at(sig_q[i]) ? State::S1 : State::S0);
				else
					initval.bits.push_back(State::Sx);

			int nid_init_val = -1;

			if (!initval.is_fully_undef())
				nid_init_val = get_sig_nid(initval);

			int sid = get_bv_sid(GetSize(sig_q));
			int nid = next_nid++;

			if (symbol.empty())
				btorf("%d state %d\n", nid, sid);
			else
				btorf("%d state %d %s\n", nid, sid, log_id(symbol));

			if (nid_init_val >= 0) {
				int nid_init = next_nid++;
				if (verbose)
					btorf("; initval = %s\n", log_signal(initval));
				btorf("%d init %d %d %d\n", nid_init, sid, nid, nid_init_val);
			}

			ff_todo.push_back(make_pair(nid, cell));
			add_nid_sig(nid, sig_q);
			goto okay;
		}

		if (cell->type.in("$anyconst", "$anyseq"))
		{
			SigSpec sig_y = sigmap(cell->getPort("\\Y"));

			int sid = get_bv_sid(GetSize(sig_y));
			int nid = next_nid++;

			btorf("%d state %d\n", nid, sid);

			if (cell->type == "$anyconst") {
				int nid2 = next_nid++;
				btorf("%d next %d %d %d\n", nid2, sid, nid, nid);
			}

			add_nid_sig(nid, sig_y);
			goto okay;
		}

		if (cell->type == "$initstate")
		{
			SigSpec sig_y = sigmap(cell->getPort("\\Y"));

			if (initstate_nid < 0)
			{
				int sid = get_bv_sid(1);
				int one_nid = get_sig_nid(Const(1, 1));
				int zero_nid = get_sig_nid(Const(0, 1));
				initstate_nid = next_nid++;
				btorf("%d state %d\n", initstate_nid, sid);
				btorf("%d init %d %d %d\n", next_nid++, sid, initstate_nid, one_nid);
				btorf("%d next %d %d %d\n", next_nid++, sid, initstate_nid, zero_nid);
			}

			add_nid_sig(initstate_nid, sig_y);
			goto okay;
		}

		if (cell->type == "$mem")
		{
			int abits = cell->getParam("\\ABITS").as_int();
			int width = cell->getParam("\\WIDTH").as_int();
			int rdports = cell->getParam("\\RD_PORTS").as_int();
			int wrports = cell->getParam("\\WR_PORTS").as_int();

			Const wr_clk_en = cell->getParam("\\WR_CLK_ENABLE");
			Const rd_clk_en = cell->getParam("\\RD_CLK_ENABLE");

			bool asyncwr = wr_clk_en.is_fully_zero();

			if (!asyncwr && !wr_clk_en.is_fully_ones())
				log_error("Memory %s.%s has mixed async/sync write ports.\n",
						log_id(module), log_id(cell));

			if (!rd_clk_en.is_fully_zero())
				log_error("Memory %s.%s has sync read ports.\n",
						log_id(module), log_id(cell));

			SigSpec sig_rd_addr = sigmap(cell->getPort("\\RD_ADDR"));
			SigSpec sig_rd_data = sigmap(cell->getPort("\\RD_DATA"));

			SigSpec sig_wr_addr = sigmap(cell->getPort("\\WR_ADDR"));
			SigSpec sig_wr_data = sigmap(cell->getPort("\\WR_DATA"));
			SigSpec sig_wr_en = sigmap(cell->getPort("\\WR_EN"));

			int data_sid = get_bv_sid(width);
			int bool_sid = get_bv_sid(1);
			int sid = get_mem_sid(abits, width);
			int nid = next_nid++;
			int nid_head = nid;

			if (cell->name[0] == '$')
				btorf("%d state %d\n", nid, sid);
			else
				btorf("%d state %d %s\n", nid, sid, log_id(cell));

			if (asyncwr)
			{
				for (int port = 0; port < wrports; port++)
				{
					SigSpec wa = sig_wr_addr.extract(port*abits, abits);
					SigSpec wd = sig_wr_data.extract(port*width, width);
					SigSpec we = sig_wr_en.extract(port*width, width);

					int wa_nid = get_sig_nid(wa);
					int wd_nid = get_sig_nid(wd);
					int we_nid = get_sig_nid(we);

					int nid2 = next_nid++;
					btorf("%d read %d %d %d\n", nid2, data_sid, nid_head, wa_nid);

					int nid3 = next_nid++;
					btorf("%d not %d %d\n", nid3, data_sid, we_nid);

					int nid4 = next_nid++;
					btorf("%d and %d %d %d\n", nid4, data_sid, nid2, nid3);

					int nid5 = next_nid++;
					btorf("%d and %d %d %d\n", nid5, data_sid, wd_nid, we_nid);

					int nid6 = next_nid++;
					btorf("%d or %d %d %d\n", nid6, data_sid, nid5, nid4);

					int nid7 = next_nid++;
					btorf("%d write %d %d %d %d\n", nid7, sid, nid_head, wa_nid, nid6);

					int nid8 = next_nid++;
					btorf("%d redor %d %d\n", nid8, bool_sid, we_nid);

					int nid9 = next_nid++;
					btorf("%d ite %d %d %d %d\n", nid9, sid, nid8, nid7, nid_head);

					nid_head = nid9;
				}
			}

			for (int port = 0; port < rdports; port++)
			{
				SigSpec ra = sig_rd_addr.extract(port*abits, abits);
				SigSpec rd = sig_rd_data.extract(port*width, width);

				int ra_nid = get_sig_nid(ra);
				int rd_nid = next_nid++;

				btorf("%d read %d %d %d\n", rd_nid, data_sid, nid_head, ra_nid);

				add_nid_sig(rd_nid, rd);
			}

			if (!asyncwr)
			{
				ff_todo.push_back(make_pair(nid, cell));
			}
			else
			{
				int nid2 = next_nid++;
				btorf("%d next %d %d %d\n", nid2, sid, nid, nid_head);
			}

			goto okay;
		}

		log_error("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));

	okay:
		btorf_pop(log_id(cell));
		cell_recursion_guard.erase(cell);
	}

	int get_sig_nid(SigSpec sig, int to_width = -1, bool is_signed = false)
	{
		int nid = -1;
		sigmap.apply(sig);

		for (auto bit : sig)
			if (bit == State::Sx)
				goto has_undef_bits;

		if (0)
		{
	has_undef_bits:
			SigSpec sig_mask_undef, sig_noundef;
			int first_undef = -1;

			for (int i = 0; i < GetSize(sig); i++)
				if (sig[i] == State::Sx) {
					if (first_undef < 0)
						first_undef = i;
					sig_mask_undef.append(State::S1);
					sig_noundef.append(State::S0);
				} else {
					sig_mask_undef.append(State::S0);
					sig_noundef.append(sig[i]);
				}

			if (to_width < 0 || first_undef < to_width)
			{
				int sid = get_bv_sid(GetSize(sig));

				int nid_input = next_nid++;
				btorf("%d input %d\n", nid_input, sid);

				int nid_masked_input;
				if (sig_mask_undef.is_fully_ones()) {
					nid_masked_input = nid_input;
				} else {
					int nid_mask_undef = get_sig_nid(sig_mask_undef);
					nid_masked_input = next_nid++;
					btorf("%d and %d %d %d\n", nid_masked_input, sid, nid_input, nid_mask_undef);
				}

				if (sig_noundef.is_fully_zero()) {
					nid = nid_masked_input;
				} else {
					int nid_noundef = get_sig_nid(sig_noundef);
					nid = next_nid++;
					btorf("%d or %d %d %d\n", nid, sid, nid_masked_input, nid_noundef);
				}

				goto extend_or_trim;
			}

			sig = sig_noundef;
		}

		if (sig_nid.count(sig) == 0)
		{
			// <nid>, <bitidx>
			vector<pair<int, int>> nidbits;

			// collect all bits
			for (int i = 0; i < GetSize(sig); i++)
			{
				SigBit bit = sig[i];

				if (bit_nid.count(bit) == 0)
				{
					if (bit.wire == nullptr)
					{
						Const c(bit.data);

						while (i+GetSize(c) < GetSize(sig) && sig[i+GetSize(c)].wire == nullptr)
							c.bits.push_back(sig[i+GetSize(c)].data);

						if (consts.count(c) == 0) {
							int sid = get_bv_sid(GetSize(c));
							int nid = next_nid++;
							btorf("%d const %d %s\n", nid, sid, c.as_string().c_str());
							consts[c] = nid;
							nid_width[nid] = GetSize(c);
						}

						int nid = consts.at(c);

						for (int j = 0; j < GetSize(c); j++)
							nidbits.push_back(make_pair(nid, j));

						i += GetSize(c)-1;
						continue;
					}
					else
					{
						if (bit_cell.count(bit) == 0)
							log_error("No driver for signal bit %s.\n", log_signal(bit));
						export_cell(bit_cell.at(bit));
						log_assert(bit_nid.count(bit));
					}
				}

				nidbits.push_back(bit_nid.at(bit));
			}

			int width = 0;
			int nid = -1;

			// group bits and emit slice-concat chain
			for (int i = 0; i < GetSize(nidbits); i++)
			{
				int nid2 = nidbits[i].first;
				int lower =  nidbits[i].second;
				int upper = lower;

				while (i+1 < GetSize(nidbits) && nidbits[i+1].first == nidbits[i].first &&
						nidbits[i+1].second == nidbits[i].second+1)
					upper++, i++;

				int nid3 = nid2;

				if (lower != 0 || upper+1 != nid_width.at(nid2)) {
					int sid = get_bv_sid(upper-lower+1);
					nid3 = next_nid++;
					btorf("%d slice %d %d %d %d\n", nid3, sid, nid2, upper, lower);
				}

				int nid4 = nid3;

				if (nid >= 0) {
					int sid = get_bv_sid(width+upper-lower+1);
					nid4 = next_nid++;
					btorf("%d concat %d %d %d\n", nid4, sid, nid3, nid);
				}

				width += upper-lower+1;
				nid = nid4;
			}

			sig_nid[sig] = nid;
			nid_width[nid] = width;
		}

		nid = sig_nid.at(sig);

	extend_or_trim:
		if (to_width >= 0 && to_width != GetSize(sig))
		{
			if (to_width < GetSize(sig))
			{
				int sid = get_bv_sid(to_width);
				int nid2 = next_nid++;
				btorf("%d slice %d %d %d 0\n", nid2, sid, nid, to_width-1);
				nid = nid2;
			}
			else
			{
				int sid = get_bv_sid(to_width);
				int nid2 = next_nid++;
				btorf("%d %s %d %d %d\n", nid2, is_signed ? "sext" : "uext",
						sid, nid, to_width - GetSize(sig));
				nid = nid2;
			}
		}

		return nid;
	}

	BtorWorker(std::ostream &f, RTLIL::Module *module, bool verbose, bool single_bad) :
			f(f), sigmap(module), module(module), verbose(verbose), single_bad(single_bad)
	{
		btorf_push("inputs");

		for (auto wire : module->wires())
		{
			if (wire->attributes.count("\\init")) {
				Const attrval = wire->attributes.at("\\init");
				for (int i = 0; i < GetSize(wire) && i < GetSize(attrval); i++)
					if (attrval[i] == State::S0 || attrval[i] == State::S1)
						initbits[sigmap(SigBit(wire, i))] = (attrval[i] == State::S1);
			}

			if (!wire->port_id || !wire->port_input)
				continue;

			SigSpec sig = sigmap(wire);
			int sid = get_bv_sid(GetSize(sig));
			int nid = next_nid++;

			btorf("%d input %d %s\n", nid, sid, log_id(wire));
			add_nid_sig(nid, sig);
		}

		btorf_pop("inputs");

		for (auto cell : module->cells())
		for (auto &conn : cell->connections())
		{
			if (!cell->output(conn.first))
				continue;

			for (auto bit : sigmap(conn.second))
				bit_cell[bit] = cell;
		}

		for (auto wire : module->wires())
		{
			if (!wire->port_id || !wire->port_output)
				continue;

			btorf_push(stringf("output %s", log_id(wire)));

			int sid = get_bv_sid(GetSize(wire));
			int nid = get_sig_nid(wire);
			btorf("%d output %d %d %s\n", next_nid++, sid, nid, log_id(wire));

			btorf_pop(stringf("output %s", log_id(wire)));
		}

		for (auto cell : module->cells())
		{
			if (cell->type == "$assume")
			{
				btorf_push(log_id(cell));

				int sid = get_bv_sid(1);
				int nid_a = get_sig_nid(cell->getPort("\\A"));
				int nid_en = get_sig_nid(cell->getPort("\\EN"));
				int nid_not_en = next_nid++;
				int nid_a_or_not_en = next_nid++;
				int nid = next_nid++;

				btorf("%d not %d %d\n", nid_not_en, sid, nid_en);
				btorf("%d or %d %d %d\n", nid_a_or_not_en, sid, nid_a, nid_not_en);
				btorf("%d constraint %d\n", nid, nid_a_or_not_en);

				btorf_pop(log_id(cell));
			}

			if (cell->type == "$assert")
			{
				btorf_push(log_id(cell));

				int sid = get_bv_sid(1);
				int nid_a = get_sig_nid(cell->getPort("\\A"));
				int nid_en = get_sig_nid(cell->getPort("\\EN"));
				int nid_not_a = next_nid++;
				int nid_en_and_not_a = next_nid++;

				btorf("%d not %d %d\n", nid_not_a, sid, nid_a);
				btorf("%d and %d %d %d\n", nid_en_and_not_a, sid, nid_en, nid_not_a);

				if (single_bad) {
					bad_properties.push_back(nid_en_and_not_a);
				} else {
					int nid = next_nid++;
					btorf("%d bad %d\n", nid, nid_en_and_not_a);
				}

				btorf_pop(log_id(cell));
			}
		}

		for (auto wire : module->wires())
		{
			if (wire->port_id || wire->name[0] == '$')
				continue;

			btorf_push(stringf("wire %s", log_id(wire)));

			int sid = get_bv_sid(GetSize(wire));
			int nid = get_sig_nid(sigmap(wire));

			if (statewires.count(wire))
				continue;

			int this_nid = next_nid++;
			btorf("%d uext %d %d %d %s\n", this_nid, sid, nid, 0, log_id(wire));

			btorf_pop(stringf("wire %s", log_id(wire)));
			continue;
		}

		while (!ff_todo.empty())
		{
			vector<pair<int, Cell*>> todo;
			todo.swap(ff_todo);

			for (auto &it : todo)
			{
				int nid = it.first;
				Cell *cell = it.second;

				btorf_push(stringf("next %s", log_id(cell)));

				if (cell->type == "$mem")
				{
					int abits = cell->getParam("\\ABITS").as_int();
					int width = cell->getParam("\\WIDTH").as_int();
					int wrports = cell->getParam("\\WR_PORTS").as_int();

					SigSpec sig_wr_addr = sigmap(cell->getPort("\\WR_ADDR"));
					SigSpec sig_wr_data = sigmap(cell->getPort("\\WR_DATA"));
					SigSpec sig_wr_en = sigmap(cell->getPort("\\WR_EN"));

					int data_sid = get_bv_sid(width);
					int bool_sid = get_bv_sid(1);
					int sid = get_mem_sid(abits, width);
					int nid_head = nid;

					for (int port = 0; port < wrports; port++)
					{
						SigSpec wa = sig_wr_addr.extract(port*abits, abits);
						SigSpec wd = sig_wr_data.extract(port*width, width);
						SigSpec we = sig_wr_en.extract(port*width, width);

						int wa_nid = get_sig_nid(wa);
						int wd_nid = get_sig_nid(wd);
						int we_nid = get_sig_nid(we);

						int nid2 = next_nid++;
						btorf("%d read %d %d %d\n", nid2, data_sid, nid_head, wa_nid);

						int nid3 = next_nid++;
						btorf("%d not %d %d\n", nid3, data_sid, we_nid);

						int nid4 = next_nid++;
						btorf("%d and %d %d %d\n", nid4, data_sid, nid2, nid3);

						int nid5 = next_nid++;
						btorf("%d and %d %d %d\n", nid5, data_sid, wd_nid, we_nid);

						int nid6 = next_nid++;
						btorf("%d or %d %d %d\n", nid6, data_sid, nid5, nid4);

						int nid7 = next_nid++;
						btorf("%d write %d %d %d %d\n", nid7, sid, nid_head, wa_nid, nid6);

						int nid8 = next_nid++;
						btorf("%d redor %d %d\n", nid8, bool_sid, we_nid);

						int nid9 = next_nid++;
						btorf("%d ite %d %d %d %d\n", nid9, sid, nid8, nid7, nid_head);

						nid_head = nid9;
					}

					int nid2 = next_nid++;
					btorf("%d next %d %d %d\n", nid2, sid, nid, nid_head);
				}
				else
				{
					SigSpec sig = sigmap(cell->getPort("\\D"));
					int nid_q = get_sig_nid(sig);
					int sid = get_bv_sid(GetSize(sig));
					btorf("%d next %d %d %d\n", next_nid++, sid, nid, nid_q);
				}

				btorf_pop(stringf("next %s", log_id(cell)));
			}
		}

		while (!bad_properties.empty())
		{
			vector<int> todo;
			bad_properties.swap(todo);

			int sid = get_bv_sid(1);
			int cursor = 0;

			while (cursor+1 < GetSize(todo))
			{
				int nid_a = todo[cursor++];
				int nid_b = todo[cursor++];
				int nid = next_nid++;

				bad_properties.push_back(nid);
				btorf("%d or %d %d %d\n", nid, sid, nid_a, nid_b);
			}

			if (!bad_properties.empty()) {
				if (cursor < GetSize(todo))
					bad_properties.push_back(todo[cursor++]);
				log_assert(cursor == GetSize(todo));
			} else {
				int nid = next_nid++;
				log_assert(cursor == 0);
				log_assert(GetSize(todo) == 1);
				btorf("%d bad %d\n", nid, todo[cursor]);
			}
		}
	}
};

struct BtorBackend : public Backend {
	BtorBackend() : Backend("btor", "write design to BTOR file") { }
	void help() YS_OVERRIDE
	{
		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
		log("\n");
		log("    write_btor [options] [filename]\n");
		log("\n");
		log("Write a BTOR description of the current design.\n");
		log("\n");
		log("  -v\n");
		log("    Add comments and indentation to BTOR output file\n");
		log("\n");
		log("  -s\n");
		log("    Output only a single bad property for all asserts\n");
		log("\n");
	}
	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
	{
		bool verbose = false, single_bad = false;

		log_header(design, "Executing BTOR backend.\n");

		size_t argidx;
		for (argidx = 1; argidx < args.size(); argidx++)
		{
			if (args[argidx] == "-v") {
				verbose = true;
				continue;
			}
			if (args[argidx] == "-s") {
				single_bad = true;
				continue;
			}
			break;
		}
		extra_args(f, filename, args, argidx);

		RTLIL::Module *topmod = design->top_module();

		if (topmod == nullptr)
			log_cmd_error("No top module found.\n");

		*f << stringf("; BTOR description generated by %s for module %s.\n",
				yosys_version_str, log_id(topmod));

		BtorWorker(*f, topmod, verbose, single_bad);

		*f << stringf("; end of yosys output\n");
	}
} BtorBackend;

PRIVATE_NAMESPACE_END
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-14 22:57:44 +0000