``` yosys -- Yosys Open SYnthesis Suite Copyright (C) 2012 - 2020 Claire Wolf Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies. THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. ``` yosys – Yosys Open SYnthesis Suite =================================== This is a framework for RTL synthesis tools. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base. Yosys is free software licensed under the ISC license (a GPL compatible license that is similar in terms to the MIT license or the 2-clause BSD license). Web Site and Other Resources ============================ More information and documentation can be found on the Yosys web site: - http://www.clifford.at/yosys/ The "Documentation" page on the web site contains links to more resources, including a manual that even describes some of the Yosys internals: - http://www.clifford.at/yosys/documentation.html The file `CodingReadme` in this directory contains additional information for people interested in using the Yosys C++ APIs. Users interested in formal verification might want to use the formal verification front-end for Yosys, SymbiYosys: - https://symbiyosys.readthedocs.io/en/latest/ - https://github.com/YosysHQ/SymbiYosys Setup ====== You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make. TCL, readline and libffi are optional (see ``ENABLE_*`` settings in Makefile). Xdot (graphviz) is used by the ``show`` command in yosys to display schematics. For example on Ubuntu Linux 16.04 LTS the following commands will install all prerequisites for building yosys: $ sudo apt-get install build-essential clang bison flex \ libreadline-dev gawk tcl-dev libffi-dev git \ graphviz xdot pkg-config python3 libboost-system-dev \ libboost-python-dev libboost-filesystem-dev zlib1g-dev Similarily, on Mac OS X Homebrew can be used to install dependencies (from within cloned yosys repository): $ brew tap Homebrew/bundle && brew bundle or MacPorts: $ sudo port install bison flex readline gawk libffi \ git graphviz pkgconfig python36 boost zlib tcl On FreeBSD use the following command to install all prerequisites: # pkg install bison flex readline gawk libffi\ git graphviz pkgconf python3 python36 tcl-wrapper boost-libs On FreeBSD system use gmake instead of make. To run tests use: % MAKE=gmake CC=cc gmake test For Cygwin use the following command to install all prerequisites, or select these additional packages: setup-x86_64.exe -q --packages=bison,flex,gcc-core,gcc-g++,git,libffi-devel,libreadline-devel,make,pkg-config,python3,tcl-devel,boost-build,zlib-devel There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well as a source distribution for Visual Studio. Visit the Yosys download page for more information: http://www.clifford.at/yosys/download.html To configure the build system to use a specific compiler, use one of $ make config-clang $ make config-gcc For other compilers and build configurations it might be necessary to make some changes to the config section of the Makefile. $ vi Makefile # ..or.. $ vi Makefile.conf To build Yosys simply type 'make' in this directory. $ make $ sudo make install Note that this also downloads, builds and installs ABC (using yosys-abc as executable name). Tests are located in the tests subdirectory and can be executed using the test target. Note that you need gawk as well as a recent version of iverilog (i.e. build from git). Then, execute tests via: $ make test Getting Started ============
ARG IMAGE="python:3-slim-buster"

#---

FROM $IMAGE AS base

RUN apt-get update -qq \
 && DEBIAN_FRONTEND=noninteractive apt-get -y install --no-install-recommends \
    ca-certificates \
    clang \
    curl \
    libffi-dev \
    libreadline-dev \
    tcl-dev \
    graphviz \
    xdot \
 && apt-get autoclean && apt-get clean && apt-get -y autoremove \
 && update-ca-certificates \
 && rm -rf /var/lib/apt/lists

#---

FROM base AS build

RUN apt-get update -qq \
 && DEBIAN_FRONTEND=noninteractive apt-get -y install --no-install-recommends \
    bison \
    flex \
    gawk \
    gcc \
    git \
    iverilog \
    pkg-config \
 && apt-get autoclean && apt-get clean && apt-get -y autoremove \
 && rm -rf /var/lib/apt/lists

COPY . /yosys

ENV PREFIX /opt/yosys

RUN cd /yosys \
 && make \
 && make install \
 && make test

#---

FROM base

COPY --from=build /opt/yosys /opt/yosys

ENV PATH /opt/yosys/bin:$PATH

RUN useradd -m yosys
USER yosys

CMD ["yosys"]
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-09 15:17:20 +0000
lock buffer on this output, it will instead try inserting the clock buffer on the input port (this is used to implement clock inverter cells that clock buffer insertion will "see through"). - The ``clkbuf_inhibit`` is the default attribute to set on a wire to prevent automatic clock buffer insertion by ``clkbufmap``. This behaviour can be overridden by providing a custom selection to ``clkbufmap``. - The ``invertible_pin`` attribute can be set on a port to mark it as invertible via a cell parameter. The name of the inversion parameter is specified as the value of this attribute. The value of the inversion parameter must be of the same width as the port, with 1 indicating an inverted bit and 0 indicating a non-inverted bit. - The ``iopad_external_pin`` attribute on a blackbox module's port marks it as the external-facing pin of an I/O pad, and prevents ``iopadmap`` from inserting another pad cell on it. - The module attribute ``abc9_lut`` is an integer attribute indicating to `abc9` that this module describes a LUT with an area cost of this value, and propagation delays described using `specify` statements. - The module attribute ``abc9_box`` is a boolean specifying a black/white-box definition, with propagation delays described using `specify` statements, for use by `abc9`. - The port attribute ``abc9_carry`` marks the carry-in (if an input port) and carry-out (if output port) ports of a box. This information is necessary for `abc9` to preserve the integrity of carry-chains. Specifying this attribute onto a bus port will affect only its most significant bit. - The module attribute ``abc9_flop`` is a boolean marking the module as a flip-flop. This allows `abc9` to analyse its contents in order to perform sequential synthesis. - The frontend sets attributes ``always_comb``, ``always_latch`` and ``always_ff`` on processes derived from SystemVerilog style always blocks according to the type of the always. These are checked for correctness in ``proc_dlatch``. - The cell attribute ``wildcard_port_conns`` represents wildcard port connections (SystemVerilog ``.*``). These are resolved to concrete connections to matching wires in ``hierarchy``. - In addition to the ``(* ... *)`` attribute syntax, Yosys supports the non-standard ``{* ... *}`` attribute syntax to set default attributes for everything that comes after the ``{* ... *}`` statement. (Reset by adding an empty ``{* *}`` statement.) - In module parameter and port declarations, and cell port and parameter lists, a trailing comma is ignored. This simplifies writing Verilog code generators a bit in some cases. - Modules can be declared with ``module mod_name(...);`` (with three dots instead of a list of module ports). With this syntax it is sufficient to simply declare a module port as 'input' or 'output' in the module body. - When defining a macro with `define, all text between triple double quotes is interpreted as macro body, even if it contains unescaped newlines. The triple double quotes are removed from the macro body. For example: `define MY_MACRO(a, b) """ assign a = 23; assign b = 42; """ - The attribute ``via_celltype`` can be used to implement a Verilog task or function by instantiating the specified cell type. The value is the name of the cell type to use. For functions the name of the output port can be specified by appending it to the cell type separated by a whitespace. The body of the task or function is unused in this case and can be used to specify a behavioral model of the cell type for simulation. For example: module my_add3(A, B, C, Y); parameter WIDTH = 8; input [WIDTH-1:0] A, B, C; output [WIDTH-1:0] Y; ... endmodule module top; ... (* via_celltype = "my_add3 Y" *) (* via_celltype_defparam_WIDTH = 32 *) function [31:0] add3; input [31:0] A, B, C; begin add3 = A + B + C; end endfunction ... endmodule - The ``wiretype`` attribute is added by the verilog parser for wires of a typedef'd type to indicate the type identifier. - Various ``enum_value_{value}`` attributes are added to wires of an enumerated type to give a map of possible enum items to their values. - The ``enum_base_type`` attribute is added to enum items to indicate which enum they belong to (enums -- anonymous and otherwise -- are automatically named with an auto-incrementing counter). Note that enums are currently not strongly typed. - A limited subset of DPI-C functions is supported. The plugin mechanism (see ``help plugin``) can be used to load .so files with implementations of DPI-C routines. As a non-standard extension it is possible to specify a plugin alias using the ``:`` syntax. For example: module dpitest; import "DPI-C" function foo:round = real my_round (real); parameter real r = my_round(12.345); endmodule $ yosys -p 'plugin -a foo -i /lib/libm.so; read_verilog dpitest.v' - Sized constants (the syntax ``'s?[bodh]``) support constant expressions as ````. If the expression is not a simple identifier, it must be put in parentheses. Examples: ``WIDTH'd42``, ``(4+2)'b101010`` - The system tasks ``$finish``, ``$stop`` and ``$display`` are supported in initial blocks in an unconditional context (only if/case statements on expressions over parameters and constant values are allowed). The intended use for this is synthesis-time DRC. - There is limited support for converting ``specify`` .. ``endspecify`` statements to special ``$specify2``, ``$specify3``, and ``$specrule`` cells, for use in blackboxes and whiteboxes. Use ``read_verilog -specify`` to enable this functionality. (By default these blocks are ignored.) Non-standard or SystemVerilog features for formal verification ============================================================== - Support for ``assert``, ``assume``, ``restrict``, and ``cover`` is enabled when ``read_verilog`` is called with ``-formal``. - The system task ``$initstate`` evaluates to 1 in the initial state and to 0 otherwise. - The system function ``$anyconst`` evaluates to any constant value. This is equivalent to declaring a reg as ``rand const``, but also works outside of checkers. (Yosys also supports ``rand const`` outside checkers.) - The system function ``$anyseq`` evaluates to any value, possibly a different value in each cycle. This is equivalent to declaring a reg as ``rand``, but also works outside of checkers. (Yosys also supports ``rand`` variables outside checkers.) - The system functions ``$allconst`` and ``$allseq`` can be used to construct formal exist-forall problems. Assumptions only hold if the trace satisfies the assumption for all ``$allconst/$allseq`` values. For assertions and cover statements it is sufficient if just one ``$allconst/$allseq`` value triggers the property (similar to ``$anyconst/$anyseq``). - Wires/registers declared using the ``anyconst/anyseq/allconst/allseq`` attribute (for example ``(* anyconst *) reg [7:0] foobar;``) will behave as if driven by a ``$anyconst/$anyseq/$allconst/$allseq`` function. - The SystemVerilog tasks ``$past``, ``$stable``, ``$rose`` and ``$fell`` are supported in any clocked block. - The syntax ``@($global_clock)`` can be used to create FFs that have no explicit clock input (``$ff`` cells). The same can be achieved by using ``@(posedge )`` or ``@(negedge )`` when ```` is marked with the ``(* gclk *)`` Verilog attribute. Supported features from SystemVerilog ===================================== When ``read_verilog`` is called with ``-sv``, it accepts some language features from SystemVerilog: - The ``assert`` statement from SystemVerilog is supported in its most basic form. In module context: ``assert property ();`` and within an always block: ``assert();``. It is transformed to an ``$assert`` cell. - The ``assume``, ``restrict``, and ``cover`` statements from SystemVerilog are also supported. The same limitations as with the ``assert`` statement apply. - The keywords ``always_comb``, ``always_ff`` and ``always_latch``, ``logic`` and ``bit`` are supported. - Declaring free variables with ``rand`` and ``rand const`` is supported. - Checkers without a port list that do not need to be instantiated (but instead behave like a named block) are supported. - SystemVerilog packages are supported. Once a SystemVerilog file is read into a design with ``read_verilog``, all its packages are available to SystemVerilog files being read into the same design afterwards. - typedefs are supported (including inside packages) - type casts are currently not supported - enums are supported (including inside packages) - but are currently not strongly typed - SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether ports are inputs or outputs are supported. Building the documentation ========================== Note that there is no need to build the manual if you just want to read it. Simply download the PDF from http://www.clifford.at/yosys/documentation.html instead. On Ubuntu, texlive needs these packages to be able to build the manual: sudo apt-get install texlive-binaries sudo apt-get install texlive-science # install algorithm2e.sty sudo apt-get install texlive-bibtex-extra # gets multibib.sty sudo apt-get install texlive-fonts-extra # gets skull.sty and dsfont.sty sudo apt-get install texlive-publishers # IEEEtran.cls Also the non-free font luximono should be installed, there is unfortunately no Ubuntu package for this so it should be installed separately using `getnonfreefonts`: wget https://tug.org/fonts/getnonfreefonts/install-getnonfreefonts sudo texlua install-getnonfreefonts # will install to /usr/local by default, can be changed by editing BINDIR at MANDIR at the top of the script getnonfreefonts luximono # installs to /home/user/texmf Then execute, from the root of the repository: make manual Notes: - To run `make manual` you need to have installed Yosys with `make install`, otherwise it will fail on finding `kernel/yosys.h` while building `PRESENTATION_Prog`.