read_verilog fsm_1.v
hierarchy -top fsm_1
proc
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm_1 # Constrain all select calls below inside the top module
#Vivado synthesizes 2 LUT5, 2 LUT4, 1 LUT3, 4 FDRE.
stat
select -assert-count 1 t:BUFG
select -assert-count 4 t:FDRE
select -assert-count 2 t:LUT4
select -assert-count 2 t:LUT5
select -assert-count 1 t:LUT6

select -assert-none t:BUFG t:FDRE t:LUT4 t:LUT5 t:LUT6 %% t:* %D