read_verilog -icells << EOT

module top(...);

input C, R, E, S;
input [1:0] D;
output [20:0] Q;

$dff #(.CLK_POLARITY(1'b0), .WIDTH(2)) ff0 (.CLK(C), .D(D), .Q(Q[1:0]));
$dffe #(.CLK_POLARITY(1'b0), .EN_POLARITY(1'b0), .WIDTH(2)) ff1 (.CLK(C), .EN(E), .D(D), .Q(Q[3:2]));
$sdff #(.CLK_POLARITY(1'b0), .WIDTH(2), .SRST_POLARITY(1'b0), .SRST_VALUE(2'h2)) ff2 (.CLK(C), .SRST(R), .D(D), .Q(Q[5:4]));
$sdffe #(.CLK_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(2), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2)) ff3 (.CLK(C), .EN(E), .SRST(R), .D(D), .Q(Q[7:6]));
$sdffce #(.CLK_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(2), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2)) ff4 (.CLK(C), .EN(E), .SRST(R), .D(D), .Q(Q[9:8]));
$adff #(.CLK_POLARITY(1'b0), .WIDTH(2), .ARST_POLARITY(1'b0), .ARST_VALUE(2'h2)) ff5 (.CLK(C), .ARST(R), .D(D), .Q(Q[11:10]));
$adffe #(.CLK_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(2), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2)) ff6 (.CLK(C), .EN(E), .ARST(R), .D(D), .Q(Q[13:12]));
$dffsr #(.CLK_POLARITY(1'b0), .WIDTH(2), .CLR_POLARITY(1'b0), .SET_POLARITY(1'b1)) ff7 (.CLK(C), .CLR({R, S}), .SET({S, R}), .D(D), .Q(Q[15:14]));
$dffsre #(.CLK_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(2), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0)) ff8 (.CLK(C), .EN(E), .CLR({R, R}), .SET({S, S}), .D(D), .Q(Q[17:16]));

endmodule

EOT

design -save orig

equiv_opt -assert -async2sync dffunmap
design -load postopt
select -assert-none t:$sdff t:$dffe t:$adffe t:$sdffe t:$sdffce t:$dffsre
select -assert-count 5 t:$dff
select -assert-count 2 t:$adff
select -assert-count 2 t:$dffsr

design -load orig

equiv_opt -assert -async2sync dffunmap -ce-only
design -load postopt
select -assert-none t:$dffe t:$adffe t:$sdffe t:$sdffce t:$dffsre
select -assert-count 3 t:$dff
select -assert-count 2 t:$sdff
select -assert-count 2 t:$adff
select -assert-count 2 t:$dffsr

design -load orig

equiv_opt -assert -async2sync dffunmap -srst-only
design -load postopt
select -assert-none t:$sdff t:$sdffe t:$sdffce
select -assert-count 3 t:$dff
select -assert-count 2 t:$dffe
select -assert-count 1 t:$adff
select -assert-count 1 t:$adffe
select -assert-count 1 t:$dffsr
select -assert-count 1 t:$dffsre

design -load orig
simplemap

equiv_opt -assert -async2sync dffunmap
design -load postopt
select -assert-none t:$_SDFF* t:$_DFFE_* t:$_DFFSRE_*
select -assert-count 10 t:$_DFF_N_
select -assert-count 1 t:$_DFF_NP0_
select -assert-count 1 t:$_DFF_NN0_
select -assert-count 1 t:$_DFF_NP1_
select -assert-count 1 t:$_DFF_NN1_
select -assert-count 2 t:$_DFFSR_NPN_
select -assert-count 2 t:$_DFFSR_NNP_

design -load orig
simplemap

equiv_opt -assert -async2sync dffunmap -ce-only
design -load postopt
select -assert-none t:$_SDFFE_* t:$_SDFFCE_* t:$_DFFE_* t:$_DFFSRE_*
select -assert-count 6 t:$_DFF_N_
select -assert-count 1 t:$_SDFF_NP0_
select -assert-count 1 t:$_SDFF_NN0_
select -assert-count 1 t:$_SDFF_NP1_
select -assert-count 1 t:$_SDFF_NN1_
select -assert-count 1 t:$_DFF_NP0_
select -assert-count 1 t:$_DFF_NN0_
select -assert-count 1 t:$_DFF_NP1_
select -assert-count 1 t:$_DFF_NN1_
select -assert-count 2 t:$_DFFSR_NPN_
select -assert-count 2 t:$_DFFSR_NNP_

design -load orig
simplemap

equiv_opt -assert -async2sync dffunmap -srst-only
design -load postopt
select -assert-none t:$sdff t:$sdffe t:$sdffce
select -assert-count 6 t:$_DFF_N_
select -assert-count 2 t:$_DFFE_NP_
select -assert-count 2 t:$_DFFE_NN_
select -assert-count 1 t:$_DFF_NN0_
select -assert-count 1 t:$_DFF_NN1_
select -assert-count 1 t:$_DFFE_NP0P_
select -assert-count 1 t:$_DFFE_NP1P_
select -assert-count 2 t:$_DFFSR_NPN_
select -assert-count 2 t:$_DFFSRE_NNPP_