read_verilog opt_share_extend.v proc;; copy opt_share_test merged alumacc merged opt merged opt_share merged opt_clean merged miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter select -assert-count 1 -module merged t:$alu rg/iCE40/ghdl' title='iCE40/ghdl Git repository'/>
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path: root/testsuite/gna/issue691/testsuite.sh
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