read_verilog macc.v
proc
hierarchy -top top
#equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check

equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 -dsp
async2sync
equiv_opt -run prove: -assert null

design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_MAC16
select -assert-none t:SB_MAC16 %% t:* %D