read_verilog macc.v
proc
hierarchy -top top
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 41 t:LUT4
select -assert-count 6 t:CARRY
select -assert-count 7 t:DFFSR
select -assert-none t:LUT4 t:CARRY t:DFFSR %% t:* %D