module wire_example( a, b, y); input a, b; output y; wire a, b, y; assign y = a & b; endmodule lternate' title='Atom feed' href='http://git.panaceas.org/cgit/iCE40/yosys/atom/frontends/verilog/preproc.cc?h=master' type='application/atom+xml'/>
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