//----------------------------------------------------- // This is FSM demo program using function // Design Name : fsm_using_function // File Name : fsm_using_function.v //----------------------------------------------------- module fsm_using_function ( clock , // clock reset , // Active high, syn reset req_0 , // Request 0 req_1 , // Request 1 gnt_0 , // Grant 0 gnt_1 ); //-------------Input Ports----------------------------- input clock,reset,req_0,req_1; //-------------Output Ports---------------------------- output gnt_0,gnt_1; //-------------Input ports Data Type------------------- wire clock,reset,req_0,req_1; //-------------Output Ports Data Type------------------ reg gnt_0,gnt_1; //-------------Internal Constants-------------------------- parameter SIZE = 3 ; parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100 ; //-------------Internal Variables--------------------------- reg [SIZE-1:0] state ;// Seq part of the FSM wire [SIZE-1:0] next_state ;// combo part of FSM //----------Code startes Here------------------------ assign next_state = fsm_function(state, req_0, req_1); //----------Function for Combo Logic----------------- function [SIZE-1:0] fsm_function; input [SIZE-1:0] state ; input req_0 ; input req_1 ; case(state) IDLE : if (req_0 == 1'b1) begin fsm_function = GNT0; end else if (req_1 == 1'b1) begin fsm_function= GNT1; end else begin fsm_function = IDLE; end GNT0 : if (req_0 == 1'b1) begin fsm_function = GNT0; end else begin fsm_function = IDLE; end GNT1 : if (req_1 == 1'b1) begin fsm_function = GNT1; end else begin fsm_function = IDLE; end default : fsm_function = IDLE; endcase endfunction //----------Seq Logic----------------------------- always @ (posedge clock) begin : FSM_SEQ if (reset == 1'b1) begin state <= #1 IDLE; end else begin state <= #1 next_state; end end //----------Output Logic----------------------------- always @ (posedge clock) begin : OUTPUT_LOGIC if (reset == 1'b1) begin gnt_0 <= #1 1'b0; gnt_1 <= #1 1'b0; end else begin case(state) IDLE : begin gnt_0 <= #1 1'b0; gnt_1 <= #1 1'b0; end GNT0 : begin gnt_0 <= #1 1'b1; gnt_1 <= #1 1'b0; end GNT1 : begin gnt_0 <= #1 1'b0; gnt_1 <= #1 1'b1; end default : begin gnt_0 <= #1 1'b0; gnt_1 <= #1 1'b0; end endcase end end // End Of Block OUTPUT_LOGIC endmodule // End of Module arbiter ptography/tree/?id=c5b430f7ec091c02017fd07c7871ea0a4b2de044'>root/vectors/cryptography_vectors/CMAC/nist-800-38b-aes128.txt
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# AES-128-CMAC Test Vectors
# NIST SP_800-38B

COUNT = 0
KEY = 2b7e151628aed2a6abf7158809cf4f3c
MESSAGE =
OUTPUT = bb1d6929e95937287fa37d129b756746

COUNT = 1
KEY = 2b7e151628aed2a6abf7158809cf4f3c
MESSAGE = 6bc1bee22e409f96e93d7e117393172a
OUTPUT = 070a16b46b4d4144f79bdd9dd04a287c

COUNT = 2
KEY = 2b7e151628aed2a6abf7158809cf4f3c
MESSAGE = 6bc1bee22e409f96e93d7e117393172aae2d8a571e03ac9c9eb76fac45af8e5130c81c46a35ce411
OUTPUT = dfa66747de9ae63030ca32611497c827

COUNT = 3
KEY = 2b7e151628aed2a6abf7158809cf4f3c
MESSAGE = 6bc1bee22e409f96e93d7e117393172aae2d8a571e03ac9c9eb76fac45af8e5130c81c46a35ce411e5fbc1191a0a52eff69f2445df4f9b17ad2b417be66c3710
OUTPUT = 51f0bebf7e3b9d92fc49741779363cfe