//----------------------------------------------------- // This is FSM demo program using function // Design Name : fsm_using_function // File Name : fsm_using_function.v //----------------------------------------------------- module fsm_using_function ( clock , // clock reset , // Active high, syn reset req_0 , // Request 0 req_1 , // Request 1 gnt_0 , // Grant 0 gnt_1 ); //-------------Input Ports----------------------------- input clock,reset,req_0,req_1; //-------------Output Ports---------------------------- output gnt_0,gnt_1; //-------------Input ports Data Type------------------- wire clock,reset,req_0,req_1; //-------------Output Ports Data Type------------------ reg gnt_0,gnt_1; //-------------Internal Constants-------------------------- parameter SIZE = 3 ; parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100 ; //-------------Internal Variables--------------------------- reg [SIZE-1:0] state ;// Seq part of the FSM wire [SIZE-1:0] next_state ;// combo part of FSM //----------Code startes Here------------------------ assign next_state = fsm_function(state, req_0, req_1); //----------Function for Combo Logic----------------- function [SIZE-1:0] fsm_function; input [SIZE-1:0] state ; input req_0 ; input req_1 ; case(state) IDLE : if (req_0 == 1'b1) begin fsm_function = GNT0; end else if (req_1 == 1'b1) begin fsm_function= GNT1; end else begin fsm_function = IDLE; end GNT0 : if (req_0 == 1'b1) begin fsm_function = GNT0; end else begin fsm_function = IDLE; end GNT1 : if (req_1 == 1'b1) begin fsm_function = GNT1; end else begin fsm_function = IDLE; end default : fsm_function = IDLE; endcase endfunction //----------Seq Logic----------------------------- always @ (posedge clock) begin : FSM_SEQ if (reset == 1'b1) begin state <= #1 IDLE; end else begin state <= #1 next_state; end end //----------Output Logic----------------------------- always @ (posedge clock) begin : OUTPUT_LOGIC if (reset == 1'b1) begin gnt_0 <= #1 1'b0; gnt_1 <= #1 1'b0; end else begin case(state) IDLE : begin gnt_0 <= #1 1'b0; gnt_1 <= #1 1'b0; end GNT0 : begin gnt_0 <= #1 1'b1; gnt_1 <= #1 1'b0; end GNT1 : begin gnt_0 <= #1 1'b0; gnt_1 <= #1 1'b1; end default : begin gnt_0 <= #1 1'b0; gnt_1 <= #1 1'b0; end endcase end end // End Of Block OUTPUT_LOGIC endmodule // End of Module arbiter -ports.patch?h=do-work/Edimax-v2&id=a9d4bdee43e0556020b1e0c6e153e39f86e51093'>diffstats
path: root/target/linux/brcm63xx/patches-3.9/408-bcm63xx_enet-enable-rgmii-clock-on-external-ports.patch
blob: 6d0ffbb6d8e025d58ada9a90fdb94f703aff764b (plain) 
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From d8237d704fc25eb2fc25ef4403608b78c6a6d4be Mon Sep 17 00:00:00 2001
From: Jonas Gorski <jonas.gorski@gmail.com>
Date: Sun, 15 Jul 2012 20:08:57 +0200
Subject: [PATCH 54/81] bcm63xx_enet: enable rgmii clock on external ports

---
 arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |   13 +++++++++++++
 drivers/net/ethernet/broadcom/bcm63xx_enet.c      |   12 ++++++++++++
 2 files changed, 25 insertions(+), 0 deletions(-)

--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -861,6 +861,19 @@
 #define ENETSW_PORTOV_FDX_MASK		(1 << 1)
 #define ENETSW_PORTOV_LINKUP_MASK	(1 << 0)
 
+/* Port RGMII control register */
+#define ENETSW_RGMII_CTRL_REG(x)	(0x60 + (x))
+#define ENETSW_RGMII_CTRL_GMII_CLK_EN	(1 << 7)
+#define ENETSW_RGMII_CTRL_MII_OVERRIDE_EN (1 << 6)
+#define ENETSW_RGMII_CTRL_MII_MODE_MASK	(3 << 4)
+#define ENETSW_RGMII_CTRL_RGMII_MODE	(0 << 4)
+#define ENETSW_RGMII_CTRL_MII_MODE	(1 << 4)
+#define ENETSW_RGMII_CTRL_RVMII_MODE	(2 << 4)
+#define ENETSW_RGMII_CTRL_TIMING_SEL_EN	(1 << 0)
+
+/* Port RGMII timing register */
+#define ENETSW_RGMII_TIMING_REG(x)	(0x68 + (x))
+
 /* MDIO control register */
 #define ENETSW_MDIOC_REG		(0xb0)
 #define ENETSW_MDIOC_EXT_MASK		(1 << 16)
--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
@@ -2200,6 +2200,18 @@ static int bcm_enetsw_open(struct net_de
 		priv->sw_port_link[i] = 0;
 	}
 
+	/* enable external ports */
+	for (i = ENETSW_RGMII_PORT0; i < priv->num_ports; i++) {
+		u8 rgmii_ctrl;
+
+		if (!priv->used_ports[i].used)
+			continue;
+
+		rgmii_ctrl = enetsw_readb(priv, ENETSW_RGMII_CTRL_REG(i));
+		rgmii_ctrl |= ENETSW_RGMII_CTRL_GMII_CLK_EN;
+		enetsw_writeb(priv, rgmii_ctrl, ENETSW_RGMII_CTRL_REG(i));
+	}
+
 	/* reset mib */
 	val = enetsw_readb(priv, ENETSW_GMCR_REG);
 	val |= ENETSW_GMCR_RST_MIB_MASK;