read_verilog ../common/adffs.v
design -save read

hierarchy -top adff
proc
equiv_opt -async2sync -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:FD1P3DX
select -assert-none t:FD1P3DX t:IB t:OB t:VLO t:VHI %% t:* %D

design -load read
hierarchy -top adffn
proc
equiv_opt -async2sync -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adffn # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:FD1P3DX
select -assert-count 1 t:INV
select -assert-none t:FD1P3DX t:INV t:LUT4 t:IB t:OB t:VLO t:VHI %% t:* %D

design -load read
hierarchy -top dffs
proc
equiv_opt -async2sync -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffs # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:FD1P3IX
select -assert-count 1 t:LUT4
select -assert-none t:FD1P3IX t:LUT4 t:IB t:OB t:VLO t:VHI %% t:* %D

design -load read
hierarchy -top ndffnr
proc
equiv_opt -async2sync -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd ndffnr # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:FD1P3IX
select -assert-count 2 t:INV
select -assert-none t:FD1P3IX t:INV t:LUT4 t:IB t:OB t:VLO t:VHI %% t:* %D