read_verilog -D NO_INIT ../common/adffs.v
design -save read

hierarchy -top adff
proc
equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adff # Constrain all select calls below inside the top module
select -assert-count 1 t:CC_BUFG
select -assert-count 1 t:CC_DFF
select -assert-none t:CC_BUFG t:CC_DFF %% t:* %D

design -load read
hierarchy -top adffn
proc
equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adffn # Constrain all select calls below inside the top module
select -assert-count 1 t:CC_BUFG
select -assert-count 1 t:CC_DFF
select -assert-none t:CC_BUFG t:CC_DFF %% t:* %D

design -load read
hierarchy -top dffs
proc
equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffs # Constrain all select calls below inside the top module
select -assert-count 1 t:CC_BUFG
select -assert-count 1 t:CC_DFF
select -assert-max 1 t:CC_LUT2
select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 %% t:* %D

design -load read
hierarchy -top ndffnr
proc
equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd ndffnr # Constrain all select calls below inside the top module
select -assert-count 1 t:CC_BUFG
select -assert-count 1 t:CC_DFF
select -assert-max 1 t:CC_LUT2
select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 %% t:* %D