module dff ( input d, clk, output reg q ); always @( posedge clk ) q <= d; endmodule module dffe( input d, clk, en, output reg q ); initial begin q = 0; end always @( posedge clk ) if ( en ) q <= d; endmodule ys/atom/examples/intel/MAX10/runme_postsynth?h=master' type='application/atom+xml'/>
aboutsummaryrefslogtreecommitdiffstats
path: root/examples/intel/MAX10/runme_postsynth
blob: f1621054062a51b45fc4429c9d1fe70ae6bd51e5 (plain) 
1
2
3
4
5