read_verilog ../common/add_sub.v hierarchy -top top proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 10 t:AL_MAP_ADDER select -assert-count 4 t:AL_MAP_LUT1 select -assert-none t:AL_MAP_LUT1 t:AL_MAP_ADDER %% t:* %D t' href='ssh://git@git.panaceas.org/git/iCE40/ghdl' title='iCE40/ghdl Git repository'/>
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