/techlibs/xilinx/
../
.gitignore
Makefile.inc
abc_map.v
abc_model.v
abc_unmap.v
abc_xc7.box
abc_xc7.lut
abc_xc7_nowide.lut
arith_map.v
brams_init.py
cells_map.v
cells_sim.v
cells_xtra.py
dsp_map.v
lut_map.v
lutrams.txt
lutrams_map.v
mux_map.v
synth_xilinx.cc
tests
xc6s_brams.txt
xc6s_brams_bb.v
xc6s_brams_map.v
xc6s_cells_xtra.v
xc6s_ff_map.v
xc6v_cells_xtra.v
xc7_brams.txt
xc7_brams_bb.v
xc7_brams_map.v
xc7_cells_xtra.v
xc7_ff_map.v
xcu_cells_xtra.v