/*
 *  yosys -- Yosys Open SYnthesis Suite
 *
 *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
 *                2019  Eddie Hung    <eddie@fpgeh.com>
 *
 *  Permission to use, copy, modify, and/or distribute this software for any
 *  purpose with or without fee is hereby granted, provided that the above
 *  copyright notice and this permission notice appear in all copies.
 *
 *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */

// The following techmapping rules are intended to be run (with -max_iter 1)
//   before invoking the `abc9` pass in order to transform the design into
//   a format that it understands.

`ifdef DFF_MODE
// For example, (complex) flip-flops are expected to be described as an
//   combinatorial box (containing all control logic such as clock enable
//   or synchronous resets) followed by a basic D-Q flop.
// Yosys will automatically analyse the simulation model (described in
//   cells_sim.v) and detach any $_DFF_P_ or $_DFF_N_ cells present in
//   order to extract the combinatorial control logic left behind.
//   Specifically, a simulation model similar to the one below:
//
//                ++===================================++
//                ||                        Sim model  ||
//                ||      /\/\/\/\                     ||
//            D -->>-----<        >     +------+       ||
//            R -->>-----<  Comb. >     |$_DFF_|       ||
//           CE -->>-----<  logic >-----| [NP]_|---+---->>-- Q
//                ||  +--<        >     +------+   |   ||
//                ||  |   \/\/\/\/                 |   ||
//                ||  |                            |   ||
//                ||  +----------------------------+   ||
//                ||                                   ||
//                ++===================================++
//
//   is transformed into:
//
//                ++==================++
//                ||         Comb box ||
//                ||                  ||
//                ||      /\/\/\/\    ||
//           D  -->>-----<        >   ||
//           R  -->>-----<  Comb. >   ||        +-----------+
//          CE  -->>-----<  logic >--->>-- $Q --|$__ABC9_FF_|--+-->> Q
//   abc9_ff.Q +-->>-----<        >   ||        +-----------+  |
//             |  ||      \/\/\/\/    ||                       |
//             |  ||                  ||                       |
//             |  ++==================++                       |
//             |                                               |
//             +-----------------------------------------------+
//
// The purpose of the following FD* rules are to wrap the flop with:
// (a) a special $__ABC9_FF_ in front of the FD*'s output, indicating to abc9
//     the connectivity of its basic D-Q flop
// (b) an optional $__ABC9_ASYNC_ cell in front of $__ABC_FF_'s output to
//     capture asynchronous behaviour
// (c) a special abc9_ff.clock wire to capture its clock domain and polarity
//     (indicated to `abc9' so that it only performs sequential synthesis
//     (with reachability analysis) correctly on one domain at a time)
// (d) an (* abc9_init *) attribute on the $__ABC9_FF_ cell capturing its
//     initial state
//     NOTE: in order to perform sequential synthesis, `abc9' requires that
//     the initial value of all flops be zero
// (e) a special _TECHMAP_REPLACE_.abc9_ff.Q wire that will be used for feedback
//     into the (combinatorial) FD* cell to facilitate clock-enable behaviour

module FDRE (output Q, (* techmap_autopurge *) input C, CE, D, R);
  parameter [0:0] INIT = 1'b0;
  parameter [0:0] IS_C_INVERTED = 1'b0;
  parameter [0:0] IS_D_INVERTED = 1'b0;
  parameter [0:0] IS_R_INVERTED = 1'b0;
  wire QQ, $Q;
  generate if (INIT == 1'b1) begin
    assign Q = ~QQ;
    FDSE #(
      .INIT(1'b0),
      .IS_C_INVERTED(IS_C_INVERTED),
      .IS_D_INVERTED(IS_D_INVERTED),
      .IS_S_INVERTED(IS_R_INVERTED)
    ) _TECHMAP_REPLACE_ (
      .D(~D), .Q($Q), .C(C), .CE(CE), .S(R)
    );
  end
  else begin
    assign Q = QQ;
    FDRE #(
      .INIT(1'b0),
      .IS_C_INVERTED(IS_C_INVERTED),
      .IS_D_INVERTED(IS_D_INVERTED),
      .IS_R_INVERTED(IS_R_INVERTED)
    ) _TECHMAP_REPLACE_ (
      .D(D), .Q($Q), .C(C), .CE(CE), .R(R)
    );
  end
  endgenerate
  (* abc9_init = 1'b0 *)
  $__ABC9_FF_ abc9_ff (.D($Q), .Q(QQ));

  // Special signals
  wire [1:0] abc9_ff.clock = {C, IS_C_INVERTED};
  wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ;
endmodule
module FDRE_1 (output Q, (* techmap_autopurge *) input C, CE, D, R);
  parameter [0:0] INIT = 1'b0;
  wire QQ, $Q;
  generate if (INIT == 1'b1) begin
    assign Q = ~QQ;
    FDSE_1 #(
      .INIT(1'b0)
    ) _TECHMAP_REPLACE_ (
      .D(~D), .Q($Q), .C(C), .CE(CE), .S(R)
    );
  end
  else begin
    assign Q = QQ;
    FDRE_1 #(
      .INIT(1'b0)
    ) _TECHMAP_REPLACE_ (
      .D(D), .Q($Q), .C(C), .CE(CE), .R(R)
    );
  end
  endgenerate
  (* abc9_init = 1'b0 *)
  $__ABC9_FF_ abc9_ff (.D($Q), .Q(QQ));

  // Special signals
  wire [1:0] abc9_ff.clock = {C, 1'b1 /* IS_C_INVERTED */};
  wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ;
endmodule

module FDSE (output Q, (* techmap_autopurge *) input C, CE, D, S);
  parameter [0:0] INIT = 1'b1;
  parameter [0:0] IS_C_INVERTED = 1'b0;
  parameter [0:0] IS_D_INVERTED = 1'b0;
  parameter [0:0] IS_S_INVERTED = 1'b0;
  wire QQ, $Q;
  generate if (INIT == 1'b1) begin
    assign Q = ~QQ;
    FDRE #(
      .INIT(1'b0),
      .IS_C_INVERTED(IS_C_INVERTED),
      .IS_D_INVERTED(IS_D_INVERTED),
      .IS_R_INVERTED(IS_S_INVERTED)
    ) _TECHMAP_REPLACE_ (
      .D(~D), .Q($Q), .C(C), .CE(CE), .R(S)
    );
  end
  else begin
    assign Q = QQ;
    FDSE #(
      .INIT(1'b0),
      .IS_C_INVERTED(IS_C_INVERTED),
      .IS_D_INVERTED(IS_D_INVERTED),
      .IS_S_INVERTED(IS_S_INVERTED)
    ) _TECHMAP_REPLACE_ (
      .D(D), .Q($Q), .C(C), .CE(CE), .S(S)
    );
  end endgenerate
  (* abc9_init = 1'b0 *)
  $__ABC9_FF_ abc9_ff (.D($Q), .Q(QQ));

  // Special signals
  wire [1:0] abc9_ff.clock = {C, IS_C_INVERTED};
  wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ;
endmodule
module FDSE_1 (output Q, (* techmap_autopurge *) input C, CE, D, S);
  parameter [0:0] INIT = 1'b1;
  wire QQ, $Q;
  generate if (INIT == 1'b1) begin
    assign Q = ~QQ;
    FDRE_1 #(
      .INIT(1'b0)
    ) _TECHMAP_REPLACE_ (
      .D(~D), .Q($Q), .C(C), .CE(CE), .R(S)
    );
  end
  else begin
    assign Q = QQ;
    FDSE_1 #(
      .INIT(1'b0)
    ) _TECHMAP_REPLACE_ (
      .D(D), .Q($Q), .C(C), .CE(CE), .S(S)
    );
  end endgenerate
  (* abc9_init = 1'b0 *)
  $__ABC9_FF_ abc9_ff (.D($Q), .Q(QQ));

  // Special signals
  wire [1:0] abc9_ff.clock = {C, 1'b1 /* IS_C_INVERTED */};
  wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = QQ;
endmodule

module FDCE (output Q, (* techmap_autopurge *) input C, CE, D, CLR);
  parameter [0:0] INIT = 1'b0;
  parameter [0:0] IS_C_INVERTED = 1'b0;
  parameter [0:0] IS_D_INVERTED = 1'b0;
  parameter [0:0] IS_CLR_INVERTED = 1'b0;
  wire QQ, $Q, $QQ;
  generate if (INIT == 1'b1) begin
    assign Q = ~QQ;
    FDPE #(
      .INIT(1'b0),
      .IS_C_INVERTED(IS_C_INVERTED),
      .IS_D_INVERTED(IS_D_INVERTED),
      .IS_PRE_INVERTED(IS_CLR_INVERTED)
    ) _TECHMAP_REPLACE_ (
      .D(~D), .Q($Q), .C(C), .CE(CE), .PRE(CLR)
                                        // ^^^ Note that async
                                        //     control is not directly
                                        //     supported by abc9 but its
                                        //     behaviour is captured by
                                        //     $__ABC9_ASYNC1 below
    );
    // Since this is an async flop, async behaviour is dealt with here
    $__ABC9_ASYNC1 abc_async (.A($QQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ));
  end
  else begin
    assign Q = QQ;
    FDCE #(
      .INIT(1'b0),
      .IS_C_INVERTED(IS_C_INVERTED),
      .IS_D_INVERTED(IS_D_INVERTED),
      .IS_CLR_INVERTED(IS_CLR_INVERTED)
    ) _TECHMAP_REPLACE_ (
      .D(D), .Q($Q), .C(C), .CE(CE), .CLR(CLR)
                                       // ^^^ Note that async
                                       //     control is not directly
                                       //     supported by abc9 but its
                                       //     behaviour is captured by
                                       //     $__ABC9_ASYNC0 below
    );
    // Since this is an async flop, async behaviour is dealt with here
    $__ABC9_ASYNC0 abc_async (.A($QQ), .S(CLR ^ IS_CLR_INVERTED), .Y(QQ));
  end endgenerate
  (* abc9_init = 1'b0 *)
  $__ABC9_FF_ abc9_ff (.D($Q), .Q($QQ));

  // Special signals
  wire [1:0] abc9_ff.clock = {C, IS_C_INVERTED};
  wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ;
endmodule
module FDCE_1 (output Q, (* techmap_autopurge *) input C, CE, D, CLR);
  parameter [0:0] INIT = 1'b0;
  wire QQ, $Q, $QQ;
  generate if (INIT == 1'b1) begin
    assign Q = ~QQ;
    FDPE_1 #(
      .INIT(1'b0)
    ) _TECHMAP_REPLACE_ (
      .D(~D), .Q($Q), .C(C), .CE(CE), .PRE(CLR)
                                        // ^^^ Note that async
                                        //     control is not directly
                                        //     supported by abc9 but its
                                        //     behaviour is captured by
                                        //     $__ABC9_ASYNC1 below
    );
    $__ABC9_ASYNC1 abc_async (.A($QQ), .S(CLR), .Y(QQ));
  end
  else begin
    assign Q = QQ;
    FDCE_1 #(
      .INIT(1'b0)
    ) _TECHMAP_REPLACE_ (
      .D(D), .Q($Q), .C(C), .CE(CE), .CLR(CLR)
                                       // ^^^ Note that async
                                       //     control is not directly
                                       //     supported by abc9 but its
                                       //     behaviour is captured by
                                       //     $__ABC9_ASYNC0 below
    );
    $__ABC9_ASYNC0 abc_async (.A($QQ), .S(CLR), .Y(QQ));
  end endgenerate
  (* abc9_init = 1'b0 *)
  $__ABC9_FF_ abc9_ff (.D($Q), .Q($QQ));

  // Special signals
  wire [1:0] abc9_ff.clock = {C, 1'b1 /* IS_C_INVERTED */};
  wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ;
endmodule

module FDPE (output Q, (* techmap_autopurge *) input C, CE, D, PRE);
  parameter [0:0] INIT = 1'b1;
  parameter [0:0] IS_C_INVERTED = 1'b0;
  parameter [0:0] IS_D_INVERTED = 1'b0;
  parameter [0:0] IS_PRE_INVERTED = 1'b0;
  wire QQ, $Q, $QQ;
  generate if (INIT == 1'b1) begin
    assign Q = ~QQ;
    FDCE #(
      .INIT(1'b0),
      .IS_C_INVERTED(IS_C_INVERTED),
      .IS_D_INVERTED(IS_D_INVERTED),
      .IS_CLR_INVERTED(IS_PRE_INVERTED),
    ) _TECHMAP_REPLACE_ (
      .D(~D), .Q($Q), .C(C), .CE(CE), .CLR(PRE)
                                        // ^^^ Note that async
                                        //     control is not directly
                                        //     supported by abc9 but its
                                        //     behaviour is captured by
                                        //     $__ABC9_ASYNC0 below
    );
    $__ABC9_ASYNC0 abc_async (.A($QQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ));
  end
  else begin
    assign Q = QQ;
    FDPE #(
      .INIT(1'b0),
      .IS_C_INVERTED(IS_C_INVERTED),
      .IS_D_INVERTED(IS_D_INVERTED),
      .IS_PRE_INVERTED(IS_PRE_INVERTED),
    ) _TECHMAP_REPLACE_ (
      .D(D), .Q($Q), .C(C), .CE(CE), .PRE(PRE)
                                       // ^^^ Note that async
                                       //     control is not directly
                                       //     supported by abc9 but its
                                       //     behaviour is captured by
                                       //     $__ABC9_ASYNC1 below
    );
    $__ABC9_ASYNC1 abc_async (.A($QQ), .S(PRE ^ IS_PRE_INVERTED), .Y(QQ));
  end endgenerate
  (* abc9_init = 1'b0 *)
  $__ABC9_FF_ abc9_ff (.D($Q), .Q($QQ));

  // Special signals
  wire [1:0] abc9_ff.clock = {C, IS_C_INVERTED};
  wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ;
endmodule
module FDPE_1 (output Q, (* techmap_autopurge *) input C, CE, D, PRE);
  parameter [0:0] INIT = 1'b1;
  wire QQ, $Q, $QQ;
  generate if (INIT == 1'b1) begin
    assign Q = ~QQ;
    FDCE_1 #(
      .INIT(1'b0)
    ) _TECHMAP_REPLACE_ (
      .D(~D), .Q($Q), .C(C), .CE(CE), .CLR(PRE)
                                        // ^^^ Note that async
                                        //     control is not directly
                                        //     supported by abc9 but its
                                        //     behaviour is captured by
                                        //     $__ABC9_ASYNC0 below
    );
    $__ABC9_ASYNC0 abc_async (.A($QQ), .S(PRE), .Y(QQ));
  end
  else begin
    assign Q = QQ;
    FDPE_1 #(
      .INIT(1'b0)
    ) _TECHMAP_REPLACE_ (
      .D(D), .Q($Q), .C(C), .CE(CE), .PRE(PRE)
                                       // ^^^ Note that async
                                       //     control is not directly
                                       //     supported by abc9 but its
                                       //     behaviour is captured by
                                       //     $__ABC9_ASYNC1 below
    );
    $__ABC9_ASYNC1 abc_async (.A($QQ), .S(PRE), .Y(QQ));
  end endgenerate
  (* abc9_init = 1'b0 *)
  $__ABC9_FF_ abc9_ff (.D($Q), .Q($QQ));

  // Special signals
  wire [1:0] abc9_ff.clock = {C, 1'b1 /* IS_C_INVERTED */};
  wire [0:0] _TECHMAP_REPLACE_.abc9_ff.Q = $QQ;
endmodule
`endif

// Attach a (combinatorial) black-box onto the output
//   of thes LUTRAM primitives to capture their
//   asynchronous read behaviour
module RAM32X1D (
  output DPO, SPO,
  (* techmap_autopurge *) input  D,
  (* techmap_autopurge *) input  WCLK,
  (* techmap_autopurge *) input  WE,
  (* techmap_autopurge *) input  A0, A1, A2, A3, A4,
  (* techmap_autopurge *) input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
);
  parameter INIT = 32'h0;
  parameter IS_WCLK_INVERTED = 1'b0;
  wire $DPO, $SPO;
  RAM32X1D #(
    .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
  ) _TECHMAP_REPLACE_ (
    .DPO($DPO), .SPO($SPO),
    .D(D), .WCLK(WCLK), .WE(WE),
    .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
    .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
  );
  $__ABC9_RAM6 spo (.A($SPO), .S({1'b1, A4, A3, A2, A1, A0}), .Y(SPO));
  $__ABC9_RAM6 dpo (.A($DPO), .S({1'b1, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
endmodule

module RAM64X1D (
  output DPO, SPO,
  (* techmap_autopurge *) input  D,
  (* techmap_autopurge *) input  WCLK,
  (* techmap_autopurge *) input  WE,
  (* techmap_autopurge *) input  A0, A1, A2, A3, A4, A5,
  (* techmap_autopurge *) input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
);
  parameter INIT = 64'h0;
  parameter IS_WCLK_INVERTED = 1'b0;
  wire $DPO, $SPO;
  RAM64X1D #(
    .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
  ) _TECHMAP_REPLACE_ (
    .DPO($DPO), .SPO($SPO),
    .D(D), .WCLK(WCLK), .WE(WE),
    .A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5),
    .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5)
  );
  $__ABC9_RAM6 spo (.A($SPO), .S({A5, A4, A3, A2, A1, A0}), .Y(SPO));
  $__ABC9_RAM6 dpo (.A($DPO), .S({DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
endmodule

module RAM128X1D (
  output       DPO, SPO,
  (* techmap_autopurge *) input        D,
  (* techmap_autopurge *) input        WCLK,
  (* techmap_autopurge *) input        WE,
  (* techmap_autopurge *) input  [6:0] A, DPRA
);
  parameter INIT = 128'h0;
  parameter IS_WCLK_INVERTED = 1'b0;
  wire $DPO, $SPO;
  RAM128X1D #(
    .INIT(INIT), .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
  ) _TECHMAP_REPLACE_ (
    .DPO($DPO), .SPO($SPO),
    .D(D), .WCLK(WCLK), .WE(WE),
    .A(A),
    .DPRA(DPRA)
  );
  $__ABC9_RAM7 spo (.A($SPO), .S(A), .Y(SPO));
  $__ABC9_RAM7 dpo (.A($DPO), .S(DPRA), .Y(DPO));
endmodule

module RAM32M (
  output [1:0] DOA,
  output [1:0] DOB,
  output [1:0] DOC,
  output [1:0] DOD,
  (* techmap_autopurge *) input [4:0] ADDRA,
  (* techmap_autopurge *) input [4:0] ADDRB,
  (* techmap_autopurge *) input [4:0] ADDRC,
  (* techmap_autopurge *) input [4:0] ADDRD,
  (* techmap_autopurge *) input [1:0] DIA,
  (* techmap_autopurge *) input [1:0] DIB,
  (* techmap_autopurge *) input [1:0] DIC,
  (* techmap_autopurge *) input [1:0] DID,
  (* techmap_autopurge *) input WCLK,
  (* techmap_autopurge *) input WE
);
  parameter [63:0] INIT_A = 64'h0000000000000000;
  parameter [63:0] INIT_B = 64'h0000000000000000;
  parameter [63:0] INIT_C = 64'h0000000000000000;
  parameter [63:0] INIT_D = 64'h0000000000000000;
  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
  wire [1:0] $DOA, $DOB, $DOC, $DOD;
  RAM32M #(
    .INIT_A(INIT_A), .INIT_B(INIT_B), .INIT_C(INIT_C), .INIT_D(INIT_D),
    .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
  ) _TECHMAP_REPLACE_ (
    .DOA($DOA), .DOB($DOB), .DOC($DOC), .DOD($DOD),
    .WCLK(WCLK), .WE(WE),
    .ADDRA(ADDRA), .ADDRB(ADDRB), .ADDRC(ADDRC), .ADDRD(ADDRD),
    .DIA(DIA), .DIB(DIB), .DIC(DIC), .DID(DID)
  );
  $__ABC9_RAM6 doa0 (.A($DOA[0]), .S({1'b1, ADDRA}), .Y(DOA[0]));
  $__ABC9_RAM6 doa1 (.A($DOA[1]), .S({1'b1, ADDRA}), .Y(DOA[1]));
  $__ABC9_RAM6 dob0 (.A($DOB[0]), .S({1'b1, ADDRB}), .Y(DOB[0]));
  $__ABC9_RAM6 dob1 (.A($DOB[1]), .S({1'b1, ADDRB}), .Y(DOB[1]));
  $__ABC9_RAM6 doc0 (.A($DOC[0]), .S({1'b1, ADDRC}), .Y(DOC[0]));
  $__ABC9_RAM6 doc1 (.A($DOC[1]), .S({1'b1, ADDRC}), .Y(DOC[1]));
  $__ABC9_RAM6 dod0 (.A($DOD[0]), .S({1'b1, ADDRD}), .Y(DOD[0]));
  $__ABC9_RAM6 dod1 (.A($DOD[1]), .S({1'b1, ADDRD}), .Y(DOD[1]));
endmodule

module RAM64M (
  output DOA,
  output DOB,
  output DOC,
  output DOD,
  (* techmap_autopurge *) input [5:0] ADDRA,
  (* techmap_autopurge *) input [5:0] ADDRB,
  (* techmap_autopurge *) input [5:0] ADDRC,
  (* techmap_autopurge *) input [5:0] ADDRD,
  (* techmap_autopurge *) input DIA,
  (* techmap_autopurge *) input DIB,
  (* techmap_autopurge *) input DIC,
  (* techmap_autopurge *) input DID,
  (* techmap_autopurge *) input WCLK,
  (* techmap_autopurge *) input WE
);
  parameter [63:0] INIT_A = 64'h0000000000000000;
  parameter [63:0] INIT_B = 64'h0000000000000000;
  parameter [63:0] INIT_C = 64'h0000000000000000;
  parameter [63:0] INIT_D = 64'h0000000000000000;
  parameter [0:0] IS_WCLK_INVERTED = 1'b0;
  wire $DOA, $DOB, $DOC, $DOD;
  RAM64M #(
    .INIT_A(INIT_A), .INIT_B(INIT_B), .INIT_C(INIT_C), .INIT_D(INIT_D),
    .IS_WCLK_INVERTED(IS_WCLK_INVERTED)
  ) _TECHMAP_REPLACE_ (
    .DOA($DOA), .DOB($DOB), .DOC($DOC), .DOD($DOD),
    .WCLK(WCLK), .WE(WE),
    .ADDRA(ADDRA), .ADDRB(ADDRB), .ADDRC(ADDRC), .ADDRD(ADDRD),
    .DIA(DIA), .DIB(DIB), .DIC(DIC), .DID(DID)
  );
  $__ABC9_RAM6 doa (.A($DOA), .S(ADDRA), .Y(DOA));
  $__ABC9_RAM6 dob (.A($DOB), .S(ADDRB), .Y(DOB));
  $__ABC9_RAM6 doc (.A($DOC), .S(ADDRC), .Y(DOC));
  $__ABC9_RAM6 dod (.A($DOD), .S(ADDRD), .Y(DOD));
endmodule

module SRL16 (
  output Q,
  (* techmap_autopurge *) input A0, A1, A2, A3, CLK, D
);
  parameter [15:0] INIT = 16'h0000;
  wire $Q;
  SRL16 #(
    .INIT(INIT),
  ) _TECHMAP_REPLACE_ (
    .Q($Q),
    .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CLK(CLK), .D(D)
  );
  $__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
endmodule

module SRL16E (
  output Q,
  (* techmap_autopurge *) input A0, A1, A2, A3, CE, CLK, D
);
  parameter [15:0] INIT = 16'h0000;
  parameter [0:0] IS_CLK_INVERTED = 1'b0;
  wire $Q;
  SRL16E #(
    .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
  ) _TECHMAP_REPLACE_ (
    .Q($Q),
    .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
  );
  $__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
endmodule

module SRLC16 (
  output Q, Q15,
  (* techmap_autopurge *) input A0, A1, A2, A3, CLK, D
);
  parameter [15:0] INIT = 16'h0000;
  wire $Q;
  SRLC16 #(
    .INIT(INIT),
  ) _TECHMAP_REPLACE_ (
    .Q($Q), .Q(Q15),
    .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CLK(CLK), .D(D)
  );
  $__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
endmodule

module SRLC16E (
  output Q, Q15,
  (* techmap_autopurge *) input A0, A1, A2, A3, CE, CLK, D
);
  parameter [15:0] INIT = 16'h0000;
  parameter [0:0] IS_CLK_INVERTED = 1'b0;
  wire $Q;
  SRLC16E #(
    .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
  ) _TECHMAP_REPLACE_ (
    .Q($Q), .Q(Q15),
    .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
  );
  $__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
endmodule

module SRLC32E (
  output Q,
  output Q31,
  (* techmap_autopurge *) input [4:0] A,
  (* techmap_autopurge *) input CE, CLK, D
);
  parameter [31:0] INIT = 32'h00000000;
  parameter [0:0] IS_CLK_INVERTED = 1'b0;
  wire $Q;
  SRLC32E #(
    .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
  ) _TECHMAP_REPLACE_ (
    .Q($Q), .Q31(Q31),
    .A(A), .CE(CE), .CLK(CLK), .D(D)
  );
  $__ABC9_RAM6 q (.A($Q), .S({1'b1, A}), .Y(Q));
endmodule

module DSP48E1 (
    (* techmap_autopurge *) output [29:0] ACOUT,
    (* techmap_autopurge *) output [17:0] BCOUT,
    (* techmap_autopurge *) output reg CARRYCASCOUT,
    (* techmap_autopurge *) output reg [3:0] CARRYOUT,
    (* techmap_autopurge *) output reg MULTSIGNOUT,
    (* techmap_autopurge *) output OVERFLOW,
    (* techmap_autopurge *) output reg signed [47:0] P,
    (* techmap_autopurge *) output PATTERNBDETECT,
    (* techmap_autopurge *) output PATTERNDETECT,
    (* techmap_autopurge *) output [47:0] PCOUT,
    (* techmap_autopurge *) output UNDERFLOW,
    (* techmap_autopurge *) input signed [29:0] A,
    (* techmap_autopurge *) input [29:0] ACIN,
    (* techmap_autopurge *) input [3:0] ALUMODE,
    (* techmap_autopurge *) input signed [17:0] B,
    (* techmap_autopurge *) input [17:0] BCIN,
    (* techmap_autopurge *) input [47:0] C,
    (* techmap_autopurge *) input CARRYCASCIN,
    (* techmap_autopurge *) input CARRYIN,
    (* techmap_autopurge *) input [2:0] CARRYINSEL,
    (* techmap_autopurge *) input CEA1,
    (* techmap_autopurge *) input CEA2,
    (* techmap_autopurge *) input CEAD,
    (* techmap_autopurge *) input CEALUMODE,
    (* techmap_autopurge *) input CEB1,
    (* techmap_autopurge *) input CEB2,
    (* techmap_autopurge *) input CEC,
    (* techmap_autopurge *) input CECARRYIN,
    (* techmap_autopurge *) input CECTRL,
    (* techmap_autopurge *) input CED,
    (* techmap_autopurge *) input CEINMODE,
    (* techmap_autopurge *) input CEM,
    (* techmap_autopurge *) input CEP,
    (* techmap_autopurge *) input CLK,
    (* techmap_autopurge *) input [24:0] D,
    (* techmap_autopurge *) input [4:0] INMODE,
    (* techmap_autopurge *) input MULTSIGNIN,
    (* techmap_autopurge *) input [6:0] OPMODE,
    (* techmap_autopurge *) input [47:0] PCIN,
    (* techmap_autopurge *) input RSTA,
    (* techmap_autopurge *) input RSTALLCARRYIN,
    (* techmap_autopurge *) input RSTALUMODE,
    (* techmap_autopurge *) input RSTB,
    (* techmap_autopurge *) input RSTC,
    (* techmap_autopurge *) input RSTCTRL,
    (* techmap_autopurge *) input RSTD,
    (* techmap_autopurge *) input RSTINMODE,
    (* techmap_autopurge *) input RSTM,
    (* techmap_autopurge *) input RSTP
);
    parameter integer ACASCREG = 1;
    parameter integer ADREG = 1;
    parameter integer ALUMODEREG = 1;
    parameter integer AREG = 1;
    parameter AUTORESET_PATDET = "NO_RESET";
    parameter A_INPUT = "DIRECT";
    parameter integer BCASCREG = 1;
    parameter integer BREG = 1;
    parameter B_INPUT = "DIRECT";
    parameter integer CARRYINREG = 1;
    parameter integer CARRYINSELREG = 1;
    parameter integer CREG = 1;
    parameter integer DREG = 1;
    parameter integer INMODEREG = 1;
    parameter integer MREG = 1;
    parameter integer OPMODEREG = 1;
    parameter integer PREG = 1;
    parameter SEL_MASK = "MASK";
    parameter SEL_PATTERN = "PATTERN";
    parameter USE_DPORT = "FALSE";
    parameter USE_MULT = "MULTIPLY";
    parameter USE_PATTERN_DETECT = "NO_PATDET";
    parameter USE_SIMD = "ONE48";
    parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
    parameter [47:0] PATTERN = 48'h000000000000;
    parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
    parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
    parameter [0:0] IS_CLK_INVERTED = 1'b0;
    parameter [4:0] IS_INMODE_INVERTED = 5'b0;
    parameter [6:0] IS_OPMODE_INVERTED = 7'b0;

    wire [47:0] $P, $PCOUT;

    DSP48E1 #(
        .ACASCREG(ACASCREG),
        .ADREG(ADREG),
        .ALUMODEREG(ALUMODEREG),
        .AREG(AREG),
        .AUTORESET_PATDET(AUTORESET_PATDET),
        .A_INPUT(A_INPUT),
        .BCASCREG(BCASCREG),
        .BREG(BREG),
        .B_INPUT(B_INPUT),
        .CARRYINREG(CARRYINREG),
        .CARRYINSELREG(CARRYINSELREG),
        .CREG(CREG),
        .DREG(DREG),
        .INMODEREG(INMODEREG),
        .MREG(MREG),
        .OPMODEREG(OPMODEREG),
        .PREG(PREG),
        .SEL_MASK(SEL_MASK),
        .SEL_PATTERN(SEL_PATTERN),
        .USE_DPORT(USE_DPORT),
        .USE_MULT(USE_MULT),
        .USE_PATTERN_DETECT(USE_PATTERN_DETECT),
        .USE_SIMD(USE_SIMD),
        .MASK(MASK),
        .PATTERN(PATTERN),
        .IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED),
        .IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED),
        .IS_CLK_INVERTED(IS_CLK_INVERTED),
        .IS_INMODE_INVERTED(IS_INMODE_INVERTED),
        .IS_OPMODE_INVERTED(IS_OPMODE_INVERTED)
    ) _TECHMAP_REPLACE_ (
        .ACOUT(ACOUT),
        .BCOUT(BCOUT),
        .CARRYCASCOUT(CARRYCASCOUT),
        .CARRYOUT(CARRYOUT),
        .MULTSIGNOUT(MULTSIGNOUT),
        .OVERFLOW(OVERFLOW),
        .P($P),
        .PATTERNBDETECT(PATTERNBDETECT),
        .PATTERNDETECT(PATTERNDETECT),
        .PCOUT($PCOUT),
        .UNDERFLOW(UNDERFLOW),
        .A(A),
        .ACIN(ACIN),
        .ALUMODE(ALUMODE),
        .B(B),
        .BCIN(BCIN),
        .C(C),
        .CARRYCASCIN(CARRYCASCIN),
        .CARRYIN(CARRYIN),
        .CARRYINSEL(CARRYINSEL),
        .CEA1(CEA1),
        .CEA2(CEA2),
        .CEAD(CEAD),
        .CEALUMODE(CEALUMODE),
        .CEB1(CEB1),
        .CEB2(CEB2),
        .CEC(CEC),
        .CECARRYIN(CECARRYIN),
        .CECTRL(CECTRL),
        .CED(CED),
        .CEINMODE(CEINMODE),
        .CEM(CEM),
        .CEP(CEP),
        .CLK(CLK),
        .D(D),
        .INMODE(INMODE),
        .MULTSIGNIN(MULTSIGNIN),
        .OPMODE(OPMODE),
        .PCIN(PCIN),
        .RSTA(RSTA),
        .RSTALLCARRYIN(RSTALLCARRYIN),
        .RSTALUMODE(RSTALUMODE),
        .RSTB(RSTB),
        .RSTC(RSTC),
        .RSTCTRL(RSTCTRL),
        .RSTD(RSTD),
        .RSTINMODE(RSTINMODE),
        .RSTM(RSTM),
        .RSTP(RSTP)
    );
    $__ABC9_DSP48E1 #(
        .ADREG(ADREG),
        .AREG(AREG),
        .BREG(BREG),
        .CREG(CREG),
        .DREG(DREG),
        .MREG(MREG),
        .PREG(PREG),
        .USE_DPORT(USE_DPORT),
        .USE_MULT(USE_MULT)
    ) dsp_comb (
        .$A(A), .$B(B), .$C(C), .$D(D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT));
endmodule
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<a id='n920' href='#n920'>920</a>
<a id='n921' href='#n921'>921</a>
<a id='n922' href='#n922'>922</a>
<a id='n923' href='#n923'>923</a>
<a id='n924' href='#n924'>924</a>
<a id='n925' href='#n925'>925</a>
<a id='n926' href='#n926'>926</a>
<a id='n927' href='#n927'>927</a>
<a id='n928' href='#n928'>928</a>
<a id='n929' href='#n929'>929</a>
<a id='n930' href='#n930'>930</a>
<a id='n931' href='#n931'>931</a>
<a id='n932' href='#n932'>932</a>
<a id='n933' href='#n933'>933</a>
<a id='n934' href='#n934'>934</a>
<a id='n935' href='#n935'>935</a>
<a id='n936' href='#n936'>936</a>
<a id='n937' href='#n937'>937</a>
<a id='n938' href='#n938'>938</a>
<a id='n939' href='#n939'>939</a>
<a id='n940' href='#n940'>940</a>
<a id='n941' href='#n941'>941</a>
<a id='n942' href='#n942'>942</a>
<a id='n943' href='#n943'>943</a>
<a id='n944' href='#n944'>944</a>
<a id='n945' href='#n945'>945</a>
<a id='n946' href='#n946'>946</a>
<a id='n947' href='#n947'>947</a>
<a id='n948' href='#n948'>948</a>
<a id='n949' href='#n949'>949</a>
<a id='n950' href='#n950'>950</a>
<a id='n951' href='#n951'>951</a>
<a id='n952' href='#n952'>952</a>
<a id='n953' href='#n953'>953</a>
<a id='n954' href='#n954'>954</a>
<a id='n955' href='#n955'>955</a>
<a id='n956' href='#n956'>956</a>
<a id='n957' href='#n957'>957</a>
<a id='n958' href='#n958'>958</a>
<a id='n959' href='#n959'>959</a>
<a id='n960' href='#n960'>960</a>
<a id='n961' href='#n961'>961</a>
<a id='n962' href='#n962'>962</a>
<a id='n963' href='#n963'>963</a>
<a id='n964' href='#n964'>964</a>
<a id='n965' href='#n965'>965</a>
<a id='n966' href='#n966'>966</a>
<a id='n967' href='#n967'>967</a>
<a id='n968' href='#n968'>968</a>
<a id='n969' href='#n969'>969</a>
<a id='n970' href='#n970'>970</a>
<a id='n971' href='#n971'>971</a>
<a id='n972' href='#n972'>972</a>
<a id='n973' href='#n973'>973</a>
<a id='n974' href='#n974'>974</a>
<a id='n975' href='#n975'>975</a>
<a id='n976' href='#n976'>976</a>
<a id='n977' href='#n977'>977</a>
<a id='n978' href='#n978'>978</a>
<a id='n979' href='#n979'>979</a>
<a id='n980' href='#n980'>980</a>
<a id='n981' href='#n981'>981</a>
<a id='n982' href='#n982'>982</a>
<a id='n983' href='#n983'>983</a>
<a id='n984' href='#n984'>984</a>
<a id='n985' href='#n985'>985</a>
<a id='n986' href='#n986'>986</a>
<a id='n987' href='#n987'>987</a>
<a id='n988' href='#n988'>988</a>
<a id='n989' href='#n989'>989</a>
<a id='n990' href='#n990'>990</a>
<a id='n991' href='#n991'>991</a>
<a id='n992' href='#n992'>992</a>
<a id='n993' href='#n993'>993</a>
<a id='n994' href='#n994'>994</a>
<a id='n995' href='#n995'>995</a>
<a id='n996' href='#n996'>996</a>
<a id='n997' href='#n997'>997</a>
<a id='n998' href='#n998'>998</a>
<a id='n999' href='#n999'>999</a>
<a id='n1000' href='#n1000'>1000</a>
<a id='n1001' href='#n1001'>1001</a>
<a id='n1002' href='#n1002'>1002</a>
<a id='n1003' href='#n1003'>1003</a>
<a id='n1004' href='#n1004'>1004</a>
<a id='n1005' href='#n1005'>1005</a>
<a id='n1006' href='#n1006'>1006</a>
<a id='n1007' href='#n1007'>1007</a>
<a id='n1008' href='#n1008'>1008</a>
<a id='n1009' href='#n1009'>1009</a>
<a id='n1010' href='#n1010'>1010</a>
<a id='n1011' href='#n1011'>1011</a>
<a id='n1012' href='#n1012'>1012</a>
<a id='n1013' href='#n1013'>1013</a>
<a id='n1014' href='#n1014'>1014</a>
<a id='n1015' href='#n1015'>1015</a>
<a id='n1016' href='#n1016'>1016</a>
<a id='n1017' href='#n1017'>1017</a>
<a id='n1018' href='#n1018'>1018</a>
<a id='n1019' href='#n1019'>1019</a>
<a id='n1020' href='#n1020'>1020</a>
<a id='n1021' href='#n1021'>1021</a>
<a id='n1022' href='#n1022'>1022</a>
<a id='n1023' href='#n1023'>1023</a>
<a id='n1024' href='#n1024'>1024</a>
<a id='n1025' href='#n1025'>1025</a>
<a id='n1026' href='#n1026'>1026</a>
<a id='n1027' href='#n1027'>1027</a>
<a id='n1028' href='#n1028'>1028</a>
<a id='n1029' href='#n1029'>1029</a>
<a id='n1030' href='#n1030'>1030</a>
<a id='n1031' href='#n1031'>1031</a>
<a id='n1032' href='#n1032'>1032</a>
<a id='n1033' href='#n1033'>1033</a>
<a id='n1034' href='#n1034'>1034</a>
<a id='n1035' href='#n1035'>1035</a>
<a id='n1036' href='#n1036'>1036</a>
<a id='n1037' href='#n1037'>1037</a>
<a id='n1038' href='#n1038'>1038</a>
<a id='n1039' href='#n1039'>1039</a>
<a id='n1040' href='#n1040'>1040</a>
<a id='n1041' href='#n1041'>1041</a>
<a id='n1042' href='#n1042'>1042</a>
<a id='n1043' href='#n1043'>1043</a>
<a id='n1044' href='#n1044'>1044</a>
<a id='n1045' href='#n1045'>1045</a>
<a id='n1046' href='#n1046'>1046</a>
<a id='n1047' href='#n1047'>1047</a>
<a id='n1048' href='#n1048'>1048</a>
<a id='n1049' href='#n1049'>1049</a>
<a id='n1050' href='#n1050'>1050</a>
<a id='n1051' href='#n1051'>1051</a>
<a id='n1052' href='#n1052'>1052</a>
<a id='n1053' href='#n1053'>1053</a>
<a id='n1054' href='#n1054'>1054</a>
<a id='n1055' href='#n1055'>1055</a>
<a id='n1056' href='#n1056'>1056</a>
<a id='n1057' href='#n1057'>1057</a>
<a id='n1058' href='#n1058'>1058</a>
<a id='n1059' href='#n1059'>1059</a>
<a id='n1060' href='#n1060'>1060</a>
<a id='n1061' href='#n1061'>1061</a>
<a id='n1062' href='#n1062'>1062</a>
<a id='n1063' href='#n1063'>1063</a>
<a id='n1064' href='#n1064'>1064</a>
<a id='n1065' href='#n1065'>1065</a>
<a id='n1066' href='#n1066'>1066</a>
<a id='n1067' href='#n1067'>1067</a>
<a id='n1068' href='#n1068'>1068</a>
<a id='n1069' href='#n1069'>1069</a>
<a id='n1070' href='#n1070'>1070</a>
<a id='n1071' href='#n1071'>1071</a>
<a id='n1072' href='#n1072'>1072</a>
<a id='n1073' href='#n1073'>1073</a>
<a id='n1074' href='#n1074'>1074</a>
<a id='n1075' href='#n1075'>1075</a>
<a id='n1076' href='#n1076'>1076</a>
<a id='n1077' href='#n1077'>1077</a>
<a id='n1078' href='#n1078'>1078</a>
<a id='n1079' href='#n1079'>1079</a>
<a id='n1080' href='#n1080'>1080</a>
<a id='n1081' href='#n1081'>1081</a>
<a id='n1082' href='#n1082'>1082</a>
<a id='n1083' href='#n1083'>1083</a>
<a id='n1084' href='#n1084'>1084</a>
<a id='n1085' href='#n1085'>1085</a>
<a id='n1086' href='#n1086'>1086</a>
<a id='n1087' href='#n1087'>1087</a>
<a id='n1088' href='#n1088'>1088</a>
<a id='n1089' href='#n1089'>1089</a>
<a id='n1090' href='#n1090'>1090</a>
<a id='n1091' href='#n1091'>1091</a>
<a id='n1092' href='#n1092'>1092</a>
<a id='n1093' href='#n1093'>1093</a>
<a id='n1094' href='#n1094'>1094</a>
<a id='n1095' href='#n1095'>1095</a>
<a id='n1096' href='#n1096'>1096</a>
<a id='n1097' href='#n1097'>1097</a>
<a id='n1098' href='#n1098'>1098</a>
<a id='n1099' href='#n1099'>1099</a>
<a id='n1100' href='#n1100'>1100</a>
<a id='n1101' href='#n1101'>1101</a>
<a id='n1102' href='#n1102'>1102</a>
<a id='n1103' href='#n1103'>1103</a>
<a id='n1104' href='#n1104'>1104</a>
<a id='n1105' href='#n1105'>1105</a>
<a id='n1106' href='#n1106'>1106</a>
<a id='n1107' href='#n1107'>1107</a>
<a id='n1108' href='#n1108'>1108</a>
<a id='n1109' href='#n1109'>1109</a>
<a id='n1110' href='#n1110'>1110</a>
<a id='n1111' href='#n1111'>1111</a>
<a id='n1112' href='#n1112'>1112</a>
<a id='n1113' href='#n1113'>1113</a>
<a id='n1114' href='#n1114'>1114</a>
<a id='n1115' href='#n1115'>1115</a>
<a id='n1116' href='#n1116'>1116</a>
<a id='n1117' href='#n1117'>1117</a>
<a id='n1118' href='#n1118'>1118</a>
<a id='n1119' href='#n1119'>1119</a>
<a id='n1120' href='#n1120'>1120</a>
<a id='n1121' href='#n1121'>1121</a>
<a id='n1122' href='#n1122'>1122</a>
<a id='n1123' href='#n1123'>1123</a>
<a id='n1124' href='#n1124'>1124</a>
<a id='n1125' href='#n1125'>1125</a>
<a id='n1126' href='#n1126'>1126</a>
<a id='n1127' href='#n1127'>1127</a>
<a id='n1128' href='#n1128'>1128</a>
<a id='n1129' href='#n1129'>1129</a>
<a id='n1130' href='#n1130'>1130</a>
<a id='n1131' href='#n1131'>1131</a>
<a id='n1132' href='#n1132'>1132</a>
<a id='n1133' href='#n1133'>1133</a>
<a id='n1134' href='#n1134'>1134</a>
<a id='n1135' href='#n1135'>1135</a>
<a id='n1136' href='#n1136'>1136</a>
<a id='n1137' href='#n1137'>1137</a>
<a id='n1138' href='#n1138'>1138</a>
<a id='n1139' href='#n1139'>1139</a>
<a id='n1140' href='#n1140'>1140</a>
<a id='n1141' href='#n1141'>1141</a>
<a id='n1142' href='#n1142'>1142</a>
<a id='n1143' href='#n1143'>1143</a>
<a id='n1144' href='#n1144'>1144</a>
<a id='n1145' href='#n1145'>1145</a>
<a id='n1146' href='#n1146'>1146</a>
<a id='n1147' href='#n1147'>1147</a>
<a id='n1148' href='#n1148'>1148</a>
<a id='n1149' href='#n1149'>1149</a>
<a id='n1150' href='#n1150'>1150</a>
</pre></td>
<td class='lines'><pre><code>