// The four D flip-flops (DFFs) in a Cyclone V/10GX Adaptive Logic Module (ALM) // act as one-bit memory cells that can be placed very flexibly (wherever there's // an ALM); each flop is represented by a MISTRAL_FF cell. // // The flops in these chips are rather flexible in some ways, but in practice // quite crippled by FPGA standards. // // What the flops can do // --------------------- // The core flop acts as a single-bit memory that initialises to zero at chip // reset. It takes in data on the rising edge of CLK if ENA is high, // and outputs it to Q. The ENA (clock enable) pin can therefore be used to // capture the input only if a condition is true. // // The data itself is zero if SCLR (synchronous clear) is high, else it comes // from SDATA (synchronous data) if SLOAD (synchronous load) is high, or DATAIN // if SLOAD is low. // // If ACLR (asynchronous clear) is low then Q is forced to zero, regardless of // the synchronous inputs or CLK edge. This is most often used for an FPGA-wide // power-on reset. // // An asynchronous set that sets Q to one can be emulated by inverting the input // and output of the flop, resulting in ACLR forcing Q to zero, which then gets // inverted to produce one. Likewise, logic can operate on the falling edge of // CLK if CLK is inverted before being passed as an input. // // What the flops *can't* do // ------------------------- // The trickiest part of the above capabilities is the lack of configurable // initialisation state. For example, it isn't possible to implement a flop with // asynchronous clear that initialises to one, because the hardware initialises // to zero. Likewise, you can't emulate a flop with asynchronous set that // initialises to zero, because the inverters mean the flop initialises to one. // // If the input design requires one of these cells (which appears to be rare // in practice) then synth_intel_alm will fail to synthesize the design where // other Yosys synthesis scripts might succeed. // // This stands in notable contrast to e.g. Xilinx flip-flops, which have // configurable initialisation state and native synchronous/asynchronous // set/clear (although not at the same time), which means they can generally // implement a much wider variety of logic. // DATAIN: synchronous data input // CLK: clock input (positive edge) // ACLR: asynchronous clear (negative-true) // ENA: clock-enable // SCLR: synchronous clear // SLOAD: synchronous load // SDATA: synchronous load data // // Q: data output // // Note: the DFFEAS primitive is mostly emulated; it does not reflect what the hardware implements. (* abc9_box, lib_whitebox *) module MISTRAL_FF( input DATAIN, (* clkbuf_sink *) input CLK, input ACLR, ENA, SCLR, SLOAD, SDATA, output reg Q ); `ifdef cyclonev specify if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = 731; if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = 890; if (ENA && !SCLR && SLOAD) (posedge CLK => (Q : SDATA)) = 618; $setup(DATAIN, posedge CLK, /* -196 */ 0); $setup(ENA, posedge CLK, /* -196 */ 0); $setup(SCLR, posedge CLK, /* -196 */ 0); $setup(SLOAD, posedge CLK, /* -196 */ 0); $setup(SDATA, posedge CLK, /* -196 */ 0); if (ACLR === 1'b0) (ACLR => Q) = 282; endspecify `endif `ifdef cyclone10gx specify // TODO (long-term): investigate these numbers. // It seems relying on the Quartus Timing Analyzer was not the best idea; it's too fiddly. if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = 219; if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = 219; if (ENA && !SCLR && SLOAD) (posedge CLK => (Q : SDATA)) = 219; $setup(DATAIN, posedge CLK, 268); $setup(ENA, posedge CLK, 268); $setup(SCLR, posedge CLK, 268); $setup(SLOAD, posedge CLK, 268); $setup(SDATA, posedge CLK, 268); if (ACLR === 1'b0) (ACLR => Q) = 0; endspecify `endif initial begin // Altera flops initialise to zero. Q = 0; end always @(posedge CLK, negedge ACLR) begin // Asynchronous clear if (!ACLR) Q <= 0; // Clock-enable else if (ENA) begin // Synchronous clear if (SCLR) Q <= 0; // Synchronous load else if (SLOAD) Q <= SDATA; else Q <= DATAIN; end end endmodule ef='#n21'>21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 
/******************************************************************************
 * domain_build.c
 * 
 * Copyright (c) 2002-2005, K A Fraser
 */

#include <xen/config.h>
#include <xen/init.h>
#include <xen/lib.h>
#include <xen/ctype.h>
#include <xen/sched.h>
#include <xen/smp.h>
#include <xen/delay.h>
#include <xen/event.h>
#include <xen/elf.h>
#include <xen/kernel.h>
#include <asm/regs.h>
#include <asm/system.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/desc.h>
#include <asm/i387.h>
#include <asm/shadow.h>

/* opt_dom0_mem: memory allocated to domain 0. */
static unsigned int opt_dom0_mem;
static void parse_dom0_mem(char *s)
{
    unsigned long long bytes = parse_size_and_unit(s);
    /* If no unit is specified we default to kB units, not bytes. */
    if ( isdigit(s[strlen(s)-1]) )
        opt_dom0_mem = (unsigned int)bytes;
    else
        opt_dom0_mem = (unsigned int)(bytes >> 10);
}
custom_param("dom0_mem", parse_dom0_mem);

static unsigned int opt_dom0_shadow = 0;
boolean_param("dom0_shadow", opt_dom0_shadow);

static unsigned int opt_dom0_translate = 0;
boolean_param("dom0_translate", opt_dom0_translate);

#if defined(__i386__)
/* No ring-3 access in initial leaf page tables. */
#define L1_PROT (_PAGE_PRESENT|_PAGE_RW|_PAGE_ACCESSED)
#elif defined(__x86_64__)
/* Allow ring-3 access in long mode as guest cannot use ring 1. */
#define L1_PROT (_PAGE_PRESENT|_PAGE_RW|_PAGE_ACCESSED|_PAGE_USER)
#endif
/* Don't change these: Linux expects just these bits to be set. */
/* (And that includes the bogus _PAGE_DIRTY!) */
#define L2_PROT (_PAGE_PRESENT|_PAGE_RW|_PAGE_ACCESSED|_PAGE_DIRTY|_PAGE_USER)
#define L3_PROT (_PAGE_PRESENT|_PAGE_RW|_PAGE_ACCESSED|_PAGE_DIRTY|_PAGE_USER)
#define L4_PROT (_PAGE_PRESENT|_PAGE_RW|_PAGE_ACCESSED|_PAGE_DIRTY|_PAGE_USER)

#define round_pgup(_p)    (((_p)+(PAGE_SIZE-1))&PAGE_MASK)
#define round_pgdown(_p)  ((_p)&PAGE_MASK)

static struct pfn_info *alloc_largest(struct domain *d, unsigned long max)
{
    struct pfn_info *page;
    unsigned int order = get_order(max * PAGE_SIZE);
    if ( (max & (max-1)) != 0 )
        order--;
    while ( (page = alloc_domheap_pages(d, order)) == NULL )
        if ( order-- == 0 )
            break;
    return page;
}

int construct_dom0(struct domain *d,
                   unsigned long _image_start, unsigned long image_len, 
                   unsigned long _initrd_start, unsigned long initrd_len,
                   char *cmdline)
{
    char *dst;
    int i, rc;
    unsigned long pfn, mfn;
    unsigned long nr_pages;
    unsigned long nr_pt_pages;
    unsigned long alloc_start;
    unsigned long alloc_end;
    unsigned long count;
    struct pfn_info *page = NULL;
    start_info_t *si;
    struct exec_domain *ed = d->exec_domain[0];
#if defined(__i386__)
    char *image_start  = (char *)_image_start;  /* use lowmem mappings */
    char *initrd_start = (char *)_initrd_start; /* use lowmem mappings */
#elif defined(__x86_64__)
    char *image_start  = __va(_image_start);
    char *initrd_start = __va(_initrd_start);
    l4_pgentry_t *l4tab = NULL, *l4start = NULL;
    l3_pgentry_t *l3tab = NULL, *l3start = NULL;
#endif
    l2_pgentry_t *l2tab = NULL, *l2start = NULL;
    l1_pgentry_t *l1tab = NULL, *l1start = NULL;

    /*
     * This fully describes the memory layout of the initial domain. All 
     * *_start address are page-aligned, except v_start (and v_end) which are 
     * superpage-aligned.
     */
    struct domain_setup_info dsi;
    unsigned long vinitrd_start;
    unsigned long vinitrd_end;
    unsigned long vphysmap_start;
    unsigned long vphysmap_end;
    unsigned long vstartinfo_start;
    unsigned long vstartinfo_end;
    unsigned long vstack_start;
    unsigned long vstack_end;
    unsigned long vpt_start;
    unsigned long vpt_end;
    unsigned long v_end;

    /* Machine address of next candidate page-table page. */
    unsigned long mpt_alloc;

    extern void physdev_init_dom0(struct domain *);
    extern void translate_l2pgtable(struct domain *d, l1_pgentry_t *p2m, unsigned long l2mfn);

    /* Sanity! */
    if ( d->domain_id != 0 ) 
        BUG();
    if ( test_bit(_DOMF_constructed, &d->domain_flags) ) 
        BUG();

    memset(&dsi, 0, sizeof(struct domain_setup_info));
    dsi.image_addr = (unsigned long)image_start;
    dsi.image_len  = image_len;

    printk("*** LOADING DOMAIN 0 ***\n");

    /* By default DOM0 is allocated all available memory. */
    d->max_pages = ~0U;
    if ( (nr_pages = opt_dom0_mem >> (PAGE_SHIFT - 10)) == 0 )
        nr_pages = avail_domheap_pages() +
            ((initrd_len + PAGE_SIZE - 1) >> PAGE_SHIFT) +
            ((image_len  + PAGE_SIZE - 1) >> PAGE_SHIFT);
    if ( (page = alloc_largest(d, nr_pages)) == NULL )
        panic("Not enough RAM for DOM0 reservation.\n");
    alloc_start = page_to_phys(page);
    alloc_end   = alloc_start + (d->tot_pages << PAGE_SHIFT);