module \$lut (A, Y); parameter WIDTH = 1; parameter LUT = 0; (* force_downto *) input [WIDTH-1:0] A; output Y; generate if (WIDTH == 1) begin generate if (LUT == 2'b00) begin assign Y = 1'b0; end else if (LUT == 2'b01) begin MISTRAL_NOT _TECHMAP_REPLACE_( .A(A[0]), .Q(Y) ); end else if (LUT == 2'b10) begin assign Y = A; end else if (LUT == 2'b11) begin assign Y = 1'b1; end endgenerate end else if (WIDTH == 2) begin MISTRAL_ALUT2 #(.LUT(LUT)) _TECHMAP_REPLACE_( .A(A[0]), .B(A[1]), .Q(Y) ); end else if (WIDTH == 3) begin MISTRAL_ALUT3 #(.LUT(LUT)) _TECHMAP_REPLACE_( .A(A[0]), .B(A[1]), .C(A[2]), .Q(Y) ); end else if (WIDTH == 4) begin MISTRAL_ALUT4 #(.LUT(LUT)) _TECHMAP_REPLACE_( .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]), .Q(Y) ); end else if (WIDTH == 5) begin MISTRAL_ALUT5 #(.LUT(LUT)) _TECHMAP_REPLACE_ ( .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]), .E(A[4]), .Q(Y) ); end else if (WIDTH == 6) begin MISTRAL_ALUT6 #(.LUT(LUT)) _TECHMAP_REPLACE_ ( .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]), .E(A[4]), .F(A[5]), .Q(Y) ); end else begin wire _TECHMAP_FAIL_ = 1'b1; end endgenerate endmodule ys/tree/techlibs/intel/cycloneive/arith_map.v?id=6f9602b4cfedc6441f55272f6c025d64620cd24f'>treecommitdiffstats
path: root/techlibs/intel/cycloneive/arith_map.v
blob: f31baf1e1d492320d8330ca4ea2525820e51cfb8 (plain) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105