bram $__TRELLIS_DPR16X4 init 1 abits 4 dbits 4 groups 2 ports 1 1 wrmode 0 1 enable 0 1 transp 0 0 clocks 0 1 clkpol 0 2 endbram match $__TRELLIS_DPR16X4 make_outreg min wports 1 endmatch it.panaceas.org/cgit.cgi/iCE40/yosys/atom/tests/arch/anlogic/add_sub.ys?h=master' type='application/atom+xml'/>
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