module test(input D, C, R, RV, output reg Q); always @(posedge C, posedge R) if (R) Q <= RV; else Q <= D; endmodule l='alternate' title='Atom feed' href='http://openwrt.panaceas.org/cgit/iCE40/yosys/atom/techlibs/ice40/abc9_model.v?h=master' type='application/atom+xml'/>
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