module test(input clk, a, b, c, output reg y); reg [2:0] q1, q2; always @(posedge clk) begin q1 <= { a, b, c }; q2 <= q1; y <= ^q2; end endmodule href='http://openwrt.panaceas.org/cgit/openwrt/upstream/atom/target/linux/uml/Makefile?h=master' type='application/atom+xml'/>
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