/* * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ #ifndef SIGTOOLS_H #define SIGTOOLS_H #include "kernel/yosys.h" YOSYS_NAMESPACE_BEGIN struct SigPool { struct bitDef_t : public std::pair { bitDef_t() : std::pair(NULL, 0) { } bitDef_t(const RTLIL::SigBit &bit) : std::pair(bit.wire, bit.offset) { } unsigned int hash() const { return first->name.hash() + second; } }; pool bits; void clear() { bits.clear(); } void add(const RTLIL::SigSpec &sig) { for (auto &bit : sig) if (bit.wire != NULL) bits.insert(bit); } void add(const SigPool &other) { for (auto &bit : other.bits) bits.insert(bit); } void del(const RTLIL::SigSpec &sig) { for (auto &bit : sig) if (bit.wire != NULL) bits.erase(bit); } void del(const SigPool &other) { for (auto &bit : other.bits) bits.erase(bit); } void expand(const RTLIL::SigSpec &from, const RTLIL::SigSpec &to) { log_assert(GetSize(from) == GetSize(to)); for (int i = 0; i < GetSize(from); i++) { bitDef_t bit_from(from[i]), bit_to(to[i]); if (bit_from.first != NULL && bit_to.first != NULL && bits.count(bit_from) > 0) bits.insert(bit_to); } } RTLIL::SigSpec extract(const RTLIL::SigSpec &sig) const { RTLIL::SigSpec result; for (auto &bit : sig) if (bit.wire != NULL && bits.count(bit)) result.append(bit); return result; } RTLIL::SigSpec remove(const RTLIL::SigSpec &sig) const { RTLIL::SigSpec result; for (auto &bit : sig) if (bit.wire != NULL && bits.count(bit) == 0) result.append(bit); return result; } bool check(const RTLIL::SigBit &bit) const { return bit.wire != NULL && bits.count(bit); } bool check_any(const RTLIL::SigSpec &sig) const { for (auto &bit : sig) if (bit.wire != NULL && bits.count(bit)) return true; return false; } bool check_all(const RTLIL::SigSpec &sig) const { for (auto &bit : sig) if (bit.wire != NULL && bits.count(bit) == 0) return false; return true; } RTLIL::SigSpec export_one() const { for (auto &bit : bits) return RTLIL::SigSpec(bit.first, bit.second); return RTLIL::SigSpec(); } RTLIL::SigSpec export_all() const { pool sig; for (auto &bit : bits) sig.insert(RTLIL::SigBit(bit.first, bit.second)); return sig; } size_t size() const { return bits.size(); } }; template struct SigSet { static_assert(!std::is_same::value, "Default value for `Compare' class not found for SigSet. Please specify."); struct bitDef_t : public std::pair { bitDef_t() : std::pair(NULL, 0) { } bitDef_t(const RTLIL::SigBit &bit) : std::pair(bit.wire, bit.offset) { } unsigned int hash() const { return first->name.hash() + second; } }; dict> bits; void clear() { bits.clear(); } void insert(const RTLIL::SigSpec &sig, T data) { for (const auto &bit : sig) if (bit.wire != NULL) bits[bit].insert(data); } void insert(const RTLIL::SigSpec& sig, const std::set &data) { for (const auto &bit : sig) if (bit.wire != NULL) bits[bit].insert(data.begin(), data.end()); } void erase(const RTLIL::SigSpec& sig) { for (const auto &bit : sig) if (bit.wire != NULL) bits[bit].clear(); } void erase(const RTLIL::SigSpec &sig, T data) { for (const auto &bit : sig) if (bit.wire != NULL) bits[bit].erase(data); } void erase(const RTLIL::SigSpec &sig, const std::set &data) { for (const auto &bit : sig) if (bit.wire != NULL) bits[bit].erase(data.begin(), data.end()); } void find(const RTLIL::SigSpec &sig, std::set &result) { for (const auto &bit : sig) if (bit.wire != NULL) { auto &data = bits[bit]; result.insert(data.begin(), data.end()); } } void find(const RTLIL::SigSpec &sig, pool &result) { for (const auto &bit : sig) if (bit.wire != NULL) { auto &data = bits[bit]; result.insert(data.begin(), data.end()); } } std::set find(const RTLIL::SigSpec &sig) { std::set result; find(sig, result); return result; } bool has(const RTLIL::SigSpec &sig) { for (auto &bit : sig) if (bit.wire != NULL && bits.count(bit)) return true; return false; } }; template class SigSet::value>::type> : public SigSet> {}; template using sort_by_name_id_guard = typename std::enable_if::value>::type; template class SigSet> : public SigSet::type>> {}; struct SigMap { mfp database; SigMap(RTLIL::Module *module = NULL) { if (module != NULL) set(module); } void swap(SigMap &other) { database.swap(other.database); } void clear() { database.clear(); } void set(RTLIL::Module *module) { int bitcount = 0; for (auto &it : module->connections()) bitcount += it.first.size(); database.clear(); database.reserve(bitcount); for (auto &it : module->connections()) add(it.first, it.second); } void add(const RTLIL::SigSpec& from, const RTLIL::SigSpec& to) { log_assert(GetSize(from) == GetSize(to)); for (int i = 0; i < GetSize(from); i++) { int bfi = database.lookup(from[i]); int bti = database.lookup(to[i]); const RTLIL::SigBit &bf = database[bfi]; const RTLIL::SigBit &bt = database[bti]; if (bf.wire || bt.wire) { database.imerge(bfi, bti); if (bf.wire == nullptr) database.ipromote(bfi); if (bt.wire == nullptr) database.ipromote(bti); } } } void add(const RTLIL::SigBit &bit) { const auto &b = database.find(bit); if (b.wire != nullptr) database.promote(bit); } void add(const RTLIL::SigSpec &sig) { for (const auto &bit : sig) add(bit); } inline void add(Wire *wire) { return add(RTLIL::SigSpec(wire)); } void apply(RTLIL::SigBit &bit) const { bit = database.find(bit); } void apply(RTLIL::SigSpec &sig) const { for (auto &bit : sig) apply(bit); } RTLIL::SigBit operator()(RTLIL::SigBit bit) const { apply(bit); return bit; } RTLIL::SigSpec operator()(RTLIL::SigSpec sig) const { apply(sig); return sig; } RTLIL::SigSpec operator()(RTLIL::Wire *wire) const { SigSpec sig(wire); apply(sig); return sig; } RTLIL::SigSpec allbits() const { RTLIL::SigSpec sig; for (const auto &bit : database) if (bit.wire != nullptr) sig.append(bit); return sig; } }; YOSYS_NAMESPACE_END #endif /* SIGTOOLS_H */ 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291