/* * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2020 Marcelina Kościelnicka * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ #ifndef MEM_H #define MEM_H #include "kernel/yosys.h" #include "kernel/ffinit.h" YOSYS_NAMESPACE_BEGIN struct MemRd : RTLIL::AttrObject { bool removed; Cell *cell; int wide_log2; bool clk_enable, clk_polarity, ce_over_srst; Const arst_value, srst_value, init_value; // One bit for every write port, true iff simultanous read on this // port and write on the other port will bypass the written data // to this port's output (default behavior is to read old value). // Can only be set for write ports that have the same clock domain. std::vector transparency_mask; // One bit for every write port, true iff simultanous read on this // port and write on the other port will return an all-X (don't care) // value. Mutually exclusive with transparency_mask. // Can only be set for write ports that have the same clock domain. // For optimization purposes, this will also be set if we can // determine that the two ports can never be active simultanously // (making the above vacuously true). std::vector collision_x_mask; SigSpec clk, en, arst, srst, addr, data; MemRd() : removed(false), cell(nullptr) {} // Returns the address of given subword index accessed by this port. SigSpec sub_addr(int sub) { SigSpec res = addr; for (int i = 0; i < wide_log2; i++) res[i] = State(sub >> i & 1); return res; } }; struct MemWr : RTLIL::AttrObject { bool removed; Cell *cell; int wide_log2; bool clk_enable, clk_polarity; std::vector priority_mask; SigSpec clk, en, addr, data; MemWr() : removed(false), cell(nullptr) {} // Returns the address of given subword index accessed by this port. SigSpec sub_addr(int sub) { SigSpec res = addr; for (int i = 0; i < wide_log2; i++) res[i] = State(sub >> i & 1); return res; } }; struct MemInit : RTLIL::AttrObject { bool removed; Cell *cell; Const addr; Const data; Const en; MemInit() : removed(false), cell(nullptr) {} }; struct Mem : RTLIL::AttrObject { Module *module; IdString memid; bool packed; RTLIL::Memory *mem; Cell *cell; int width, start_offset, size; std::vector inits; std::vector rd_ports; std::vector wr_ports; // Removes this memory from the module. The data in helper structures // is unaffected except for the cell/mem fields. void remove(); // Commits all changes in helper structures into the module — ports and // inits marked as removed are actually removed, new ports/inits create // new cells, modified port/inits are commited into their existing // cells. Note that this reindexes the ports and inits array (actually // removing the ports/inits marked as removed). void emit(); // Marks all inits as removed. void clear_inits(); // Coalesces inits: whenever two inits have overlapping or touching // address ranges, they are combined into one, with the higher-priority // one's data overwriting the other. Running this results in // an inits list equivalent to the original, in which all entries // cover disjoint (and non-touching) address ranges, and all enable // masks are all-1. void coalesce_inits(); // Checks consistency of this memory and all its ports/inits, using // log_assert. void check(); // Gathers all initialization data into a single big const covering // the whole memory. For all non-initialized bits, Sx will be returned. Const get_init_data() const; // Constructs and returns the helper structures for all memories // in a module. static std::vector get_all_memories(Module *module); // Constructs and returns the helper structures for all selected // memories in a module. static std::vector get_selected_memories(Module *module); // Converts a synchronous read port into an asynchronous one by // extracting the data (or, in some rare cases, address) register // into a separate cell, together with any soft-transparency // logic necessary to preserve its semantics. Returns the created // register cell, if any. Note that in some rare cases this function // may succeed and perform a conversion without creating a new // register — a nullptr result doesn't imply nothing was done. Cell *extract_rdff(int idx, FfInitVals *initvals); // Splits all wide ports in this memory into equivalent narrow ones. // This function performs no modifications at all to the actual // netlist unless and until emit() is called. void narrow(); // If write port idx2 currently has priority over write port idx1, // inserts extra logic on idx1's enable signal to disable writes // when idx2 is writing to the same address, then removes the priority // from the priority mask. If there is a memory port that is // transparent with idx1, but not with idx2, that port is converted // to use soft transparency logic. void emulate_priority(int idx1, int idx2, FfInitVals *initvals); // Creates soft-transparency logic on read port ridx, bypassing the // data from write port widx. Should only be called when ridx is // transparent wrt widx in the first place. Once we're done, the // transparency_mask bit will be cleared, and the collision_x_mask // bit will be set instead (since whatever value is read will be // replaced by the soft transparency logic). void emulate_transparency(int widx, int ridx, FfInitVals *initvals); // Prepares for merging write port idx2 into idx1 (where idx1 < idx2). // Specifically, takes care of priority masks: any priority relations // that idx2 had are replicated onto idx1, unless they conflict with // priorities already present on idx1, in which case emulate_priority // is called. Likewise, ensures transparency and undefined collision // masks of all read ports have the same values for both ports, // calling emulate_transparency if necessary. void prepare_wr_merge(int idx1, int idx2, FfInitVals *initvals); // Prepares for merging read port idx2 into idx1. // Specifically, makes sure the transparency and undefined collision // masks of both ports are equal, by changing undefined behavior // of one port to the other's defined behavior, or by calling // emulate_transparency if necessary. void prepare_rd_merge(int idx1, int idx2, FfInitVals *initvals); // Prepares the memory for widening a port to a given width. This // involves ensuring that start_offset and size are aligned to the // target width. void widen_prep(int wide_log2); // Widens a write port up to a given width. The newly port is // equivalent to the original, made by replicating enable/data bits // and masking enable bits with decoders on the low part of the // original address. void widen_wr_port(int idx, int wide_log2); Mem(Module *module, IdString memid, int width, int start_offset, int size) : module(module), memid(memid), packed(false), mem(nullptr), cell(nullptr), width(width), start_offset(start_offset), size(size) {} }; YOSYS_NAMESPACE_END #endif 144'>144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681