/* * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * * --- * * The Verilog frontend. * * This frontend is using the AST frontend library (see frontends/ast/). * Thus this frontend does not generate RTLIL code directly but creates an * AST directly from the Verilog parse tree and then passes this AST to * the AST frontend library. * */ #include "verilog_frontend.h" #include "kernel/yosys.h" #include "libs/sha1/sha1.h" #include YOSYS_NAMESPACE_BEGIN using namespace VERILOG_FRONTEND; // use the Verilog bison/flex parser to generate an AST and use AST::process() to convert it to RTLIL static std::vector verilog_defaults; static std::list> verilog_defaults_stack; struct VerilogFrontend : public Frontend { VerilogFrontend() : Frontend("verilog", "read modules from verilog file") { } virtual void help() { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log(" read_verilog [options] [filename]\n"); log("\n"); log("Load modules from a verilog file to the current design. A large subset of\n"); log("Verilog-2005 is supported.\n"); log("\n"); log(" -sv\n"); log(" enable support for SystemVerilog features. (only a small subset\n"); log(" of SystemVerilog is supported)\n"); log("\n"); log(" -formal\n"); log(" enable support for assert() and assume() statements\n"); log(" (assert support is also enabled with -sv)\n"); log("\n"); log(" -dump_ast1\n"); log(" dump abstract syntax tree (before simplification)\n"); log("\n"); log(" -dump_ast2\n"); log(" dump abstract syntax tree (after simplification)\n"); log("\n"); log(" -dump_vlog\n"); log(" dump ast as verilog code (after simplification)\n"); log("\n"); log(" -yydebug\n"); log(" enable parser debug output\n"); log("\n"); log(" -nolatches\n"); log(" usually latches are synthesized into logic loops\n"); log(" this option prohibits this and sets the output to 'x'\n"); log(" in what would be the latches hold condition\n"); log("\n"); log(" this behavior can also be achieved by setting the\n"); log(" 'nolatches' attribute on the respective module or\n"); log(" always block.\n"); log("\n"); log(" -nomem2reg\n"); log(" under certain conditions memories are converted to registers\n"); log(" early during simplification to ensure correct handling of\n"); log(" complex corner cases. this option disables this behavior.\n"); log("\n"); log(" this can also be achieved by setting the 'nomem2reg'\n"); log(" attribute on the respective module or register.\n"); log("\n"); log(" This is potentially dangerous. Usually the front-end has good\n"); log(" reasons for converting an array to a list of registers.\n"); log(" Prohibiting this step will likely result in incorrect synthesis\n"); log(" results.\n"); log("\n"); log(" -mem2reg\n"); log(" always convert memories to registers. this can also be\n"); log(" achieved by setting the 'mem2reg' attribute on the respective\n"); log(" module or register.\n"); log("\n"); log(" -nomeminit\n"); log(" do not infer $meminit cells and instead convert initialized\n"); log(" memories to registers directly in the front-end.\n"); log("\n"); log(" -ppdump\n"); log(" dump verilog code after pre-processor\n"); log("\n"); log(" -nopp\n"); log(" do not run the pre-processor\n"); log("\n"); log(" -lib\n"); log(" only create empty blackbox modules\n"); log("\n"); log(" -noopt\n"); log(" don't perform basic optimizations (such as const folding) in the\n"); log(" high-level front-end.\n"); log("\n"); log(" -icells\n"); log(" interpret cell types starting with '$' as internal cell types\n"); log("\n"); log(" -ignore_redef\n"); log(" ignore re-definitions of modules. (the default behavior is to\n"); log(" create an error message.)\n"); log("\n"); log(" -defer\n"); log(" only read the abstract syntax tree and defer actual compilation\n"); log(" to a later 'hierarchy' command. Useful in cases where the default\n"); log(" parameters of modules yield invalid or not synthesizable code.\n"); log("\n"); log(" -setattr \n"); log(" set the specified attribute (to the value 1) on all loaded modules\n"); log("\n"); log(" -Dname[=definition]\n"); log(" define the preprocessor symbol 'name' and set its optional value\n"); log(" 'definition'\n"); log("\n"); log(" -Idir\n"); log(" add 'dir' to the directories which are used when searching include\n"); log(" files\n"); log("\n"); log("The command 'verilog_defaults' can be used to register default options for\n"); log("subsequent calls to 'read_verilog'.\n"); log("\n"); log("Note that the Verilog frontend does a pretty good job of processing valid\n"); log("verilog input, but has not very good error reporting. It generally is\n"); log("recommended to use a simulator (for example icarus verilog) for checking\n"); log("the syntax of the code, rather than to rely on read_verilog for that.\n"); log("\n"); } virtual void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) { bool flag_dump_ast1 = false; bool flag_dump_ast2 = false; bool flag_dump_vlog = false; bool flag_nolatches = false; bool flag_nomeminit = false; bool flag_nomem2reg = false; bool flag_mem2reg = false; bool flag_ppdump = false; bool flag_nopp = false; bool flag_lib = false; bool flag_noopt = false; bool flag_icells = false; bool flag_ignore_redef = false; bool flag_defer = false; std::map defines_map; std::list include_dirs; std::list attributes; frontend_verilog_yydebug = false; sv_mode = false; formal_mode = false; log_header("Executing Verilog-2005 frontend.\n"); args.insert(args.begin()+1, verilog_defaults.begin(), verilog_defaults.end()); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { std::string arg = args[argidx]; if (arg == "-sv") { sv_mode = true; continue; } if (arg == "-formal") { formal_mode = true; continue; } if (arg == "-dump_ast1") { flag_dump_ast1 = true; continue; } if (arg == "-dump_ast2") { flag_dump_ast2 = true; continue; } if (arg == "-dump_vlog") { flag_dump_vlog = true; continue; } if (arg == "-yydebug") { frontend_verilog_yydebug = true; continue; } if (arg == "-nolatches") { flag_nolatches = true; continue; } if (arg == "-nomeminit") { flag_nomeminit = true; continue; } if (arg == "-nomem2reg") { flag_nomem2reg = true; continue; } if (arg == "-mem2reg") { flag_mem2reg = true; continue; } if (arg == "-ppdump") { flag_ppdump = true; continue; } if (arg == "-nopp") { flag_nopp = true; continue; } if (arg == "-lib") { flag_lib = true; continue; } if (arg == "-noopt") { flag_noopt = true; continue; } if (arg == "-icells") { flag_icells = true; continue; } if (arg == "-ignore_redef") { flag_ignore_redef = true; continue; } if (arg == "-defer") { flag_defer = true; continue; } if (arg == "-setattr" && argidx+1 < args.size()) { attributes.push_back(RTLIL::escape_id(args[++argidx])); continue; } if (arg == "-D" && argidx+1 < args.size()) { std::string name = args[++argidx], value; size_t equal = name.find('=', 2); if (equal != std::string::npos) { value = arg.substr(equal+1); name = arg.substr(0, equal); } defines_map[name] = value; continue; } if (arg.compare(0, 2, "-D") == 0) { size_t equal = arg.find('=', 2); std::string name = arg.substr(2, equal-2); std::string value; if (equal != std::string::npos) value = arg.substr(equal+1); defines_map[name] = value; continue; } if (arg == "-I" && argidx+1 < args.size()) { include_dirs.push_back(args[++argidx]); continue; } if (arg.compare(0, 2, "-I") == 0) { include_dirs.push_back(arg.substr(2)); continue; } break; } extra_args(f, filename, args, argidx); log("Parsing %s%s input from `%s' to AST representation.\n", formal_mode ? "formal " : "", sv_mode ? "SystemVerilog" : "Verilog", filename.c_str()); AST::current_filename = filename; AST::set_line_num = &frontend_verilog_yyset_lineno; AST::get_line_num = &frontend_verilog_yyget_lineno; current_ast = new AST::AstNode(AST::AST_DESIGN); default_nettype_wire = true; lexin = f; std::string code_after_preproc; if (!flag_nopp) { code_after_preproc = frontend_verilog_preproc(*f, filename, defines_map, include_dirs); if (flag_ppdump) log("-- Verilog code after preprocessor --\n%s-- END OF DUMP --\n", code_after_preproc.c_str()); lexin = new std::istringstream(code_after_preproc); } frontend_verilog_yyset_lineno(1); frontend_verilog_yyrestart(NULL); frontend_verilog_yyparse(); frontend_verilog_yylex_destroy(); for (auto &child : current_ast->children) { if (child->type == AST::AST_MODULE) for (auto &attr : attributes) if (child->attributes.count(attr) == 0) child->attributes[attr] = AST::AstNode::mkconst_int(1, false); } AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_ignore_redef, flag_defer, default_nettype_wire); if (!flag_nopp) delete lexin; delete current_ast; current_ast = NULL; log("Successfully finished Verilog frontend.\n"); } } VerilogFrontend; struct VerilogDefaults : public Pass { VerilogDefaults() : Pass("verilog_defaults", "set default options for read_verilog") { } virtual void help() { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log(" verilog_defaults -add [options]\n"); log("\n"); log("Add the sepcified options to the list of default options to read_verilog.\n"); log("\n"); log("\n"); log(" verilog_defaults -clear"); log("\n"); log("Clear the list of verilog default options.\n"); log("\n"); log("\n"); log(" verilog_defaults -push"); log(" verilog_defaults -pop"); log("\n"); log("Push or pop the list of default options to a stack. Note that -push does\n"); log("not imply -clear.\n"); log("\n"); } virtual void execute(std::vector args, RTLIL::Design*) { if (args.size() == 0) cmd_error(args, 1, "Missing argument."); if (args[1] == "-add") { verilog_defaults.insert(verilog_defaults.end(), args.begin()+2, args.end()); return; } if (args.size() != 2) cmd_error(args, 2, "Extra argument."); if (args[1] == "-clear") { verilog_defaults.clear(); return; } if (args[1] == "-push") { verilog_defaults_stack.push_back(verilog_defaults); return; } if (args[1] == "-pop") { if (verilog_defaults_stack.empty()) { verilog_defaults.clear(); } else { verilog_defaults.swap(verilog_defaults_stack.back()); verilog_defaults_stack.pop_back(); } return; } } } VerilogDefaults; YOSYS_NAMESPACE_END // the yyerror function used by bison to report parser errors void frontend_verilog_yyerror(char const *fmt, ...) { va_list ap; char buffer[1024]; char *p = buffer; p += snprintf(p, buffer + sizeof(buffer) - p, "Parser error in line %s:%d: ", YOSYS_NAMESPACE_PREFIX AST::current_filename.c_str(), frontend_verilog_yyget_lineno()); va_start(ap, fmt); p += vsnprintf(p, buffer + sizeof(buffer) - p, fmt, ap); va_end(ap); p += snprintf(p, buffer + sizeof(buffer) - p, "\n"); YOSYS_NAMESPACE_PREFIX log_error("%s", buffer); exit(1); } /a> 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 
/*
 * ia64-specific cdb routines
 * cdb xen/ia64 by Isaku Yamahta <yamahata at valinux co jp>
 *                 VA Linux Systems Japan K.K.
 *  some routines are stolen from kgdb/ia64.
 */
/*
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2, or (at your option) any
 * later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 */

/*
 * Copyright (C) 2000-2001 VERITAS Software Corporation.
 */
/*
 *  Contributor:     Lake Stevens Instrument Division$
 *  Written by:      Glenn Engel $
 *  Updated by:	     Amit Kale<akale@veritas.com>
 *  Modified for 386 by Jim Kingdon, Cygnus Support.
 *  Origianl kgdb, compatibility with 2.1.xx kernel by David Grothe <dave@gcom.com>
 *
 */


#include <xen/lib.h>
#include <xen/mm.h>
#include <asm/byteorder.h>
#include <asm/debugger.h>
#include <asm/uaccess.h>

#define USE_UNWIND

#ifdef USE_UNWIND
#include <asm/unwind.h>
#endif

/* Printk isn't particularly safe just after we've trapped to the
   debugger. so avoid it. */
#define dbg_printk(...)
//#define dbg_printk(...)	printk(__VA_ARGS__)

u16
gdb_arch_signal_num(struct cpu_user_regs *regs, unsigned long cookie)
{
    /* XXX */
    return 1;
}

void 
gdb_arch_read_reg_array(struct cpu_user_regs *regs, struct gdb_context *ctx)
{
    gdb_send_reply("", ctx);
}

void 
gdb_arch_write_reg_array(struct cpu_user_regs *regs, const char* buf,
                         struct gdb_context *ctx)
{
    /* XXX TODO */
    gdb_send_reply("E02", ctx);
}

/* Like copy_from_user, but safe to call with interrupts disabled.
   Trust me, and don't look behind the curtain. */
unsigned
gdb_arch_copy_from_user(void *dest, const void *src, unsigned len)
{
	int val;
	__asm__ __volatile__(
		"cmp4.eq p6, p0 = r0, %1\n"
		"(p6) br.cond.dptk 2f\n"
		"[1:]\n"
		".xdata4 \"__ex_table\", 99f-., 2f-.;\n"
		"[99:] ld1 %0 = [%3], 1\n"
		";;\n"
		".xdata4 \"__ex_table\", 99f-., 2f-.;\n"
		"[99:] st1 [%2] = %0, 1\n"
		"adds %1 = -1, %1\n"
		";;\n"
		"cmp4.eq p0, p6 = r0, %1\n"
		"(p6) br.cond.dptk 1b\n"
		"[2:]\n"
		: "=r"(val), "=r"(len), "=r"(dest), "=r"(src)
		:  "1"(len), "2"(dest), "3"(src)
		: "memory", "p6");
	return len;
}

unsigned int 
gdb_arch_copy_to_user(void *dest, const void *src, unsigned len)
{
    /* XXX  */
    return len;
}

#define NUM_REGS 590
#define REGISTER_BYTES (NUM_REGS*8+128*8)
#define REGISTER_BYTE(N) (((N) * 8)									\
	+ ((N) <= IA64_FR0_REGNUM ?                                     \
	0 : 8 * (((N) > IA64_FR127_REGNUM) ? 128 : (N) - IA64_FR0_REGNUM)))
#define REGISTER_SIZE(N)                                               \
	(((N) >= IA64_FR0_REGNUM && (N) <= IA64_FR127_REGNUM) ? 16 : 8)
#define IA64_GR0_REGNUM         0
#define IA64_FR0_REGNUM         128
#define IA64_FR127_REGNUM       (IA64_FR0_REGNUM+127)
#define IA64_PR0_REGNUM         256
#define IA64_BR0_REGNUM         320
#define IA64_VFP_REGNUM         328
#define IA64_PR_REGNUM          330
#define IA64_IP_REGNUM          331
#define IA64_PSR_REGNUM         332
#define IA64_CFM_REGNUM         333
#define IA64_AR0_REGNUM         334
#define IA64_NAT0_REGNUM        462
#define IA64_NAT31_REGNUM       (IA64_NAT0_REGNUM+31)
#define IA64_NAT32_REGNUM       (IA64_NAT0_REGNUM+32)
#define IA64_RSC_REGNUM			(IA64_AR0_REGNUM+16)
#define IA64_BSP_REGNUM			(IA64_AR0_REGNUM+17)
#define IA64_BSPSTORE_REGNUM	(IA64_AR0_REGNUM+18)
#define IA64_RNAT_REGNUM		(IA64_AR0_REGNUM+19)
#define IA64_FCR_REGNUM			(IA64_AR0_REGNUM+21)
#define IA64_EFLAG_REGNUM		(IA64_AR0_REGNUM+24)
#define IA64_CSD_REGNUM			(IA64_AR0_REGNUM+25)
#define IA64_SSD_REGNUM			(IA64_AR0_REGNUM+26)
#define IA64_CFLG_REGNUM		(IA64_AR0_REGNUM+27)
#define IA64_FSR_REGNUM			(IA64_AR0_REGNUM+28)
#define IA64_FIR_REGNUM			(IA64_AR0_REGNUM+29)
#define IA64_FDR_REGNUM			(IA64_AR0_REGNUM+30)
#define IA64_CCV_REGNUM			(IA64_AR0_REGNUM+32)
#define IA64_UNAT_REGNUM		(IA64_AR0_REGNUM+36)
#define IA64_FPSR_REGNUM		(IA64_AR0_REGNUM+40)
#define IA64_ITC_REGNUM			(IA64_AR0_REGNUM+44)
#define IA64_PFS_REGNUM			(IA64_AR0_REGNUM+64)
#define IA64_LC_REGNUM			(IA64_AR0_REGNUM+65)
#define IA64_EC_REGNUM			(IA64_AR0_REGNUM+66)

#ifndef USE_UNWIND
struct regs_to_cpu_user_resgs_index {
	unsigned int reg;
	unsigned int ptregoff;
};

#define ptoff(V)		((unsigned int)&((struct cpu_user_regs*)0x0)->V)

// gr
static const struct regs_to_cpu_user_resgs_index
gr_reg_to_cpu_user_regs_index[] = {
	{IA64_GR0_REGNUM + 8,  ptoff(r8)},
	{IA64_GR0_REGNUM + 9,  ptoff(r9)},
	{IA64_GR0_REGNUM + 10, ptoff(r10)},
	{IA64_GR0_REGNUM + 11, ptoff(r11)},
	{IA64_GR0_REGNUM + 1,  ptoff(r1)},
	{IA64_GR0_REGNUM + 12, ptoff(r12)},
	{IA64_GR0_REGNUM + 13, ptoff(r13)},
	{IA64_GR0_REGNUM + 15, ptoff(r15)},

	{IA64_GR0_REGNUM + 14, ptoff(r14)},
	{IA64_GR0_REGNUM + 2,  ptoff(r2)},
	{IA64_GR0_REGNUM + 3,  ptoff(r3)},
	{IA64_GR0_REGNUM + 16, ptoff(r16)},
	{IA64_GR0_REGNUM + 17, ptoff(r17)},
	{IA64_GR0_REGNUM + 18, ptoff(r18)},
	{IA64_GR0_REGNUM + 19, ptoff(r19)},
	{IA64_GR0_REGNUM + 20, ptoff(r20)},
	{IA64_GR0_REGNUM + 21, ptoff(r21)},
	{IA64_GR0_REGNUM + 22, ptoff(r22)},
	{IA64_GR0_REGNUM + 23, ptoff(r23)},
	{IA64_GR0_REGNUM + 24, ptoff(r24)},
	{IA64_GR0_REGNUM + 25, ptoff(r25)},
	{IA64_GR0_REGNUM + 26, ptoff(r26)},
	{IA64_GR0_REGNUM + 27, ptoff(r27)},
	{IA64_GR0_REGNUM + 28, ptoff(r28)},
	{IA64_GR0_REGNUM + 29, ptoff(r29)},
	{IA64_GR0_REGNUM + 30, ptoff(r30)},
	{IA64_GR0_REGNUM + 31, ptoff(r31)},

	{IA64_GR0_REGNUM + 4,  ptoff(r4)},
	{IA64_GR0_REGNUM + 5,  ptoff(r5)},
	{IA64_GR0_REGNUM + 6,  ptoff(r6)},
	{IA64_GR0_REGNUM + 7,  ptoff(r7)},
};
static const int gr_reg_to_cpu_user_regs_index_max =
	sizeof(gr_reg_to_cpu_user_regs_index) /
	sizeof(gr_reg_to_cpu_user_regs_index[0]); 

// br
static const struct regs_to_cpu_user_resgs_index
br_reg_to_cpu_user_regs_index[] = {
	{IA64_BR0_REGNUM + 0, ptoff(b0)},
	{IA64_BR0_REGNUM + 6, ptoff(b6)},
	{IA64_BR0_REGNUM + 7, ptoff(b7)},
};
static const int br_reg_to_cpu_user_regs_index_max =
	sizeof(br_reg_to_cpu_user_regs_index) /
	sizeof(br_reg_to_cpu_user_regs_index[0]); 

// f
static const struct regs_to_cpu_user_resgs_index
fr_reg_to_cpu_user_regs_index[] = {
	{IA64_FR0_REGNUM + 6,  ptoff(f6)},
	{IA64_FR0_REGNUM + 7,  ptoff(f7)},
	{IA64_FR0_REGNUM + 8,  ptoff(f8)},
	{IA64_FR0_REGNUM + 9,  ptoff(f9)},
	{IA64_FR0_REGNUM + 10, ptoff(f10)},
	{IA64_FR0_REGNUM + 11, ptoff(f11)},
};
static const int fr_reg_to_cpu_user_regs_index_max =
	sizeof(fr_reg_to_cpu_user_regs_index) /
	sizeof(fr_reg_to_cpu_user_regs_index[0]); 
	

void 
gdb_arch_read_reg(unsigned long regnum, struct cpu_user_regs *regs,
                  struct gdb_context *ctx)
{
	unsigned long reg = IA64_IP_REGNUM;
	char buf[9];
	int i;

	dbg_printk("Register read regnum = 0x%lx\n", regnum);
	if (IA64_GR0_REGNUM <= regnum && regnum <= IA64_GR0_REGNUM + 31) {
		for (i = 0; i < gr_reg_to_cpu_user_regs_index_max; i++) {
			if (gr_reg_to_cpu_user_regs_index[i].reg == regnum) {
				reg = *(unsigned long*)(((char*)regs) + gr_reg_to_cpu_user_regs_index[i].ptregoff);
				break;
			}
		}
		if (i == gr_reg_to_cpu_user_regs_index_max) {
			goto out_err;
		}
	} else if (IA64_BR0_REGNUM <= regnum && regnum <= IA64_BR0_REGNUM + 7) {
		for (i = 0; i < br_reg_to_cpu_user_regs_index_max; i++) {
			if (br_reg_to_cpu_user_regs_index[i].reg == regnum) {
				reg = *(unsigned long*)(((char*)regs) + br_reg_to_cpu_user_regs_index[i].ptregoff);
				break;
			}
		}
		if (i == br_reg_to_cpu_user_regs_index_max) {
			goto out_err;
		}
	} else if (IA64_FR0_REGNUM + 6 <= regnum && regnum <= IA64_FR0_REGNUM + 11) {
		for (i = 0; i < fr_reg_to_cpu_user_regs_index_max; i++) {
			if (fr_reg_to_cpu_user_regs_index[i].reg == regnum) {
				reg = *(unsigned long*)(((char*)regs) + fr_reg_to_cpu_user_regs_index[i].ptregoff);
				break;
			}
		}
		if (i == fr_reg_to_cpu_user_regs_index_max) {
			goto out_err;
		}
	} else if (regnum == IA64_CSD_REGNUM) {
		reg = regs->ar_csd;
	} else if (regnum == IA64_SSD_REGNUM) {
		reg = regs->ar_ssd;
	} else if (regnum == IA64_PSR_REGNUM) {
		reg = regs->cr_ipsr;
	} else if (regnum == IA64_IP_REGNUM) {
		reg = regs->cr_iip;
	} else if (regnum == IA64_CFM_REGNUM) {
		reg = regs->cr_ifs;
	} else if (regnum == IA64_UNAT_REGNUM) {
		reg = regs->ar_unat;
	} else if (regnum == IA64_PFS_REGNUM) {
		reg = regs->ar_pfs;
	} else if (regnum == IA64_RSC_REGNUM) {
		reg = regs->ar_rsc;
	} else if (regnum == IA64_RNAT_REGNUM) {
		reg = regs->ar_rnat;
	} else if (regnum == IA64_BSPSTORE_REGNUM) {
		reg = regs->ar_bspstore;
	} else if (regnum == IA64_PR_REGNUM) {
		reg = regs->pr;
	} else if (regnum == IA64_FPSR_REGNUM) {
		reg = regs->ar_fpsr;
	} else if (regnum == IA64_CCV_REGNUM) {
		reg = regs->ar_ccv;
	} else {
		// emul_unat, rfi_pfs
		goto out_err;
	}

	dbg_printk("Register read regnum = 0x%lx, val = 0x%lx\n", regnum, reg);	
	sprintf(buf, "%.08lx", swab64(reg));
out:
	return gdb_send_reply(buf, ctx);

out_err:
	dbg_printk("Register read unsupported regnum = 0x%lx\n", regnum);
	sprintf(buf, "%s", "x");
	goto out;
}
#else

#define	ptoff(V)	((unsigned int) &((struct pt_regs *)0x0)->V)
struct reg_to_ptreg_index {
	unsigned int reg;
	unsigned int ptregoff;
};

static struct reg_to_ptreg_index gr_reg_to_ptreg_index[] = {
	{IA64_GR0_REGNUM + 1, ptoff(r1)},
	{IA64_GR0_REGNUM + 2, ptoff(r2)},
	{IA64_GR0_REGNUM + 3, ptoff(r3)},
	{IA64_GR0_REGNUM + 8, ptoff(r8)},
	{IA64_GR0_REGNUM + 9, ptoff(r9)},
	{IA64_GR0_REGNUM + 10, ptoff(r10)},
	{IA64_GR0_REGNUM + 11, ptoff(r11)},
	{IA64_GR0_REGNUM + 12, ptoff(r12)},
	{IA64_GR0_REGNUM + 13, ptoff(r13)},
	{IA64_GR0_REGNUM + 14, ptoff(r14)},
	{IA64_GR0_REGNUM + 15, ptoff(r15)},
	{IA64_GR0_REGNUM + 16, ptoff(r16)},
	{IA64_GR0_REGNUM + 17, ptoff(r17)},
	{IA64_GR0_REGNUM + 18, ptoff(r18)},
	{IA64_GR0_REGNUM + 19, ptoff(r19)},
	{IA64_GR0_REGNUM + 20, ptoff(r20)},
	{IA64_GR0_REGNUM + 21, ptoff(r21)},
	{IA64_GR0_REGNUM + 22, ptoff(r22)},
	{IA64_GR0_REGNUM + 23, ptoff(r23)},
	{IA64_GR0_REGNUM + 24, ptoff(r24)},
	{IA64_GR0_REGNUM + 25, ptoff(r25)},
	{IA64_GR0_REGNUM + 26, ptoff(r26)},
	{IA64_GR0_REGNUM + 27, ptoff(r27)},
	{IA64_GR0_REGNUM + 28, ptoff(r28)},
	{IA64_GR0_REGNUM + 29, ptoff(r29)},
	{IA64_GR0_REGNUM + 30, ptoff(r30)},
	{IA64_GR0_REGNUM + 31, ptoff(r31)},
};

static struct reg_to_ptreg_index br_reg_to_ptreg_index[] = {
	{IA64_BR0_REGNUM, ptoff(b0)},
	{IA64_BR0_REGNUM + 6, ptoff(b6)},
	{IA64_BR0_REGNUM + 7, ptoff(b7)},
};

static struct reg_to_ptreg_index ar_reg_to_ptreg_index[] = {
	{IA64_PFS_REGNUM, ptoff(ar_pfs)},
	{IA64_UNAT_REGNUM, ptoff(ar_unat)},
	{IA64_RNAT_REGNUM, ptoff(ar_rnat)},
	{IA64_BSPSTORE_REGNUM, ptoff(ar_bspstore)},
	{IA64_RSC_REGNUM, ptoff(ar_rsc)},
	{IA64_CSD_REGNUM, ptoff(ar_csd)},
	{IA64_SSD_REGNUM, ptoff(ar_ssd)},
	{IA64_FPSR_REGNUM, ptoff(ar_fpsr)},
	{IA64_CCV_REGNUM, ptoff(ar_ccv)},
};

#ifndef XEN
extern atomic_t cpu_doing_single_step;
#endif

static int kgdb_gr_reg(int regnum, struct unw_frame_info *info,
	unsigned long *reg, int rw)
{
	char nat;

	if ((regnum >= IA64_GR0_REGNUM && regnum <= (IA64_GR0_REGNUM + 1)) ||
		(regnum >= (IA64_GR0_REGNUM + 4) &&
		regnum <= (IA64_GR0_REGNUM + 7)))
		return !unw_access_gr(info, regnum - IA64_GR0_REGNUM,
		reg, &nat, rw);
	else
		return 0;
}
static int kgdb_gr_ptreg(int regnum, struct pt_regs * ptregs,
	struct unw_frame_info *info, unsigned long *reg, int rw)
{
	int i, result = 1;
	char nat;

	if (!((regnum >= (IA64_GR0_REGNUM + 2) &&
		regnum <= (IA64_GR0_REGNUM + 3)) ||
		(regnum >= (IA64_GR0_REGNUM + 8) &&
		regnum <= (IA64_GR0_REGNUM + 15)) ||
		(regnum >= (IA64_GR0_REGNUM + 16) &&
		regnum <= (IA64_GR0_REGNUM + 31))))
		return 0;
	else if (rw && ptregs) {
		for (i = 0; i < ARRAY_SIZE(gr_reg_to_ptreg_index); i++)
			if (gr_reg_to_ptreg_index[i].reg == regnum) {
				*((unsigned long *)(((void *)ptregs) +
				gr_reg_to_ptreg_index[i].ptregoff)) = *reg;
				break;
			}
	} else if (!rw && ptregs) {
		for (i = 0; i < ARRAY_SIZE(gr_reg_to_ptreg_index); i++)
			if (gr_reg_to_ptreg_index[i].reg == regnum) {
				*reg = *((unsigned long *)
				(((void *)ptregs) +
				 gr_reg_to_ptreg_index[i].ptregoff));
				break;
			}
	} else
		result = !unw_access_gr(info, regnum - IA64_GR0_REGNUM,
					reg, &nat, rw);
	return result;
}

static int kgdb_br_reg(int regnum, struct pt_regs * ptregs,
	struct unw_frame_info *info, unsigned long *reg, int rw)
{
	int i, result = 1;

	if (!(regnum >= IA64_BR0_REGNUM && regnum <= (IA64_BR0_REGNUM + 7)))
		return 0;

	switch (regnum) {
	case IA64_BR0_REGNUM:
	case IA64_BR0_REGNUM + 6:
	case IA64_BR0_REGNUM + 7:
		if (rw) {
			for (i = 0; i < ARRAY_SIZE(br_reg_to_ptreg_index); i++)
				if (br_reg_to_ptreg_index[i].reg == regnum) {
					*((unsigned long *)
					(((void *)ptregs) +
					br_reg_to_ptreg_index[i].ptregoff)) =
					*reg;
					break;
				}
		} else
			for (i = 0; i < ARRAY_SIZE(br_reg_to_ptreg_index); i++)
				if (br_reg_to_ptreg_index[i].reg == regnum) {
						*reg = *((unsigned long *)
						(((void *)ptregs) +
						br_reg_to_ptreg_index[i].
						ptregoff));
						break;
				}
		break;
	case IA64_BR0_REGNUM + 1:
	case IA64_BR0_REGNUM + 2:
	case IA64_BR0_REGNUM + 3:
	case IA64_BR0_REGNUM + 4:
	case IA64_BR0_REGNUM + 5:
		result = !unw_access_br(info, regnum - IA64_BR0_REGNUM,
				reg, rw);
		break;
	}

	return result;
}

static int kgdb_fr_reg(int regnum, char *inbuffer, struct pt_regs * ptregs,
	struct unw_frame_info *info, unsigned long *reg,
	struct ia64_fpreg *freg, int rw)
{
	int result = 1;

	if (!(regnum >= IA64_FR0_REGNUM && regnum <= (IA64_FR0_REGNUM + 127)))
		return 0;

	switch (regnum) {
	case IA64_FR0_REGNUM + 6:
	case IA64_FR0_REGNUM + 7:
	case IA64_FR0_REGNUM + 8:
	case IA64_FR0_REGNUM + 9:
	case IA64_FR0_REGNUM + 10:
	case IA64_FR0_REGNUM + 11:
	case IA64_FR0_REGNUM + 12:
		if (rw) {
#ifndef XEN
			char *ptr = inbuffer;

			freg->u.bits[0] = *reg;
			kgdb_hex2long(&ptr, &freg->u.bits[1]);
			*(&ptregs->f6 + (regnum - (IA64_FR0_REGNUM + 6))) =
				*freg;
#else
			printk("%s: %d: writing to fpreg is not supported.\n",
				   __func__, __LINE__);
#endif
			break;
		} else if (!ptregs)
			result = !unw_access_fr(info, regnum - IA64_FR0_REGNUM,
				freg, rw);
		else
#ifndef XEN
			*freg =
			*(&ptregs->f6 + (regnum - (IA64_FR0_REGNUM + 6)));
#else
		    //XXX struct ia64_fpreg and struct pt_fpreg are same.
			*freg = *((struct ia64_fpreg*)(&ptregs->f6 +
										   (regnum - (IA64_FR0_REGNUM + 6))));
#endif
		break;
	default:
		if (!rw)
			result = !unw_access_fr(info, regnum - IA64_FR0_REGNUM,
				freg, rw);
		else
			result = 0;
		break;
	}

	return result;
}

static int kgdb_ar_reg(int regnum, struct pt_regs * ptregs,
	struct unw_frame_info *info, unsigned long *reg, int rw)
{
	int result = 0, i;

	if (!(regnum >= IA64_AR0_REGNUM && regnum <= IA64_EC_REGNUM))
		return 0;

	if (rw && ptregs) {
		for (i = 0; i < ARRAY_SIZE(ar_reg_to_ptreg_index); i++)
			if (ar_reg_to_ptreg_index[i].reg == regnum) {
				*((unsigned long *) (((void *)ptregs) +
				ar_reg_to_ptreg_index[i].ptregoff)) =
					*reg;
				result = 1;
				break;
			}
	} else if (ptregs) {
		for (i = 0; i < ARRAY_SIZE(ar_reg_to_ptreg_index); i++)
			if (ar_reg_to_ptreg_index[i].reg == regnum) {
				*reg = *((unsigned long *) (((void *)ptregs) +
					ar_reg_to_ptreg_index[i].ptregoff));
					result = 1;
				break;
			}
	}

	if (result)
		return result;

       result = 1;

	switch (regnum) {
	case IA64_CSD_REGNUM:
		result = !unw_access_ar(info, UNW_AR_CSD, reg, rw);
		break;
	case IA64_SSD_REGNUM: