// Whatever the initial content of this memory is at reset, it will never change // see demo3.smtc for assumptions and assertions module demo3(input clk, rst, input [15:0] addr, output reg [31:0] data); reg [31:0] mem [0:2**16-1]; reg [15:0] addr_q; always @(posedge clk) begin if (rst) begin data <= mem[0] ^ 123456789; addr_q <= 0; end else begin mem[addr_q] <= data ^ 123456789; data <= mem[addr] ^ 123456789; addr_q <= addr; end end endmodule le='openwrt/upstream Git repository'/>
aboutsummaryrefslogtreecommitdiffstats
path: root/target/linux/x86/modules.mk
blob: 4005ee97ef098c4cc91083a243cfa80c41f95b0d (plain) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104