From 3c5a9411b1c17d9e4474fb7edb54117c2298cfc1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 11 Dec 2019 12:10:30 -0800
Subject: Add testcase for $_DFF_[NP][NP][01]_

---
 tests/techmap/zinit.ys | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 tests/techmap/zinit.ys

(limited to 'tests')

diff --git a/tests/techmap/zinit.ys b/tests/techmap/zinit.ys
new file mode 100644
index 000000000..3652f2d72
--- /dev/null
+++ b/tests/techmap/zinit.ys
@@ -0,0 +1,24 @@
+read_verilog -icells <<EOT
+module top(input C, D, S, R, output [16:0] Q);
+(* init = {17{1'b1}} *)
+wire [16:0] Q;
+$_DFF_NN0_ dff0 (.C(C), .D(D), .R(R), .Q(Q[0]));
+$_DFF_NN1_ dff1 (.C(C), .D(D), .R(R), .Q(Q[1]));
+$_DFF_NP0_ dff2 (.C(C), .D(D), .R(R), .Q(Q[2]));
+$_DFF_NP1_ dff3 (.C(C), .D(D), .R(R), .Q(Q[3]));
+$_DFF_PN0_ dff4 (.C(C), .D(D), .R(R), .Q(Q[4]));
+$_DFF_PN1_ dff5 (.C(C), .D(D), .R(R), .Q(Q[5]));
+$_DFF_PP0_ dff6 (.C(C), .D(D), .R(R), .Q(Q[6]));
+$_DFF_PP1_ dff7 (.C(C), .D(D), .R(R), .Q(Q[7]));
+
+//$_DFFSR_NNN_ dffsr0 (.C(C), .D(D), .S(S), .R(R), .Q(Q[8]));
+//$_DFFSR_NNP_ dffsr1 (.C(C), .D(D), .S(S), .R(R), .Q(Q[9]));
+//$_DFFSR_NPN_ dffsr2 (.C(C), .D(D), .S(S), .R(R), .Q(Q[10]));
+//$_DFFSR_NPP_ dffsr3 (.C(C), .D(D), .S(S), .R(R), .Q(Q[11]));
+//$_DFFSR_PNN_ dffsr4 (.C(C), .D(D), .S(S), .R(R), .Q(Q[12]));
+//$_DFFSR_PNP_ dffsr5 (.C(C), .D(D), .S(S), .R(R), .Q(Q[13]));
+//$_DFFSR_PPN_ dffsr6 (.C(C), .D(D), .S(S), .R(R), .Q(Q[14]));
+//$_DFFSR_PPP_ dffsr7 (.C(C), .D(D), .S(S), .R(R), .Q(Q[15]));
+endmodule
+EOT
+equiv_opt -map +/simcells.v -multiclock zinit
-- 
cgit v1.2.3


From 091297b9ee9c7874f17abb855f6c612c448cec70 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 13 Apr 2020 14:29:44 -0700
Subject: tests: zinit on $adff

---
 tests/techmap/zinit.ys | 37 ++++++++++++++++++-------------------
 1 file changed, 18 insertions(+), 19 deletions(-)

(limited to 'tests')

diff --git a/tests/techmap/zinit.ys b/tests/techmap/zinit.ys
index 3652f2d72..caeab69d3 100644
--- a/tests/techmap/zinit.ys
+++ b/tests/techmap/zinit.ys
@@ -1,24 +1,23 @@
 read_verilog -icells <<EOT
-module top(input C, D, S, R, output [16:0] Q);
-(* init = {17{1'b1}} *)
-wire [16:0] Q;
-$_DFF_NN0_ dff0 (.C(C), .D(D), .R(R), .Q(Q[0]));
-$_DFF_NN1_ dff1 (.C(C), .D(D), .R(R), .Q(Q[1]));
-$_DFF_NP0_ dff2 (.C(C), .D(D), .R(R), .Q(Q[2]));
-$_DFF_NP1_ dff3 (.C(C), .D(D), .R(R), .Q(Q[3]));
-$_DFF_PN0_ dff4 (.C(C), .D(D), .R(R), .Q(Q[4]));
-$_DFF_PN1_ dff5 (.C(C), .D(D), .R(R), .Q(Q[5]));
-$_DFF_PP0_ dff6 (.C(C), .D(D), .R(R), .Q(Q[6]));
-$_DFF_PP1_ dff7 (.C(C), .D(D), .R(R), .Q(Q[7]));
+module top(input C, R, input [1:0] D, (* init = {12{1'b1}} *) output [11:0] Q);
 
-//$_DFFSR_NNN_ dffsr0 (.C(C), .D(D), .S(S), .R(R), .Q(Q[8]));
-//$_DFFSR_NNP_ dffsr1 (.C(C), .D(D), .S(S), .R(R), .Q(Q[9]));
-//$_DFFSR_NPN_ dffsr2 (.C(C), .D(D), .S(S), .R(R), .Q(Q[10]));
-//$_DFFSR_NPP_ dffsr3 (.C(C), .D(D), .S(S), .R(R), .Q(Q[11]));
-//$_DFFSR_PNN_ dffsr4 (.C(C), .D(D), .S(S), .R(R), .Q(Q[12]));
-//$_DFFSR_PNP_ dffsr5 (.C(C), .D(D), .S(S), .R(R), .Q(Q[13]));
-//$_DFFSR_PPN_ dffsr6 (.C(C), .D(D), .S(S), .R(R), .Q(Q[14]));
-//$_DFFSR_PPP_ dffsr7 (.C(C), .D(D), .S(S), .R(R), .Q(Q[15]));
+(* init = 1'b1 *)
+wire unused;
+
+$_DFF_NN0_ dff0 (.C(C), .D(D[0]), .R(R), .Q(Q[0]));
+$_DFF_NN1_ dff1 (.C(C), .D(D[0]), .R(R), .Q(Q[1]));
+$_DFF_NP0_ dff2 (.C(C), .D(D[0]), .R(R), .Q(Q[2]));
+$_DFF_NP1_ dff3 (.C(C), .D(D[0]), .R(R), .Q(Q[3]));
+$_DFF_PN0_ dff4 (.C(C), .D(D[0]), .R(R), .Q(Q[4]));
+$_DFF_PN1_ dff5 (.C(C), .D(D[0]), .R(R), .Q(Q[5]));
+$_DFF_PP0_ dff6 (.C(C), .D(D[0]), .R(R), .Q(Q[6]));
+$_DFF_PP1_ dff7 (.C(C), .D(D[0]), .R(R), .Q(Q[7]));
+
+$adff #(.WIDTH(2), .CLK_POLARITY(1), .ARST_POLARITY(1'b0), .ARST_VALUE(2'd2)) dff8 (.CLK(C), .ARST(R), .D(D), .Q(Q[9:8]));
+$adff #(.WIDTH(2), .CLK_POLARITY(0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'd1)) dff9 (.CLK(C), .ARST(R), .D(D), .Q(Q[11:10]));
 endmodule
 EOT
 equiv_opt -map +/simcells.v -multiclock zinit
+design -load postopt
+
+select -assert-count 1 w:unused a:init %i
-- 
cgit v1.2.3


From c6afce763807862305c4ade28ef5bb72a4b078f6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 13 Apr 2020 15:16:51 -0700
Subject: zinit: fix review comments from @mwkmwkmwk

---
 tests/techmap/zinit.ys | 35 +++++++++++++++++++++++++++++++----
 1 file changed, 31 insertions(+), 4 deletions(-)

(limited to 'tests')

diff --git a/tests/techmap/zinit.ys b/tests/techmap/zinit.ys
index caeab69d3..c74218f7c 100644
--- a/tests/techmap/zinit.ys
+++ b/tests/techmap/zinit.ys
@@ -1,5 +1,5 @@
 read_verilog -icells <<EOT
-module top(input C, R, input [1:0] D, (* init = {12{1'b1}} *) output [11:0] Q);
+module top(input C, R, input [1:0] D, (* init = {2'b10, 2'b01, 1'b1, {8{1'b1}}} *) output [12:0] Q);
 
 (* init = 1'b1 *)
 wire unused;
@@ -13,11 +13,38 @@ $_DFF_PN1_ dff5 (.C(C), .D(D[0]), .R(R), .Q(Q[5]));
 $_DFF_PP0_ dff6 (.C(C), .D(D[0]), .R(R), .Q(Q[6]));
 $_DFF_PP1_ dff7 (.C(C), .D(D[0]), .R(R), .Q(Q[7]));
 
-$adff #(.WIDTH(2), .CLK_POLARITY(1), .ARST_POLARITY(1'b0), .ARST_VALUE(2'd2)) dff8 (.CLK(C), .ARST(R), .D(D), .Q(Q[9:8]));
-$adff #(.WIDTH(2), .CLK_POLARITY(0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'd1)) dff9 (.CLK(C), .ARST(R), .D(D), .Q(Q[11:10]));
+$adff #(.WIDTH(2), .CLK_POLARITY(1), .ARST_POLARITY(1'b0), .ARST_VALUE(2'b10)) dff8 (.CLK(C), .ARST(R), .D(D), .Q(Q[10:9]));
+$adff #(.WIDTH(2), .CLK_POLARITY(0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'b01)) dff9 (.CLK(C), .ARST(R), .D(D), .Q(Q[12:11]));
 endmodule
 EOT
-equiv_opt -map +/simcells.v -multiclock zinit
+equiv_opt -assert -map +/simcells.v -multiclock zinit
 design -load postopt
 
+select -assert-count 20 t:$_NOT_
 select -assert-count 1 w:unused a:init %i
+select -assert-count 1 w:Q a:init=13'bxxxx1xxxxxxxx %i
+
+
+design -reset
+read_verilog -icells <<EOT
+module top(input C, R, input [1:0] D, (* init = {2'bx0, 2'b0x, 1'b1, {8{1'b0}}} *) output [12:0] Q);
+
+(* init = 1'b1 *)
+wire unused;
+
+$_DFF_NN0_ dff0 (.C(C), .D(D[0]), .R(R), .Q(Q[0]));
+$_DFF_NN1_ dff1 (.C(C), .D(D[0]), .R(R), .Q(Q[1]));
+$_DFF_NP0_ dff2 (.C(C), .D(D[0]), .R(R), .Q(Q[2]));
+$_DFF_NP1_ dff3 (.C(C), .D(D[0]), .R(R), .Q(Q[3]));
+$_DFF_PN0_ dff4 (.C(C), .D(D[0]), .R(R), .Q(Q[4]));
+$_DFF_PN1_ dff5 (.C(C), .D(D[0]), .R(R), .Q(Q[5]));
+$_DFF_PP0_ dff6 (.C(C), .D(D[0]), .R(R), .Q(Q[6]));
+$_DFF_PP1_ dff7 (.C(C), .D(D[0]), .R(R), .Q(Q[7]));
+
+$adff #(.WIDTH(2), .CLK_POLARITY(1), .ARST_POLARITY(1'b0), .ARST_VALUE(2'b10)) dff8 (.CLK(C), .ARST(R), .D(D), .Q(Q[10:9]));
+$adff #(.WIDTH(2), .CLK_POLARITY(0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'b01)) dff9 (.CLK(C), .ARST(R), .D(D), .Q(Q[12:11]));
+endmodule
+EOT
+select -assert-count 0 t:$_NOT_
+select -assert-count 1 w:unused a:init %i
+select -assert-count 1 w:Q a:init=13'bx00x100000000 %i
-- 
cgit v1.2.3


From b75c5bf74374156c802461acf0a868f7e5fad3fd Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 13 Apr 2020 15:25:37 -0700
Subject: zinit: resolve one more comment by @mwkmwkmwk

---
 tests/techmap/zinit.ys | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/techmap/zinit.ys b/tests/techmap/zinit.ys
index c74218f7c..18b17621f 100644
--- a/tests/techmap/zinit.ys
+++ b/tests/techmap/zinit.ys
@@ -23,6 +23,8 @@ design -load postopt
 select -assert-count 20 t:$_NOT_
 select -assert-count 1 w:unused a:init %i
 select -assert-count 1 w:Q a:init=13'bxxxx1xxxxxxxx %i
+select -assert-count 4 c:dff0 c:dff2 c:dff4 c:dff6 %% t:$_DFF_??1_ %i
+select -assert-count 4 c:dff1 c:dff3 c:dff5 c:dff7 %% t:$_DFF_??0_ %i
 
 
 design -reset
@@ -45,6 +47,11 @@ $adff #(.WIDTH(2), .CLK_POLARITY(1), .ARST_POLARITY(1'b0), .ARST_VALUE(2'b10)) d
 $adff #(.WIDTH(2), .CLK_POLARITY(0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'b01)) dff9 (.CLK(C), .ARST(R), .D(D), .Q(Q[12:11]));
 endmodule
 EOT
+equiv_opt -assert -map +/simcells.v -multiclock zinit
+design -load postopt
+
 select -assert-count 0 t:$_NOT_
 select -assert-count 1 w:unused a:init %i
-select -assert-count 1 w:Q a:init=13'bx00x100000000 %i
+select -assert-count 1 w:Q a:init=13'bxxxx1xxxxxxxx %i
+select -assert-count 4 c:dff0 c:dff2 c:dff4 c:dff6 %% t:$_DFF_??0_ %i
+select -assert-count 4 c:dff1 c:dff3 c:dff5 c:dff7 %% t:$_DFF_??1_ %i
-- 
cgit v1.2.3