From 3839bd50f28a16f1253a56d5871465763e72180c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 19 Jul 2019 12:43:02 -0700
Subject: Add test

---
 tests/various/wreduce.ys | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 tests/various/wreduce.ys

(limited to 'tests')

diff --git a/tests/various/wreduce.ys b/tests/various/wreduce.ys
new file mode 100644
index 000000000..0b5403fa1
--- /dev/null
+++ b/tests/various/wreduce.ys
@@ -0,0 +1,22 @@
+
+read_verilog <<EOT
+module wreduce_add_test(input [3:0] i, input [7:0] j, output [7:0] o);
+    assign o = (i << 4) + j;
+endmodule
+EOT
+
+hierarchy -top wreduce_add_test
+proc
+design -save gold
+
+prep
+
+select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 %i %i
+
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
-- 
cgit v1.2.3


From 4e9b1d36fa896a8280e9c4295cf9a4e2a084f927 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 19 Jul 2019 12:50:11 -0700
Subject: Add tests for sub too

---
 tests/various/wreduce.ys | 49 +++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 48 insertions(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/various/wreduce.ys b/tests/various/wreduce.ys
index 0b5403fa1..ee03e008d 100644
--- a/tests/various/wreduce.ys
+++ b/tests/various/wreduce.ys
@@ -5,7 +5,7 @@ module wreduce_add_test(input [3:0] i, input [7:0] j, output [7:0] o);
 endmodule
 EOT
 
-hierarchy -top wreduce_add_test
+hierarchy -auto-top
 proc
 design -save gold
 
@@ -20,3 +20,50 @@ design -import gate -as gate
 
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
+
+
+### X - 0
+read_verilog <<EOT
+module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [7:0] o);
+    assign o = j - (i << 4);
+endmodule
+EOT
+
+hierarchy -auto-top
+proc
+design -save gold
+
+prep
+
+select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 %i %i
+
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+### 0 - X
+read_verilog <<EOT
+module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [7:0] o);
+    assign o = (i << 4) - j;
+endmodule
+EOT
+
+hierarchy -auto-top
+proc
+design -save gold
+
+prep
+
+select -assert-count 1 t:$sub r:A_WIDTH=8 r:B_WIDTH=8 %i %i
+
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
-- 
cgit v1.2.3


From 415a2716df8c41193650804158281ef73e7fc655 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 19 Jul 2019 12:53:18 -0700
Subject: Be more explicit

---
 tests/various/wreduce.ys | 35 +++++++++++++++++++++++++++++------
 1 file changed, 29 insertions(+), 6 deletions(-)

(limited to 'tests')

diff --git a/tests/various/wreduce.ys b/tests/various/wreduce.ys
index ee03e008d..f9e5ed4e3 100644
--- a/tests/various/wreduce.ys
+++ b/tests/various/wreduce.ys
@@ -1,6 +1,6 @@
 
 read_verilog <<EOT
-module wreduce_add_test(input [3:0] i, input [7:0] j, output [7:0] o);
+module wreduce_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
     assign o = (i << 4) + j;
 endmodule
 EOT
@@ -11,7 +11,7 @@ design -save gold
 
 prep
 
-select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 %i %i
+select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
 
 design -stash gate
 
@@ -24,7 +24,7 @@ sat -verify -prove-asserts -show-ports miter
 
 ### X - 0
 read_verilog <<EOT
-module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [7:0] o);
+module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
     assign o = j - (i << 4);
 endmodule
 EOT
@@ -35,7 +35,7 @@ design -save gold
 
 prep
 
-select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 %i %i
+select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
 
 design -stash gate
 
@@ -47,7 +47,7 @@ sat -verify -prove-asserts -show-ports miter
 
 ### 0 - X
 read_verilog <<EOT
-module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [7:0] o);
+module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
     assign o = (i << 4) - j;
 endmodule
 EOT
@@ -58,7 +58,30 @@ design -save gold
 
 prep
 
-select -assert-count 1 t:$sub r:A_WIDTH=8 r:B_WIDTH=8 %i %i
+select -assert-count 1 t:$sub r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
+
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+### 0 - X
+read_verilog <<EOT
+module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
+    assign o = (i << 4) - j;
+endmodule
+EOT
+
+hierarchy -auto-top
+proc
+design -save gold
+
+prep
+
+select -assert-count 1 t:$sub r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
 
 design -stash gate
 
-- 
cgit v1.2.3


From 5bd088a686ce040c39a8353cf3a7cfe31581d635 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 19 Jul 2019 13:11:30 -0700
Subject: Add one more test with trimming Y_WIDTH of $sub

---
 tests/various/wreduce.ys | 25 ++++++++++++++-----------
 1 file changed, 14 insertions(+), 11 deletions(-)

(limited to 'tests')

diff --git a/tests/various/wreduce.ys b/tests/various/wreduce.ys
index f9e5ed4e3..8030c005e 100644
--- a/tests/various/wreduce.ys
+++ b/tests/various/wreduce.ys
@@ -9,7 +9,7 @@ hierarchy -auto-top
 proc
 design -save gold
 
-prep
+prep # calls wreduce
 
 select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
 
@@ -21,8 +21,8 @@ design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
 
+##########
 
-### X - 0
 read_verilog <<EOT
 module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
     assign o = j - (i << 4);
@@ -33,7 +33,7 @@ hierarchy -auto-top
 proc
 design -save gold
 
-prep
+prep # calls wreduce
 
 select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
 
@@ -45,9 +45,10 @@ design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
 
-### 0 - X
+##########
+
 read_verilog <<EOT
-module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
+module wreduce_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o);
     assign o = (i << 4) - j;
 endmodule
 EOT
@@ -56,7 +57,7 @@ hierarchy -auto-top
 proc
 design -save gold
 
-prep
+prep # calls wreduce
 
 select -assert-count 1 t:$sub r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
 
@@ -68,10 +69,11 @@ design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
 
-### 0 - X
+##########
+
 read_verilog <<EOT
-module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
-    assign o = (i << 4) - j;
+module wreduce_sub_test3(input [3:0] i, input [7:0] j, output [8:0] o);
+    assign o = (j >> 4) - i;
 endmodule
 EOT
 
@@ -79,9 +81,10 @@ hierarchy -auto-top
 proc
 design -save gold
 
-prep
+prep # calls wreduce
 
-select -assert-count 1 t:$sub r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
+dump
+select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
 
 design -stash gate
 
-- 
cgit v1.2.3


From c926eeb43a9c42a0ecc34871f383f4181b7a45f9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 19 Jul 2019 14:02:46 -0700
Subject: Add another test

---
 tests/various/wreduce.ys | 25 ++++++++++++++++++++++++-
 1 file changed, 24 insertions(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/various/wreduce.ys b/tests/various/wreduce.ys
index 8030c005e..deb99304d 100644
--- a/tests/various/wreduce.ys
+++ b/tests/various/wreduce.ys
@@ -83,7 +83,6 @@ design -save gold
 
 prep # calls wreduce
 
-dump
 select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
 
 design -stash gate
@@ -93,3 +92,27 @@ design -import gate -as gate
 
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
+
+##########
+
+read_verilog <<EOT
+module wreduce_sub_test4(input [3:0] i, output [8:0] o);
+    assign o = 5'b00010 - i;
+endmodule
+EOT
+
+hierarchy -auto-top
+proc
+design -save gold
+
+prep # calls wreduce
+
+select -assert-count 1 t:$sub r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
+
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
-- 
cgit v1.2.3


From 51b39219cda35e782fe4372409edf5432f86741f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 6 Aug 2019 15:24:49 -0700
Subject: Move LSB tests from wreduce to opt_expr

---
 tests/various/opt_expr.ys |  98 ++++++++++++++++++++++++++++++++++++++++++++
 tests/various/wreduce.ys  | 102 ++--------------------------------------------
 2 files changed, 101 insertions(+), 99 deletions(-)
 create mode 100644 tests/various/opt_expr.ys

(limited to 'tests')

diff --git a/tests/various/opt_expr.ys b/tests/various/opt_expr.ys
new file mode 100644
index 000000000..2165802d6
--- /dev/null
+++ b/tests/various/opt_expr.ys
@@ -0,0 +1,98 @@
+
+read_verilog <<EOT
+module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
+    assign o = (i << 4) + j;
+endmodule
+EOT
+
+hierarchy -auto-top
+proc
+design -save gold
+
+opt_expr -fine
+wreduce
+
+select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
+
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+##########
+
+read_verilog <<EOT
+module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
+    assign o = j - (i << 4);
+endmodule
+EOT
+
+hierarchy -auto-top
+proc
+design -save gold
+
+opt_expr -fine
+wreduce
+
+select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
+
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+##########
+
+read_verilog <<EOT
+module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o);
+    assign o = (i << 4) - j;
+endmodule
+EOT
+
+hierarchy -auto-top
+proc
+design -save gold
+
+opt_expr -fine
+wreduce
+
+select -assert-count 1 t:$sub r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
+
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+##########
+
+read_verilog <<EOT
+module opt_expr_sub_test4(input [3:0] i, output [8:0] o);
+    assign o = 5'b00010 - i;
+endmodule
+EOT
+
+hierarchy -auto-top
+proc
+design -save gold
+
+opt_expr -fine
+wreduce
+
+select -assert-count 1 t:$sub r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
+
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
diff --git a/tests/various/wreduce.ys b/tests/various/wreduce.ys
index deb99304d..7e4f1765a 100644
--- a/tests/various/wreduce.ys
+++ b/tests/various/wreduce.ys
@@ -1,78 +1,5 @@
-
-read_verilog <<EOT
-module wreduce_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
-    assign o = (i << 4) + j;
-endmodule
-EOT
-
-hierarchy -auto-top
-proc
-design -save gold
-
-prep # calls wreduce
-
-select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
-
-design -stash gate
-
-design -import gold -as gold
-design -import gate -as gate
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-
-##########
-
-read_verilog <<EOT
-module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
-    assign o = j - (i << 4);
-endmodule
-EOT
-
-hierarchy -auto-top
-proc
-design -save gold
-
-prep # calls wreduce
-
-select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
-
-design -stash gate
-
-design -import gold -as gold
-design -import gate -as gate
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-
-##########
-
-read_verilog <<EOT
-module wreduce_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o);
-    assign o = (i << 4) - j;
-endmodule
-EOT
-
-hierarchy -auto-top
-proc
-design -save gold
-
-prep # calls wreduce
-
-select -assert-count 1 t:$sub r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
-
-design -stash gate
-
-design -import gold -as gold
-design -import gate -as gate
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-
-##########
-
 read_verilog <<EOT
-module wreduce_sub_test3(input [3:0] i, input [7:0] j, output [8:0] o);
+module wreduce_sub_test(input [3:0] i, input [7:0] j, output [8:0] o);
     assign o = (j >> 4) - i;
 endmodule
 EOT
@@ -81,7 +8,8 @@ hierarchy -auto-top
 proc
 design -save gold
 
-prep # calls wreduce
+opt_expr
+wreduce
 
 select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
 
@@ -92,27 +20,3 @@ design -import gate -as gate
 
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
-
-##########
-
-read_verilog <<EOT
-module wreduce_sub_test4(input [3:0] i, output [8:0] o);
-    assign o = 5'b00010 - i;
-endmodule
-EOT
-
-hierarchy -auto-top
-proc
-design -save gold
-
-prep # calls wreduce
-
-select -assert-count 1 t:$sub r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
-
-design -stash gate
-
-design -import gold -as gold
-design -import gate -as gate
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-- 
cgit v1.2.3


From 769c750c226cfde5efcd1f75940b25f51330d67b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 6 Aug 2019 15:38:43 -0700
Subject: Add signed test

---
 tests/various/wreduce.ys | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

(limited to 'tests')

diff --git a/tests/various/wreduce.ys b/tests/various/wreduce.ys
index 7e4f1765a..4257292f5 100644
--- a/tests/various/wreduce.ys
+++ b/tests/various/wreduce.ys
@@ -20,3 +20,29 @@ design -import gate -as gate
 
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
+
+##########
+
+read_verilog <<EOT
+module wreduce_sub_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
+    assign o = (j >>> 4) - i;
+endmodule
+EOT
+
+hierarchy -auto-top
+proc
+design -save gold
+
+opt_expr
+wreduce
+
+dump
+select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
+
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
-- 
cgit v1.2.3


From 2d1b517b01b6cd1ec35018d4c63aaa091fcc1917 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 6 Aug 2019 15:40:30 -0700
Subject: Add signed opt_expr tests

---
 tests/various/opt_expr.ys | 50 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

(limited to 'tests')

diff --git a/tests/various/opt_expr.ys b/tests/various/opt_expr.ys
index 2165802d6..0c61ac881 100644
--- a/tests/various/opt_expr.ys
+++ b/tests/various/opt_expr.ys
@@ -24,6 +24,31 @@ sat -verify -prove-asserts -show-ports miter
 
 ##########
 
+read_verilog <<EOT
+module opt_expr_add_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
+    assign o = (i << 4) + j;
+endmodule
+EOT
+
+hierarchy -auto-top
+proc
+design -save gold
+
+opt_expr -fine
+wreduce
+
+select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
+
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+##########
+
 read_verilog <<EOT
 module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
     assign o = j - (i << 4);
@@ -49,6 +74,31 @@ sat -verify -prove-asserts -show-ports miter
 
 ##########
 
+read_verilog <<EOT
+module opt_expr_sub_signed_test1(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
+    assign o = j - (i << 4);
+endmodule
+EOT
+
+hierarchy -auto-top
+proc
+design -save gold
+
+opt_expr -fine
+wreduce
+
+select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
+
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
+##########
+
 read_verilog <<EOT
 module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o);
     assign o = (i << 4) - j;
-- 
cgit v1.2.3