From bf046ba09c9f694517a73af28133917e76d4924a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 18:34:32 -0700
Subject: Add ice40_opt test

---
 tests/ice40/ice40_opt.ys | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 tests/ice40/ice40_opt.ys

(limited to 'tests')

diff --git a/tests/ice40/ice40_opt.ys b/tests/ice40/ice40_opt.ys
new file mode 100644
index 000000000..18e0d2b8a
--- /dev/null
+++ b/tests/ice40/ice40_opt.ys
@@ -0,0 +1,24 @@
+read_verilog -icells -formal <<EOT
+module top(input CI, I0, output CO, O);
+    wire A = 1'b0, B = 1'b0;
+	\$__ICE40_CARRY_WRAPPER #(
+		//    A[0]: 1010 1010 1010 1010
+		//    A[1]: 1100 1100 1100 1100
+		//    A[2]: 1111 0000 1111 0000
+		//    A[3]: 1111 1111 0000 0000
+		.LUT(~16'b 0110_1001_1001_0110)
+	) fadd (
+		.A(A),
+		.B(B),
+		.CI(CI),
+		.I0(I0),
+		.I3(CI),
+		.CO(CO),
+		.O(O)
+	);
+endmodule
+EOT
+
+equiv_opt -assert -map +/ice40/cells_map.v -map +/ice40/cells_sim.v ice40_opt
+design -load postopt
+select -assert-count 1 t:$lut
-- 
cgit v1.2.3


From cd5d6940e1c108b26ef4990accfb49fe7d8534c4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 18:44:57 -0700
Subject: Add SB_CARRY to ice40_opt test

---
 tests/ice40/ice40_opt.ys | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

(limited to 'tests')

diff --git a/tests/ice40/ice40_opt.ys b/tests/ice40/ice40_opt.ys
index 18e0d2b8a..b17c69c91 100644
--- a/tests/ice40/ice40_opt.ys
+++ b/tests/ice40/ice40_opt.ys
@@ -1,5 +1,5 @@
 read_verilog -icells -formal <<EOT
-module top(input CI, I0, output CO, O);
+module top(input CI, I0, output [1:0] CO, output O);
     wire A = 1'b0, B = 1'b0;
 	\$__ICE40_CARRY_WRAPPER #(
 		//    A[0]: 1010 1010 1010 1010
@@ -7,18 +7,20 @@ module top(input CI, I0, output CO, O);
 		//    A[2]: 1111 0000 1111 0000
 		//    A[3]: 1111 1111 0000 0000
 		.LUT(~16'b 0110_1001_1001_0110)
-	) fadd (
+	) u0 (
 		.A(A),
 		.B(B),
 		.CI(CI),
 		.I0(I0),
 		.I3(CI),
-		.CO(CO),
+		.CO(CO[0]),
 		.O(O)
 	);
+    SB_CARRY u1 (.I0(~A), .I1(~B), .CI(CI), .CO(CO[1]));
 endmodule
 EOT
 
 equiv_opt -assert -map +/ice40/cells_map.v -map +/ice40/cells_sim.v ice40_opt
 design -load postopt
+select -assert-count 1 t:*
 select -assert-count 1 t:$lut
-- 
cgit v1.2.3


From 4290548de35beba766bd7e0684e19de83a0cb2fa Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 30 Aug 2019 20:31:53 -0700
Subject: Make abc9 test a bit more interesting

---
 tests/various/abc9.v | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/various/abc9.v b/tests/various/abc9.v
index a08b613a8..30ebd4e26 100644
--- a/tests/various/abc9.v
+++ b/tests/various/abc9.v
@@ -5,5 +5,7 @@ always @*
 endmodule
 
 module abc9_test028(input i, output o);
-unknown u(~i, o);
+wire w;
+unknown u(~i, w);
+unknown2 u2(w, o);
 endmodule
-- 
cgit v1.2.3