From 3839bd50f28a16f1253a56d5871465763e72180c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 19 Jul 2019 12:43:02 -0700 Subject: Add test --- tests/various/wreduce.ys | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 tests/various/wreduce.ys (limited to 'tests') diff --git a/tests/various/wreduce.ys b/tests/various/wreduce.ys new file mode 100644 index 000000000..0b5403fa1 --- /dev/null +++ b/tests/various/wreduce.ys @@ -0,0 +1,22 @@ + +read_verilog < Date: Fri, 19 Jul 2019 12:50:11 -0700 Subject: Add tests for sub too --- tests/various/wreduce.ys | 49 +++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 48 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/various/wreduce.ys b/tests/various/wreduce.ys index 0b5403fa1..ee03e008d 100644 --- a/tests/various/wreduce.ys +++ b/tests/various/wreduce.ys @@ -5,7 +5,7 @@ module wreduce_add_test(input [3:0] i, input [7:0] j, output [7:0] o); endmodule EOT -hierarchy -top wreduce_add_test +hierarchy -auto-top proc design -save gold @@ -20,3 +20,50 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + + +### X - 0 +read_verilog < Date: Fri, 19 Jul 2019 12:53:18 -0700 Subject: Be more explicit --- tests/various/wreduce.ys | 35 +++++++++++++++++++++++++++++------ 1 file changed, 29 insertions(+), 6 deletions(-) (limited to 'tests') diff --git a/tests/various/wreduce.ys b/tests/various/wreduce.ys index ee03e008d..f9e5ed4e3 100644 --- a/tests/various/wreduce.ys +++ b/tests/various/wreduce.ys @@ -1,6 +1,6 @@ read_verilog < Date: Fri, 19 Jul 2019 13:11:30 -0700 Subject: Add one more test with trimming Y_WIDTH of $sub --- tests/various/wreduce.ys | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) (limited to 'tests') diff --git a/tests/various/wreduce.ys b/tests/various/wreduce.ys index f9e5ed4e3..8030c005e 100644 --- a/tests/various/wreduce.ys +++ b/tests/various/wreduce.ys @@ -9,7 +9,7 @@ hierarchy -auto-top proc design -save gold -prep +prep # calls wreduce select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i @@ -21,8 +21,8 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter +########## -### X - 0 read_verilog <> 4) - i; endmodule EOT @@ -79,9 +81,10 @@ hierarchy -auto-top proc design -save gold -prep +prep # calls wreduce -select -assert-count 1 t:$sub r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i +dump +select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i design -stash gate -- cgit v1.2.3 From c926eeb43a9c42a0ecc34871f383f4181b7a45f9 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 19 Jul 2019 14:02:46 -0700 Subject: Add another test --- tests/various/wreduce.ys | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/various/wreduce.ys b/tests/various/wreduce.ys index 8030c005e..deb99304d 100644 --- a/tests/various/wreduce.ys +++ b/tests/various/wreduce.ys @@ -83,7 +83,6 @@ design -save gold prep # calls wreduce -dump select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i design -stash gate @@ -93,3 +92,27 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + +########## + +read_verilog < Date: Fri, 26 Jul 2019 10:23:58 +0100 Subject: Add support for reading gzip'd input files Signed-off-by: David Shah --- tests/various/gzip_verilog.v.gz | Bin 0 -> 82 bytes tests/various/gzip_verilog.ys | 2 ++ 2 files changed, 2 insertions(+) create mode 100644 tests/various/gzip_verilog.v.gz create mode 100644 tests/various/gzip_verilog.ys (limited to 'tests') diff --git a/tests/various/gzip_verilog.v.gz b/tests/various/gzip_verilog.v.gz new file mode 100644 index 000000000..c52a95358 Binary files /dev/null and b/tests/various/gzip_verilog.v.gz differ diff --git a/tests/various/gzip_verilog.ys b/tests/various/gzip_verilog.ys new file mode 100644 index 000000000..870317e80 --- /dev/null +++ b/tests/various/gzip_verilog.ys @@ -0,0 +1,2 @@ +read_verilog gzip_verilog.v.gz +select -assert-any top -- cgit v1.2.3 From 07c4a7d4388cdacaa15512dd2f6f0f9e9fcb31f5 Mon Sep 17 00:00:00 2001 From: Bogdan Vukobratovic Date: Fri, 26 Jul 2019 11:36:48 +0200 Subject: Implement opt_share This pass identifies arithmetic operators that share an operand and whose results are used in mutually exclusive cases controlled by a multiplexer, and merges them together by multiplexing the other operands --- tests/opt/opt_share_cat.v | 15 +++++++++++++++ tests/opt/opt_share_cat.ys | 9 +++++++++ tests/opt/opt_share_mux_tree.v | 19 +++++++++++++++++++ tests/opt/opt_share_mux_tree.ys | 10 ++++++++++ 4 files changed, 53 insertions(+) create mode 100644 tests/opt/opt_share_cat.v create mode 100644 tests/opt/opt_share_cat.ys create mode 100644 tests/opt/opt_share_mux_tree.v create mode 100644 tests/opt/opt_share_mux_tree.ys (limited to 'tests') diff --git a/tests/opt/opt_share_cat.v b/tests/opt/opt_share_cat.v new file mode 100644 index 000000000..c32073360 --- /dev/null +++ b/tests/opt/opt_share_cat.v @@ -0,0 +1,15 @@ +module add_sub( + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [15:0] d, + input sel, + output [63:0] res, + ); + + reg [31: 0] cat1 = {a+b, c+d}; + reg [31: 0] cat2 = {a-b, c-d}; + + assign res = {b, sel ? cat1 : cat2, a}; + +endmodule diff --git a/tests/opt/opt_share_cat.ys b/tests/opt/opt_share_cat.ys new file mode 100644 index 000000000..c3f2f5a2f --- /dev/null +++ b/tests/opt/opt_share_cat.ys @@ -0,0 +1,9 @@ +read_verilog opt_share_cat.v +prep -flatten +opt +pmuxtree +opt_share +opt_clean + +select -assert-count 2 t:$sub +select -assert-count 0 t:$add diff --git a/tests/opt/opt_share_mux_tree.v b/tests/opt/opt_share_mux_tree.v new file mode 100644 index 000000000..807ed2978 --- /dev/null +++ b/tests/opt/opt_share_mux_tree.v @@ -0,0 +1,19 @@ +module add_sub( + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [1:0] sel, + output reg [15:0] res + ); + + + always @* begin + case(sel) + 0: res = a + b; + 1: res = a - b; + 2: res = a + c; + default: res = 16'bx; + endcase + end + +endmodule diff --git a/tests/opt/opt_share_mux_tree.ys b/tests/opt/opt_share_mux_tree.ys new file mode 100644 index 000000000..94d6aa7d2 --- /dev/null +++ b/tests/opt/opt_share_mux_tree.ys @@ -0,0 +1,10 @@ +read_verilog opt_share_mux_tree.v +prep -flatten +opt +pmuxtree +opt_share; +opt_share; +opt_clean + +select -assert-count 1 t:$add +select -assert-count 0 t:$sub -- cgit v1.2.3 From c075486c59155d16ed278922a3752366a95246ff Mon Sep 17 00:00:00 2001 From: Bogdan Vukobratovic Date: Sun, 28 Jul 2019 16:03:54 +0200 Subject: Reimplement opt_share to work on $alu and $pmux --- tests/opt/opt_share_add_sub.v | 10 ++++++++++ tests/opt/opt_share_add_sub.ys | 13 +++++++++++++ tests/opt/opt_share_cat.v | 2 +- tests/opt/opt_share_cat.ys | 18 +++++++++++------- tests/opt/opt_share_cat_multiuser.v | 22 ++++++++++++++++++++++ tests/opt/opt_share_cat_multiuser.ys | 13 +++++++++++++ tests/opt/opt_share_diff_port_widths.v | 21 +++++++++++++++++++++ tests/opt/opt_share_diff_port_widths.ys | 13 +++++++++++++ tests/opt/opt_share_extend.v | 19 +++++++++++++++++++ tests/opt/opt_share_extend.ys | 13 +++++++++++++ tests/opt/opt_share_large_pmux_cat.v | 22 ++++++++++++++++++++++ tests/opt/opt_share_large_pmux_cat.ys | 13 +++++++++++++ tests/opt/opt_share_large_pmux_cat_multipart.v | 25 +++++++++++++++++++++++++ tests/opt/opt_share_large_pmux_cat_multipart.ys | 15 +++++++++++++++ tests/opt/opt_share_large_pmux_multipart.v | 24 ++++++++++++++++++++++++ tests/opt/opt_share_large_pmux_multipart.ys | 13 +++++++++++++ tests/opt/opt_share_large_pmux_part.v | 22 ++++++++++++++++++++++ tests/opt/opt_share_large_pmux_part.ys | 13 +++++++++++++ tests/opt/opt_share_mux_tree.v | 2 +- tests/opt/opt_share_mux_tree.ys | 19 +++++++++++-------- 20 files changed, 295 insertions(+), 17 deletions(-) create mode 100644 tests/opt/opt_share_add_sub.v create mode 100644 tests/opt/opt_share_add_sub.ys create mode 100644 tests/opt/opt_share_cat_multiuser.v create mode 100644 tests/opt/opt_share_cat_multiuser.ys create mode 100644 tests/opt/opt_share_diff_port_widths.v create mode 100644 tests/opt/opt_share_diff_port_widths.ys create mode 100644 tests/opt/opt_share_extend.v create mode 100644 tests/opt/opt_share_extend.ys create mode 100644 tests/opt/opt_share_large_pmux_cat.v create mode 100644 tests/opt/opt_share_large_pmux_cat.ys create mode 100644 tests/opt/opt_share_large_pmux_cat_multipart.v create mode 100644 tests/opt/opt_share_large_pmux_cat_multipart.ys create mode 100644 tests/opt/opt_share_large_pmux_multipart.v create mode 100644 tests/opt/opt_share_large_pmux_multipart.ys create mode 100644 tests/opt/opt_share_large_pmux_part.v create mode 100644 tests/opt/opt_share_large_pmux_part.ys (limited to 'tests') diff --git a/tests/opt/opt_share_add_sub.v b/tests/opt/opt_share_add_sub.v new file mode 100644 index 000000000..30e093a39 --- /dev/null +++ b/tests/opt/opt_share_add_sub.v @@ -0,0 +1,10 @@ +module opt_share_test( + input [15:0] a, + input [15:0] b, + input sel, + output [15:0] res, + ); + + assign res = {sel ? a + b : a - b}; + +endmodule diff --git a/tests/opt/opt_share_add_sub.ys b/tests/opt/opt_share_add_sub.ys new file mode 100644 index 000000000..4a5406791 --- /dev/null +++ b/tests/opt/opt_share_add_sub.ys @@ -0,0 +1,13 @@ +read_verilog opt_share_add_sub.v +proc;; +copy opt_share_test merged + +alumacc merged +opt merged +opt_share merged +opt_clean merged + +miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter +sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter + +select -assert-count 1 -module merged t:$alu diff --git a/tests/opt/opt_share_cat.v b/tests/opt/opt_share_cat.v index c32073360..605dcfe59 100644 --- a/tests/opt/opt_share_cat.v +++ b/tests/opt/opt_share_cat.v @@ -1,4 +1,4 @@ -module add_sub( +module opt_share_test( input [15:0] a, input [15:0] b, input [15:0] c, diff --git a/tests/opt/opt_share_cat.ys b/tests/opt/opt_share_cat.ys index c3f2f5a2f..7de69bfde 100644 --- a/tests/opt/opt_share_cat.ys +++ b/tests/opt/opt_share_cat.ys @@ -1,9 +1,13 @@ read_verilog opt_share_cat.v -prep -flatten -opt -pmuxtree -opt_share -opt_clean +proc;; +copy opt_share_test merged -select -assert-count 2 t:$sub -select -assert-count 0 t:$add +alumacc merged +opt merged +opt_share merged +opt_clean merged + +miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter +sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter + +select -assert-count 2 -module merged t:$alu diff --git a/tests/opt/opt_share_cat_multiuser.v b/tests/opt/opt_share_cat_multiuser.v new file mode 100644 index 000000000..9ac0ceec8 --- /dev/null +++ b/tests/opt/opt_share_cat_multiuser.v @@ -0,0 +1,22 @@ +module opt_share_test( + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [15:0] d, + input sel, + output reg [47:0] res, + ); + + wire [15:0] add_res = a+b; + wire [15:0] sub_res = a-b; + wire [31: 0] cat1 = {add_res, c+d}; + wire [31: 0] cat2 = {sub_res, c-d}; + + always @* begin + case(sel) + 0: res = {cat1, add_res}; + 1: res = {cat2, add_res}; + endcase + end + +endmodule diff --git a/tests/opt/opt_share_cat_multiuser.ys b/tests/opt/opt_share_cat_multiuser.ys new file mode 100644 index 000000000..6a82fbd79 --- /dev/null +++ b/tests/opt/opt_share_cat_multiuser.ys @@ -0,0 +1,13 @@ +read_verilog opt_share_cat_multiuser.v +proc;; +copy opt_share_test merged + +alumacc merged +opt merged +opt_share merged +opt_clean merged + +miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter +sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter + +select -assert-count 3 -module merged t:$alu diff --git a/tests/opt/opt_share_diff_port_widths.v b/tests/opt/opt_share_diff_port_widths.v new file mode 100644 index 000000000..5e2971e30 --- /dev/null +++ b/tests/opt/opt_share_diff_port_widths.v @@ -0,0 +1,21 @@ +module opt_share_test( + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [1:0] sel, + output reg [15:0] res + ); + + wire [15:0] add0_res = a+b; + wire [15:0] add1_res = a+c; + + always @* begin + case(sel) + 0: res = add0_res[10:0]; + 1: res = add1_res[10:0]; + 2: res = a - b; + default: res = 32'bx; + endcase + end + +endmodule diff --git a/tests/opt/opt_share_diff_port_widths.ys b/tests/opt/opt_share_diff_port_widths.ys new file mode 100644 index 000000000..ec5e9f7b0 --- /dev/null +++ b/tests/opt/opt_share_diff_port_widths.ys @@ -0,0 +1,13 @@ +read_verilog opt_share_diff_port_widths.v +proc;; +copy opt_share_test merged + +alumacc merged +opt merged +opt_share merged +opt_clean merged + +miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter +sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter + +select -assert-count 2 -module merged t:$alu diff --git a/tests/opt/opt_share_extend.v b/tests/opt/opt_share_extend.v new file mode 100644 index 000000000..5ed6bde6f --- /dev/null +++ b/tests/opt/opt_share_extend.v @@ -0,0 +1,19 @@ +module opt_share_test( + input signed [7:0] a, + input signed [10:0] b, + input signed [15:0] c, + input [1:0] sel, + output reg signed [15:0] res + ); + + + always @* begin + case(sel) + 0: res = a + b; + 1: res = a - b; + 2: res = a + c; + default: res = 16'bx; + endcase + end + +endmodule diff --git a/tests/opt/opt_share_extend.ys b/tests/opt/opt_share_extend.ys new file mode 100644 index 000000000..c553ee0fb --- /dev/null +++ b/tests/opt/opt_share_extend.ys @@ -0,0 +1,13 @@ +read_verilog opt_share_extend.v +proc;; +copy opt_share_test merged + +alumacc merged +opt merged +opt_share merged +opt_clean merged + +miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter +sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter + +select -assert-count 1 -module merged t:$alu diff --git a/tests/opt/opt_share_large_pmux_cat.v b/tests/opt/opt_share_large_pmux_cat.v new file mode 100644 index 000000000..6208c796b --- /dev/null +++ b/tests/opt/opt_share_large_pmux_cat.v @@ -0,0 +1,22 @@ +module opt_share_test( + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [2:0] sel, + output reg [31:0] res + ); + + + always @* begin + case(sel) + 0: res = {a + b, a}; + 1: res = {a - b, b}; + 2: res = {a + c, c}; + 3: res = {a - c, a}; + 4: res = {b, b}; + 5: res = {c, c}; + default: res = 32'bx; + endcase + end + +endmodule diff --git a/tests/opt/opt_share_large_pmux_cat.ys b/tests/opt/opt_share_large_pmux_cat.ys new file mode 100644 index 000000000..4186ca52e --- /dev/null +++ b/tests/opt/opt_share_large_pmux_cat.ys @@ -0,0 +1,13 @@ +read_verilog opt_share_large_pmux_cat.v +proc;; +copy opt_share_test merged + +alumacc merged +opt merged +opt_share merged +opt_clean merged + +miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter +sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter + +select -assert-count 1 -module merged t:$alu diff --git a/tests/opt/opt_share_large_pmux_cat_multipart.v b/tests/opt/opt_share_large_pmux_cat_multipart.v new file mode 100644 index 000000000..f97971bf6 --- /dev/null +++ b/tests/opt/opt_share_large_pmux_cat_multipart.v @@ -0,0 +1,25 @@ +module opt_share_test( + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [15:0] d, + input [2:0] sel, + output reg [31:0] res + ); + + wire [15:0] add0_res = a+d; + + always @* begin + case(sel) + 0: res = {add0_res, a}; + 1: res = {a - b, add0_res[7], 15'b0}; + 2: res = {b-a, b}; + 3: res = {d, b - c}; + 4: res = {d, b - a}; + 5: res = {c, d}; + 6: res = {a - c, b-d}; + default: res = 32'bx; + endcase + end + +endmodule diff --git a/tests/opt/opt_share_large_pmux_cat_multipart.ys b/tests/opt/opt_share_large_pmux_cat_multipart.ys new file mode 100644 index 000000000..54d200dc7 --- /dev/null +++ b/tests/opt/opt_share_large_pmux_cat_multipart.ys @@ -0,0 +1,15 @@ +read_verilog opt_share_large_pmux_cat_multipart.v +proc;; +copy opt_share_test merged + +alumacc merged +opt merged + +opt_share merged +opt_clean merged +opt -full + +miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter +sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter + +select -assert-count 4 -module merged t:$alu diff --git a/tests/opt/opt_share_large_pmux_multipart.v b/tests/opt/opt_share_large_pmux_multipart.v new file mode 100644 index 000000000..e7ba318ef --- /dev/null +++ b/tests/opt/opt_share_large_pmux_multipart.v @@ -0,0 +1,24 @@ +module opt_share_test( + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [15:0] d, + input [2:0] sel, + output reg [15:0] res + ); + + + always @* begin + case(sel) + 0: res = a + d; + 1: res = a - b; + 2: res = b; + 3: res = b - c; + 4: res = b - a; + 5: res = c; + 6: res = a - c; + default: res = 16'bx; + endcase + end + +endmodule diff --git a/tests/opt/opt_share_large_pmux_multipart.ys b/tests/opt/opt_share_large_pmux_multipart.ys new file mode 100644 index 000000000..11182df1a --- /dev/null +++ b/tests/opt/opt_share_large_pmux_multipart.ys @@ -0,0 +1,13 @@ +read_verilog opt_share_large_pmux_multipart.v +proc;; +copy opt_share_test merged + +alumacc merged +opt merged +opt_share merged +opt_clean merged + +miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter +sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter + +select -assert-count 2 -module merged t:$alu diff --git a/tests/opt/opt_share_large_pmux_part.v b/tests/opt/opt_share_large_pmux_part.v new file mode 100644 index 000000000..138be0cd6 --- /dev/null +++ b/tests/opt/opt_share_large_pmux_part.v @@ -0,0 +1,22 @@ +module opt_share_test( + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [2:0] sel, + output reg [15:0] res + ); + + + always @* begin + case(sel) + 0: res = a + b; + 1: res = a - b; + 2: res = a + c; + 3: res = a - c; + 4: res = b; + 5: res = c; + default: res = 16'bx; + endcase + end + +endmodule diff --git a/tests/opt/opt_share_large_pmux_part.ys b/tests/opt/opt_share_large_pmux_part.ys new file mode 100644 index 000000000..6b594a3d6 --- /dev/null +++ b/tests/opt/opt_share_large_pmux_part.ys @@ -0,0 +1,13 @@ +read_verilog opt_share_large_pmux_part.v +proc;; +copy opt_share_test merged + +alumacc merged +opt merged +opt_share merged +opt_clean merged + +miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter +sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter + +select -assert-count 1 -module merged t:$alu diff --git a/tests/opt/opt_share_mux_tree.v b/tests/opt/opt_share_mux_tree.v index 807ed2978..c90826204 100644 --- a/tests/opt/opt_share_mux_tree.v +++ b/tests/opt/opt_share_mux_tree.v @@ -1,4 +1,4 @@ -module add_sub( +module opt_share_test( input [15:0] a, input [15:0] b, input [15:0] c, diff --git a/tests/opt/opt_share_mux_tree.ys b/tests/opt/opt_share_mux_tree.ys index 94d6aa7d2..58473039f 100644 --- a/tests/opt/opt_share_mux_tree.ys +++ b/tests/opt/opt_share_mux_tree.ys @@ -1,10 +1,13 @@ read_verilog opt_share_mux_tree.v -prep -flatten -opt -pmuxtree -opt_share; -opt_share; -opt_clean +proc;; +copy opt_share_test merged -select -assert-count 1 t:$add -select -assert-count 0 t:$sub +alumacc merged +opt merged +opt_share merged +opt_clean merged + +miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter +sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter + +select -assert-count 1 -module merged t:$alu -- cgit v1.2.3 From 3b8c917025e1be9695468588082e9175e918c9e9 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Wed, 31 Jul 2019 09:27:38 -0700 Subject: Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences. Use FIRRTL spec vlaues for definition of FIRRTL widths. Added support for '$pos`, `$pow` and `$xnor` cells. Enable tests/simple/operators.v since all operators tested there are now supported. Disable FIRRTL tests of tests/simple/{defvalue.sv,implicit_ports.v,wandwor.v} since they currently generate FIRRTL compilation errors. --- tests/simple/xfirrtl | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/simple/xfirrtl b/tests/simple/xfirrtl index ba61a4476..10063d2c2 100644 --- a/tests/simple/xfirrtl +++ b/tests/simple/xfirrtl @@ -1,10 +1,12 @@ # This file contains the names of verilog files to exclude from verilog to FIRRTL regression tests due to known failures. arraycells.v inst id[0] of +defvalue.sv Initial value not supported dff_different_styles.v dff_init.v Initial value not supported generate.v combinational loop hierdefparam.v inst id[0] of i2c_master_tests.v $adff +implicit_ports.v not fully initialized macros.v drops modules mem2reg.v drops modules mem_arst.v $adff @@ -12,7 +14,6 @@ memory.v $adff multiplier.v inst id[0] of muxtree.v drops modules omsp_dbg_uart.v $adff -operators.v $pow partsel.v drops modules process.v drops modules realexpr.v drops modules @@ -23,5 +24,6 @@ specify.v no code (empty module generates error subbytes.v $adff task_func.v drops modules values.v combinational loop +wandwor.v Invalid connect to an expression that is not a reference or a WritePort. vloghammer.v combinational loop wreduce.v original verilog issues ( -x where x isn't declared signed) -- cgit v1.2.3 From 280c4e7794543e99244aafffc62a2dd4454bcb06 Mon Sep 17 00:00:00 2001 From: Bogdan Vukobratovic Date: Sat, 3 Aug 2019 12:28:46 +0200 Subject: Fix spacing in opt_share tests, change wording in opt_share help --- tests/opt/opt_share_add_sub.v | 12 ++++---- tests/opt/opt_share_cat.v | 20 ++++++------- tests/opt/opt_share_cat_multiuser.v | 34 +++++++++++----------- tests/opt/opt_share_diff_port_widths.v | 32 ++++++++++----------- tests/opt/opt_share_extend.v | 29 +++++++++---------- tests/opt/opt_share_large_pmux_cat.v | 35 +++++++++++----------- tests/opt/opt_share_large_pmux_cat_multipart.v | 40 +++++++++++++------------- tests/opt/opt_share_large_pmux_multipart.v | 39 ++++++++++++------------- tests/opt/opt_share_large_pmux_part.v | 35 +++++++++++----------- tests/opt/opt_share_mux_tree.v | 29 +++++++++---------- 10 files changed, 150 insertions(+), 155 deletions(-) (limited to 'tests') diff --git a/tests/opt/opt_share_add_sub.v b/tests/opt/opt_share_add_sub.v index 30e093a39..1c2665cf0 100644 --- a/tests/opt/opt_share_add_sub.v +++ b/tests/opt/opt_share_add_sub.v @@ -1,10 +1,10 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input sel, - output [15:0] res, - ); + input [15:0] a, + input [15:0] b, + input sel, + output [15:0] res, + ); - assign res = {sel ? a + b : a - b}; + assign res = {sel ? a + b : a - b}; endmodule diff --git a/tests/opt/opt_share_cat.v b/tests/opt/opt_share_cat.v index 605dcfe59..7b6f626b9 100644 --- a/tests/opt/opt_share_cat.v +++ b/tests/opt/opt_share_cat.v @@ -1,15 +1,15 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input [15:0] c, - input [15:0] d, - input sel, - output [63:0] res, - ); + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [15:0] d, + input sel, + output [63:0] res, + ); - reg [31: 0] cat1 = {a+b, c+d}; - reg [31: 0] cat2 = {a-b, c-d}; + reg [31: 0] cat1 = {a+b, c+d}; + reg [31: 0] cat2 = {a-b, c-d}; - assign res = {b, sel ? cat1 : cat2, a}; + assign res = {b, sel ? cat1 : cat2, a}; endmodule diff --git a/tests/opt/opt_share_cat_multiuser.v b/tests/opt/opt_share_cat_multiuser.v index 9ac0ceec8..f77f912e9 100644 --- a/tests/opt/opt_share_cat_multiuser.v +++ b/tests/opt/opt_share_cat_multiuser.v @@ -1,22 +1,22 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input [15:0] c, - input [15:0] d, - input sel, - output reg [47:0] res, - ); + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [15:0] d, + input sel, + output reg [47:0] res, + ); - wire [15:0] add_res = a+b; - wire [15:0] sub_res = a-b; - wire [31: 0] cat1 = {add_res, c+d}; - wire [31: 0] cat2 = {sub_res, c-d}; + wire [15:0] add_res = a+b; + wire [15:0] sub_res = a-b; + wire [31: 0] cat1 = {add_res, c+d}; + wire [31: 0] cat2 = {sub_res, c-d}; - always @* begin - case(sel) - 0: res = {cat1, add_res}; - 1: res = {cat2, add_res}; - endcase - end + always @* begin + case(sel) + 0: res = {cat1, add_res}; + 1: res = {cat2, add_res}; + endcase + end endmodule diff --git a/tests/opt/opt_share_diff_port_widths.v b/tests/opt/opt_share_diff_port_widths.v index 5e2971e30..e57ab7a83 100644 --- a/tests/opt/opt_share_diff_port_widths.v +++ b/tests/opt/opt_share_diff_port_widths.v @@ -1,21 +1,21 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input [15:0] c, - input [1:0] sel, - output reg [15:0] res - ); + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [1:0] sel, + output reg [15:0] res + ); - wire [15:0] add0_res = a+b; - wire [15:0] add1_res = a+c; + wire [15:0] add0_res = a+b; + wire [15:0] add1_res = a+c; - always @* begin - case(sel) - 0: res = add0_res[10:0]; - 1: res = add1_res[10:0]; - 2: res = a - b; - default: res = 32'bx; - endcase - end + always @* begin + case(sel) + 0: res = add0_res[10:0]; + 1: res = add1_res[10:0]; + 2: res = a - b; + default: res = 32'bx; + endcase + end endmodule diff --git a/tests/opt/opt_share_extend.v b/tests/opt/opt_share_extend.v index 5ed6bde6f..60ce1a2f3 100644 --- a/tests/opt/opt_share_extend.v +++ b/tests/opt/opt_share_extend.v @@ -1,19 +1,18 @@ module opt_share_test( - input signed [7:0] a, - input signed [10:0] b, - input signed [15:0] c, - input [1:0] sel, - output reg signed [15:0] res - ); + input signed [7:0] a, + input signed [10:0] b, + input signed [15:0] c, + input [1:0] sel, + output reg signed [15:0] res + ); - - always @* begin - case(sel) - 0: res = a + b; - 1: res = a - b; - 2: res = a + c; - default: res = 16'bx; - endcase - end + always @* begin + case(sel) + 0: res = a + b; + 1: res = a - b; + 2: res = a + c; + default: res = 16'bx; + endcase + end endmodule diff --git a/tests/opt/opt_share_large_pmux_cat.v b/tests/opt/opt_share_large_pmux_cat.v index 6208c796b..0667e6080 100644 --- a/tests/opt/opt_share_large_pmux_cat.v +++ b/tests/opt/opt_share_large_pmux_cat.v @@ -1,22 +1,21 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input [15:0] c, - input [2:0] sel, - output reg [31:0] res - ); + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [2:0] sel, + output reg [31:0] res + ); - - always @* begin - case(sel) - 0: res = {a + b, a}; - 1: res = {a - b, b}; - 2: res = {a + c, c}; - 3: res = {a - c, a}; - 4: res = {b, b}; - 5: res = {c, c}; - default: res = 32'bx; - endcase - end + always @* begin + case(sel) + 0: res = {a + b, a}; + 1: res = {a - b, b}; + 2: res = {a + c, c}; + 3: res = {a - c, a}; + 4: res = {b, b}; + 5: res = {c, c}; + default: res = 32'bx; + endcase + end endmodule diff --git a/tests/opt/opt_share_large_pmux_cat_multipart.v b/tests/opt/opt_share_large_pmux_cat_multipart.v index f97971bf6..f26505d3a 100644 --- a/tests/opt/opt_share_large_pmux_cat_multipart.v +++ b/tests/opt/opt_share_large_pmux_cat_multipart.v @@ -1,25 +1,25 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input [15:0] c, - input [15:0] d, - input [2:0] sel, - output reg [31:0] res - ); + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [15:0] d, + input [2:0] sel, + output reg [31:0] res + ); - wire [15:0] add0_res = a+d; + wire [15:0] add0_res = a+d; - always @* begin - case(sel) - 0: res = {add0_res, a}; - 1: res = {a - b, add0_res[7], 15'b0}; - 2: res = {b-a, b}; - 3: res = {d, b - c}; - 4: res = {d, b - a}; - 5: res = {c, d}; - 6: res = {a - c, b-d}; - default: res = 32'bx; - endcase - end + always @* begin + case(sel) + 0: res = {add0_res, a}; + 1: res = {a - b, add0_res[7], 15'b0}; + 2: res = {b-a, b}; + 3: res = {d, b - c}; + 4: res = {d, b - a}; + 5: res = {c, d}; + 6: res = {a - c, b-d}; + default: res = 32'bx; + endcase + end endmodule diff --git a/tests/opt/opt_share_large_pmux_multipart.v b/tests/opt/opt_share_large_pmux_multipart.v index e7ba318ef..1c460292f 100644 --- a/tests/opt/opt_share_large_pmux_multipart.v +++ b/tests/opt/opt_share_large_pmux_multipart.v @@ -1,24 +1,23 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input [15:0] c, - input [15:0] d, - input [2:0] sel, - output reg [15:0] res - ); + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [15:0] d, + input [2:0] sel, + output reg [15:0] res + ); - - always @* begin - case(sel) - 0: res = a + d; - 1: res = a - b; - 2: res = b; - 3: res = b - c; - 4: res = b - a; - 5: res = c; - 6: res = a - c; - default: res = 16'bx; - endcase - end + always @* begin + case(sel) + 0: res = a + d; + 1: res = a - b; + 2: res = b; + 3: res = b - c; + 4: res = b - a; + 5: res = c; + 6: res = a - c; + default: res = 16'bx; + endcase + end endmodule diff --git a/tests/opt/opt_share_large_pmux_part.v b/tests/opt/opt_share_large_pmux_part.v index 138be0cd6..f9dd17446 100644 --- a/tests/opt/opt_share_large_pmux_part.v +++ b/tests/opt/opt_share_large_pmux_part.v @@ -1,22 +1,21 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input [15:0] c, - input [2:0] sel, - output reg [15:0] res - ); + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [2:0] sel, + output reg [15:0] res + ); - - always @* begin - case(sel) - 0: res = a + b; - 1: res = a - b; - 2: res = a + c; - 3: res = a - c; - 4: res = b; - 5: res = c; - default: res = 16'bx; - endcase - end + always @* begin + case(sel) + 0: res = a + b; + 1: res = a - b; + 2: res = a + c; + 3: res = a - c; + 4: res = b; + 5: res = c; + default: res = 16'bx; + endcase + end endmodule diff --git a/tests/opt/opt_share_mux_tree.v b/tests/opt/opt_share_mux_tree.v index c90826204..4a26afb46 100644 --- a/tests/opt/opt_share_mux_tree.v +++ b/tests/opt/opt_share_mux_tree.v @@ -1,19 +1,18 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input [15:0] c, - input [1:0] sel, - output reg [15:0] res - ); + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [1:0] sel, + output reg [15:0] res + ); - - always @* begin - case(sel) - 0: res = a + b; - 1: res = a - b; - 2: res = a + c; - default: res = 16'bx; - endcase - end + always @* begin + case(sel) + 0: res = a + b; + 1: res = a - b; + 2: res = a + c; + default: res = 16'bx; + endcase + end endmodule -- cgit v1.2.3 From d8be5ce6ba11ec78d0f7925d488fad09a3eaba2c Mon Sep 17 00:00:00 2001 From: Bogdan Vukobratovic Date: Sat, 3 Aug 2019 12:35:46 +0200 Subject: Tabs to spaces in opt_share examples --- tests/opt/opt_share_add_sub.v | 12 ++++---- tests/opt/opt_share_cat.v | 20 ++++++------- tests/opt/opt_share_cat_multiuser.v | 34 +++++++++++----------- tests/opt/opt_share_diff_port_widths.v | 32 ++++++++++----------- tests/opt/opt_share_extend.v | 28 +++++++++--------- tests/opt/opt_share_large_pmux_cat.v | 34 +++++++++++----------- tests/opt/opt_share_large_pmux_cat_multipart.v | 40 +++++++++++++------------- tests/opt/opt_share_large_pmux_multipart.v | 38 ++++++++++++------------ tests/opt/opt_share_large_pmux_part.v | 34 +++++++++++----------- tests/opt/opt_share_mux_tree.v | 28 +++++++++--------- 10 files changed, 150 insertions(+), 150 deletions(-) (limited to 'tests') diff --git a/tests/opt/opt_share_add_sub.v b/tests/opt/opt_share_add_sub.v index 1c2665cf0..d918f27cc 100644 --- a/tests/opt/opt_share_add_sub.v +++ b/tests/opt/opt_share_add_sub.v @@ -1,10 +1,10 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input sel, - output [15:0] res, - ); + input [15:0] a, + input [15:0] b, + input sel, + output [15:0] res, + ); - assign res = {sel ? a + b : a - b}; + assign res = {sel ? a + b : a - b}; endmodule diff --git a/tests/opt/opt_share_cat.v b/tests/opt/opt_share_cat.v index 7b6f626b9..7fb97fef5 100644 --- a/tests/opt/opt_share_cat.v +++ b/tests/opt/opt_share_cat.v @@ -1,15 +1,15 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input [15:0] c, - input [15:0] d, - input sel, - output [63:0] res, - ); + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [15:0] d, + input sel, + output [63:0] res, + ); - reg [31: 0] cat1 = {a+b, c+d}; - reg [31: 0] cat2 = {a-b, c-d}; + reg [31: 0] cat1 = {a+b, c+d}; + reg [31: 0] cat2 = {a-b, c-d}; - assign res = {b, sel ? cat1 : cat2, a}; + assign res = {b, sel ? cat1 : cat2, a}; endmodule diff --git a/tests/opt/opt_share_cat_multiuser.v b/tests/opt/opt_share_cat_multiuser.v index f77f912e9..b250689d9 100644 --- a/tests/opt/opt_share_cat_multiuser.v +++ b/tests/opt/opt_share_cat_multiuser.v @@ -1,22 +1,22 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input [15:0] c, - input [15:0] d, - input sel, - output reg [47:0] res, - ); + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [15:0] d, + input sel, + output reg [47:0] res, + ); - wire [15:0] add_res = a+b; - wire [15:0] sub_res = a-b; - wire [31: 0] cat1 = {add_res, c+d}; - wire [31: 0] cat2 = {sub_res, c-d}; + wire [15:0] add_res = a+b; + wire [15:0] sub_res = a-b; + wire [31: 0] cat1 = {add_res, c+d}; + wire [31: 0] cat2 = {sub_res, c-d}; - always @* begin - case(sel) - 0: res = {cat1, add_res}; - 1: res = {cat2, add_res}; - endcase - end + always @* begin + case(sel) + 0: res = {cat1, add_res}; + 1: res = {cat2, add_res}; + endcase + end endmodule diff --git a/tests/opt/opt_share_diff_port_widths.v b/tests/opt/opt_share_diff_port_widths.v index e57ab7a83..1a37c80a6 100644 --- a/tests/opt/opt_share_diff_port_widths.v +++ b/tests/opt/opt_share_diff_port_widths.v @@ -1,21 +1,21 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input [15:0] c, - input [1:0] sel, - output reg [15:0] res - ); + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [1:0] sel, + output reg [15:0] res + ); - wire [15:0] add0_res = a+b; - wire [15:0] add1_res = a+c; + wire [15:0] add0_res = a+b; + wire [15:0] add1_res = a+c; - always @* begin - case(sel) - 0: res = add0_res[10:0]; - 1: res = add1_res[10:0]; - 2: res = a - b; - default: res = 32'bx; - endcase - end + always @* begin + case(sel) + 0: res = add0_res[10:0]; + 1: res = add1_res[10:0]; + 2: res = a - b; + default: res = 32'bx; + endcase + end endmodule diff --git a/tests/opt/opt_share_extend.v b/tests/opt/opt_share_extend.v index 60ce1a2f3..d39f19069 100644 --- a/tests/opt/opt_share_extend.v +++ b/tests/opt/opt_share_extend.v @@ -1,18 +1,18 @@ module opt_share_test( - input signed [7:0] a, - input signed [10:0] b, - input signed [15:0] c, - input [1:0] sel, - output reg signed [15:0] res - ); + input signed [7:0] a, + input signed [10:0] b, + input signed [15:0] c, + input [1:0] sel, + output reg signed [15:0] res + ); - always @* begin - case(sel) - 0: res = a + b; - 1: res = a - b; - 2: res = a + c; - default: res = 16'bx; - endcase - end + always @* begin + case(sel) + 0: res = a + b; + 1: res = a - b; + 2: res = a + c; + default: res = 16'bx; + endcase + end endmodule diff --git a/tests/opt/opt_share_large_pmux_cat.v b/tests/opt/opt_share_large_pmux_cat.v index 0667e6080..416ba3766 100644 --- a/tests/opt/opt_share_large_pmux_cat.v +++ b/tests/opt/opt_share_large_pmux_cat.v @@ -1,21 +1,21 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input [15:0] c, - input [2:0] sel, - output reg [31:0] res - ); + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [2:0] sel, + output reg [31:0] res + ); - always @* begin - case(sel) - 0: res = {a + b, a}; - 1: res = {a - b, b}; - 2: res = {a + c, c}; - 3: res = {a - c, a}; - 4: res = {b, b}; - 5: res = {c, c}; - default: res = 32'bx; - endcase - end + always @* begin + case(sel) + 0: res = {a + b, a}; + 1: res = {a - b, b}; + 2: res = {a + c, c}; + 3: res = {a - c, a}; + 4: res = {b, b}; + 5: res = {c, c}; + default: res = 32'bx; + endcase + end endmodule diff --git a/tests/opt/opt_share_large_pmux_cat_multipart.v b/tests/opt/opt_share_large_pmux_cat_multipart.v index f26505d3a..34d2bd9a8 100644 --- a/tests/opt/opt_share_large_pmux_cat_multipart.v +++ b/tests/opt/opt_share_large_pmux_cat_multipart.v @@ -1,25 +1,25 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input [15:0] c, - input [15:0] d, - input [2:0] sel, - output reg [31:0] res - ); + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [15:0] d, + input [2:0] sel, + output reg [31:0] res + ); - wire [15:0] add0_res = a+d; + wire [15:0] add0_res = a+d; - always @* begin - case(sel) - 0: res = {add0_res, a}; - 1: res = {a - b, add0_res[7], 15'b0}; - 2: res = {b-a, b}; - 3: res = {d, b - c}; - 4: res = {d, b - a}; - 5: res = {c, d}; - 6: res = {a - c, b-d}; - default: res = 32'bx; - endcase - end + always @* begin + case(sel) + 0: res = {add0_res, a}; + 1: res = {a - b, add0_res[7], 15'b0}; + 2: res = {b-a, b}; + 3: res = {d, b - c}; + 4: res = {d, b - a}; + 5: res = {c, d}; + 6: res = {a - c, b-d}; + default: res = 32'bx; + endcase + end endmodule diff --git a/tests/opt/opt_share_large_pmux_multipart.v b/tests/opt/opt_share_large_pmux_multipart.v index 1c460292f..535adf96f 100644 --- a/tests/opt/opt_share_large_pmux_multipart.v +++ b/tests/opt/opt_share_large_pmux_multipart.v @@ -1,23 +1,23 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input [15:0] c, - input [15:0] d, - input [2:0] sel, - output reg [15:0] res - ); + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [15:0] d, + input [2:0] sel, + output reg [15:0] res + ); - always @* begin - case(sel) - 0: res = a + d; - 1: res = a - b; - 2: res = b; - 3: res = b - c; - 4: res = b - a; - 5: res = c; - 6: res = a - c; - default: res = 16'bx; - endcase - end + always @* begin + case(sel) + 0: res = a + d; + 1: res = a - b; + 2: res = b; + 3: res = b - c; + 4: res = b - a; + 5: res = c; + 6: res = a - c; + default: res = 16'bx; + endcase + end endmodule diff --git a/tests/opt/opt_share_large_pmux_part.v b/tests/opt/opt_share_large_pmux_part.v index f9dd17446..a9008fb5a 100644 --- a/tests/opt/opt_share_large_pmux_part.v +++ b/tests/opt/opt_share_large_pmux_part.v @@ -1,21 +1,21 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input [15:0] c, - input [2:0] sel, - output reg [15:0] res - ); + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [2:0] sel, + output reg [15:0] res + ); - always @* begin - case(sel) - 0: res = a + b; - 1: res = a - b; - 2: res = a + c; - 3: res = a - c; - 4: res = b; - 5: res = c; - default: res = 16'bx; - endcase - end + always @* begin + case(sel) + 0: res = a + b; + 1: res = a - b; + 2: res = a + c; + 3: res = a - c; + 4: res = b; + 5: res = c; + default: res = 16'bx; + endcase + end endmodule diff --git a/tests/opt/opt_share_mux_tree.v b/tests/opt/opt_share_mux_tree.v index 4a26afb46..cc5ae4eb9 100644 --- a/tests/opt/opt_share_mux_tree.v +++ b/tests/opt/opt_share_mux_tree.v @@ -1,18 +1,18 @@ module opt_share_test( - input [15:0] a, - input [15:0] b, - input [15:0] c, - input [1:0] sel, - output reg [15:0] res - ); + input [15:0] a, + input [15:0] b, + input [15:0] c, + input [1:0] sel, + output reg [15:0] res + ); - always @* begin - case(sel) - 0: res = a + b; - 1: res = a - b; - 2: res = a + c; - default: res = 16'bx; - endcase - end + always @* begin + case(sel) + 0: res = a + b; + 1: res = a - b; + 2: res = a + c; + default: res = 16'bx; + endcase + end endmodule -- cgit v1.2.3 From 6a796accc09bc2c8ef98c068185de13d3e01890a Mon Sep 17 00:00:00 2001 From: Bogdan Vukobratovic Date: Sun, 4 Aug 2019 19:06:38 +0200 Subject: Support various binary operators in opt_share --- tests/opt_share/.gitignore | 1 + tests/opt_share/generate.py | 86 +++++++++++++++++++++++++++++++++++++++++++++ tests/opt_share/run-test.sh | 39 ++++++++++++++++++++ 3 files changed, 126 insertions(+) create mode 100644 tests/opt_share/.gitignore create mode 100644 tests/opt_share/generate.py create mode 100755 tests/opt_share/run-test.sh (limited to 'tests') diff --git a/tests/opt_share/.gitignore b/tests/opt_share/.gitignore new file mode 100644 index 000000000..9c595a6fb --- /dev/null +++ b/tests/opt_share/.gitignore @@ -0,0 +1 @@ +temp diff --git a/tests/opt_share/generate.py b/tests/opt_share/generate.py new file mode 100644 index 000000000..2ec92f7de --- /dev/null +++ b/tests/opt_share/generate.py @@ -0,0 +1,86 @@ +#!/usr/bin/env python3 + +import argparse +import sys +import random +from contextlib import contextmanager + + +@contextmanager +def redirect_stdout(new_target): + old_target, sys.stdout = sys.stdout, new_target + try: + yield new_target + finally: + sys.stdout = old_target + + +def random_plus_x(): + return "%s x" % random.choice(['+', '+', '+', '-', '-', '|', '&', '^']) + + +def maybe_plus_x(expr): + if random.randint(0, 4) == 0: + return "(%s %s)" % (expr, random_plus_x()) + else: + return expr + + +parser = argparse.ArgumentParser( + formatter_class=argparse.ArgumentDefaultsHelpFormatter) +parser.add_argument('-S', '--seed', type=int, help='seed for PRNG') +parser.add_argument('-c', + '--count', + type=int, + default=100, + help='number of test cases to generate') +args = parser.parse_args() + +if args.seed is not None: + print("PRNG seed: %d" % args.seed) + random.seed(args.seed) + +for idx in range(args.count): + with open('temp/uut_%05d.v' % idx, 'w') as f: + with redirect_stdout(f): + print('module uut_%05d(a, b, c, s, y);' % (idx)) + op = random.choice([ + random.choice(['+', '-', '*', '/', '%']), + random.choice(['<', '<=', '==', '!=', '===', '!==', '>=', + '>']), + random.choice(['<<', '>>', '<<<', '>>>']), + random.choice(['|', '&', '^', '~^', '||', '&&']), + ]) + print(' input%s [%d:0] a;' % (random.choice(['', ' signed']), 8)) + print(' input%s [%d:0] b;' % (random.choice(['', ' signed']), 8)) + print(' input%s [%d:0] c;' % (random.choice(['', ' signed']), 8)) + print(' input s;') + print(' output [%d:0] y;' % 8) + ops1 = ['a', 'b'] + ops2 = ['a', 'c'] + random.shuffle(ops1) + random.shuffle(ops2) + cast1 = random.choice(['', '$signed', '$unsigned']) + cast2 = random.choice(['', '$signed', '$unsigned']) + print(' assign y = (s ? %s(%s %s %s) : %s(%s %s %s));' % + (cast1, ops1[0], op, ops1[1], + cast2, ops2[0], op, ops2[1])) + print('endmodule') + + with open('temp/uut_%05d.ys' % idx, 'w') as f: + with redirect_stdout(f): + print('read_verilog temp/uut_%05d.v' % idx) + print('proc;;') + print('copy uut_%05d gold' % idx) + print('rename uut_%05d gate' % idx) + print('tee -a temp/all_share_log.txt log') + print('tee -a temp/all_share_log.txt log #job# uut_%05d' % idx) + print('tee -a temp/all_share_log.txt opt gate') + print('tee -a temp/all_share_log.txt opt_share gate') + print('tee -a temp/all_share_log.txt opt_clean gate') + print( + 'miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter' + ) + print( + 'sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter' + ) diff --git a/tests/opt_share/run-test.sh b/tests/opt_share/run-test.sh new file mode 100755 index 000000000..e01552646 --- /dev/null +++ b/tests/opt_share/run-test.sh @@ -0,0 +1,39 @@ +#!/bin/bash + +# run this test many times: +# time bash -c 'for ((i=0; i<100; i++)); do echo "-- $i --"; bash run-test.sh || exit 1; done' + +set -e + +OPTIND=1 +count=100 +seed="" # default to no seed specified +while getopts "c:S:" opt +do + case "$opt" in + c) count="$OPTARG" ;; + S) seed="-S $OPTARG" ;; + esac +done +shift "$((OPTIND-1))" + +rm -rf temp +mkdir -p temp +echo "generating tests.." +python3 generate.py -c $count $seed + +echo "running tests.." +for i in $( ls temp/*.ys | sed 's,[^0-9],,g; s,^0*\(.\),\1,g;' ); do + echo -n "[$i]" + idx=$( printf "%05d" $i ) + ../../yosys -ql temp/uut_${idx}.log temp/uut_${idx}.ys +done +echo + +failed_share=$( echo $( gawk '/^#job#/ { j=$2; db[j]=0; } /^Removing [246] cells/ { delete db[j]; } END { for (j in db) print(j); }' temp/all_share_log.txt ) ) +if [ -n "$failed_share" ]; then + echo "Resource sharing failed for the following test cases: $failed_share" + false +fi + +exit 0 -- cgit v1.2.3 From 3a3da678ad0902ad0b16fe48cbb10053cd7dcb28 Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 31 Jul 2019 13:58:27 +0100 Subject: Add test for writing gzip-compressed files Signed-off-by: David Shah --- tests/various/.gitignore | 2 ++ tests/various/write_gzip.ys | 16 ++++++++++++++++ 2 files changed, 18 insertions(+) create mode 100644 tests/various/write_gzip.ys (limited to 'tests') diff --git a/tests/various/.gitignore b/tests/various/.gitignore index 7b3e8c68e..31078b298 100644 --- a/tests/various/.gitignore +++ b/tests/various/.gitignore @@ -1,2 +1,4 @@ /*.log /*.out +/write_gzip.v +/write_gzip.v.gz diff --git a/tests/various/write_gzip.ys b/tests/various/write_gzip.ys new file mode 100644 index 000000000..030ec318e --- /dev/null +++ b/tests/various/write_gzip.ys @@ -0,0 +1,16 @@ +read -vlog2k < Date: Tue, 6 Aug 2019 15:24:49 -0700 Subject: Move LSB tests from wreduce to opt_expr --- tests/various/opt_expr.ys | 98 ++++++++++++++++++++++++++++++++++++++++++++ tests/various/wreduce.ys | 102 ++-------------------------------------------- 2 files changed, 101 insertions(+), 99 deletions(-) create mode 100644 tests/various/opt_expr.ys (limited to 'tests') diff --git a/tests/various/opt_expr.ys b/tests/various/opt_expr.ys new file mode 100644 index 000000000..2165802d6 --- /dev/null +++ b/tests/various/opt_expr.ys @@ -0,0 +1,98 @@ + +read_verilog <> 4) - i; endmodule EOT @@ -81,7 +8,8 @@ hierarchy -auto-top proc design -save gold -prep # calls wreduce +opt_expr +wreduce select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i @@ -92,27 +20,3 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter - -########## - -read_verilog < Date: Tue, 6 Aug 2019 15:38:43 -0700 Subject: Add signed test --- tests/various/wreduce.ys | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'tests') diff --git a/tests/various/wreduce.ys b/tests/various/wreduce.ys index 7e4f1765a..4257292f5 100644 --- a/tests/various/wreduce.ys +++ b/tests/various/wreduce.ys @@ -20,3 +20,29 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + +########## + +read_verilog <>> 4) - i; +endmodule +EOT + +hierarchy -auto-top +proc +design -save gold + +opt_expr +wreduce + +dump +select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i + +design -stash gate + +design -import gold -as gold +design -import gate -as gate + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter -- cgit v1.2.3 From 2d1b517b01b6cd1ec35018d4c63aaa091fcc1917 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 6 Aug 2019 15:40:30 -0700 Subject: Add signed opt_expr tests --- tests/various/opt_expr.ys | 50 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) (limited to 'tests') diff --git a/tests/various/opt_expr.ys b/tests/various/opt_expr.ys index 2165802d6..0c61ac881 100644 --- a/tests/various/opt_expr.ys +++ b/tests/various/opt_expr.ys @@ -24,6 +24,31 @@ sat -verify -prove-asserts -show-ports miter ########## +read_verilog < Date: Wed, 7 Aug 2019 09:30:58 +0200 Subject: Fix wrong results when opt_share called before opt_clean --- tests/opt/opt_share_large_pmux_cat_multipart.ys | 1 - 1 file changed, 1 deletion(-) (limited to 'tests') diff --git a/tests/opt/opt_share_large_pmux_cat_multipart.ys b/tests/opt/opt_share_large_pmux_cat_multipart.ys index 54d200dc7..610bb8c6c 100644 --- a/tests/opt/opt_share_large_pmux_cat_multipart.ys +++ b/tests/opt/opt_share_large_pmux_cat_multipart.ys @@ -7,7 +7,6 @@ opt merged opt_share merged opt_clean merged -opt -full miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter -- cgit v1.2.3 From 4545bf482f029b7a49a7c2f88514b6c86ebf563f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 7 Aug 2019 16:48:38 -0700 Subject: Remove tests/opt/opt_ff.{v,ys} as they don't seem to do anything but run --- tests/opt/opt_ff.v | 21 --------------------- tests/opt/opt_ff.ys | 3 --- 2 files changed, 24 deletions(-) delete mode 100644 tests/opt/opt_ff.v delete mode 100644 tests/opt/opt_ff.ys (limited to 'tests') diff --git a/tests/opt/opt_ff.v b/tests/opt/opt_ff.v deleted file mode 100644 index a01b64b61..000000000 --- a/tests/opt/opt_ff.v +++ /dev/null @@ -1,21 +0,0 @@ -module top( - input clk, - input rst, - input [2:0] a, - output [1:0] b -); - reg [2:0] b_reg; - initial begin - b_reg <= 3'b0; - end - - assign b = b_reg[1:0]; - always @(posedge clk or posedge rst) begin - if(rst) begin - b_reg <= 3'b0; - end else begin - b_reg <= a; - end - end -endmodule - diff --git a/tests/opt/opt_ff.ys b/tests/opt/opt_ff.ys deleted file mode 100644 index 704c7acf3..000000000 --- a/tests/opt/opt_ff.ys +++ /dev/null @@ -1,3 +0,0 @@ -read_verilog opt_ff.v -synth_ice40 -ice40_unlut -- cgit v1.2.3 From 35bf509603904633e4bfd1d21aef834966378a90 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 7 Aug 2019 21:31:32 -0700 Subject: Add testcase from removed opt_ff.{v,ys} --- tests/various/wreduce.ys | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'tests') diff --git a/tests/various/wreduce.ys b/tests/various/wreduce.ys index 4257292f5..d3a59c6e3 100644 --- a/tests/various/wreduce.ys +++ b/tests/various/wreduce.ys @@ -46,3 +46,35 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + +########## + +# Testcase from: https://github.com/YosysHQ/yosys/commit/25680f6a078bb32f157bd580705656496717bafb +design -reset +read_verilog < Date: Wed, 7 Aug 2019 21:33:56 -0700 Subject: Remove ice40_unlut call, simply do equiv_opt on synth_ice40 --- tests/opt/opt_lut.ys | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'tests') diff --git a/tests/opt/opt_lut.ys b/tests/opt/opt_lut.ys index 59b12c351..a9fccbb62 100644 --- a/tests/opt/opt_lut.ys +++ b/tests/opt/opt_lut.ys @@ -1,4 +1,2 @@ read_verilog opt_lut.v -synth_ice40 -ice40_unlut -equiv_opt -map +/ice40/cells_sim.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3 +equiv_opt -map +/ice40/cells_sim.v -assert synth_ice40 -- cgit v1.2.3 From 2b6cdfb39f9010861cb203809b295d1c36d58aa5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 7 Aug 2019 21:35:48 -0700 Subject: Move tests/various/opt* into tests/opt/ --- tests/opt/opt_expr.ys | 148 +++++++++++++++++++++++++++++++++++++++++++++ tests/opt/opt_ff_sat.v | 12 ---- tests/opt/opt_ff_sat.ys | 5 -- tests/opt/opt_rmdff.v | 50 +++++++++++++++ tests/opt/opt_rmdff.ys | 26 ++++++++ tests/opt/opt_rmdff_sat.v | 12 ++++ tests/opt/opt_rmdff_sat.ys | 5 ++ tests/various/opt_expr.ys | 148 --------------------------------------------- tests/various/opt_rmdff.v | 50 --------------- tests/various/opt_rmdff.ys | 26 -------- 10 files changed, 241 insertions(+), 241 deletions(-) create mode 100644 tests/opt/opt_expr.ys delete mode 100644 tests/opt/opt_ff_sat.v delete mode 100644 tests/opt/opt_ff_sat.ys create mode 100644 tests/opt/opt_rmdff.v create mode 100644 tests/opt/opt_rmdff.ys create mode 100644 tests/opt/opt_rmdff_sat.v create mode 100644 tests/opt/opt_rmdff_sat.ys delete mode 100644 tests/various/opt_expr.ys delete mode 100644 tests/various/opt_rmdff.v delete mode 100644 tests/various/opt_rmdff.ys (limited to 'tests') diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys new file mode 100644 index 000000000..0c61ac881 --- /dev/null +++ b/tests/opt/opt_expr.ys @@ -0,0 +1,148 @@ + +read_verilog < Date: Wed, 7 Aug 2019 21:36:02 -0700 Subject: Remove dump call --- tests/various/wreduce.ys | 1 - 1 file changed, 1 deletion(-) (limited to 'tests') diff --git a/tests/various/wreduce.ys b/tests/various/wreduce.ys index d3a59c6e3..2e0812c48 100644 --- a/tests/various/wreduce.ys +++ b/tests/various/wreduce.ys @@ -36,7 +36,6 @@ design -save gold opt_expr wreduce -dump select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i design -stash gate -- cgit v1.2.3 From d9c16644626d49b5bb5eb463f2a113e13ad22d69 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 9 Aug 2019 10:08:17 -0700 Subject: Simplify opt_expr tests using equiv_opt --- tests/opt/opt_expr.ys | 95 +++++++++++++-------------------------------------- 1 file changed, 23 insertions(+), 72 deletions(-) (limited to 'tests') diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys index 0c61ac881..9f3c0a1cd 100644 --- a/tests/opt/opt_expr.ys +++ b/tests/opt/opt_expr.ys @@ -6,24 +6,16 @@ endmodule EOT hierarchy -auto-top -proc -design -save gold -opt_expr -fine -wreduce +equiv_opt -assert opt_expr -fine +design -load postopt +wreduce select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i -design -stash gate - -design -import gold -as gold -design -import gate -as gate - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter - ########## +design -reset read_verilog < Date: Fri, 9 Aug 2019 10:13:49 -0700 Subject: Cleanup some more --- tests/opt/opt_expr.ys | 12 ------------ 1 file changed, 12 deletions(-) (limited to 'tests') diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys index 9f3c0a1cd..28d57f530 100644 --- a/tests/opt/opt_expr.ys +++ b/tests/opt/opt_expr.ys @@ -5,8 +5,6 @@ module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o); endmodule EOT -hierarchy -auto-top - equiv_opt -assert opt_expr -fine design -load postopt @@ -22,8 +20,6 @@ module opt_expr_add_signed_test(input signed [3:0] i, input signed [7:0] j, outp endmodule EOT -hierarchy -auto-top - equiv_opt -assert opt_expr -fine design -load postopt @@ -39,8 +35,6 @@ module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o); endmodule EOT -hierarchy -auto-top - equiv_opt -assert opt_expr -fine design -load postopt @@ -56,8 +50,6 @@ module opt_expr_sub_signed_test1(input signed [3:0] i, input signed [7:0] j, out endmodule EOT -hierarchy -auto-top - equiv_opt -assert opt_expr -fine design -load postopt @@ -73,8 +65,6 @@ module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o); endmodule EOT -hierarchy -auto-top - equiv_opt -assert opt_expr -fine design -load postopt @@ -90,8 +80,6 @@ module opt_expr_sub_test4(input [3:0] i, output [8:0] o); endmodule EOT -hierarchy -auto-top - equiv_opt -assert opt_expr -fine design -load postopt -- cgit v1.2.3 From 93001116011d46e50c0a24b0bd21c2f07746dc42 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 9 Aug 2019 10:22:06 -0700 Subject: Add new $alu test, remove wreduce --- tests/opt/opt_expr.ys | 32 +++++++++++++++++++++----------- 1 file changed, 21 insertions(+), 11 deletions(-) (limited to 'tests') diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys index 28d57f530..96ab2f31a 100644 --- a/tests/opt/opt_expr.ys +++ b/tests/opt/opt_expr.ys @@ -8,8 +8,22 @@ EOT equiv_opt -assert opt_expr -fine design -load postopt -wreduce -select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i +select -assert-count 1 t:$add r:A_WIDTH=5 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i + +########## + +design -reset +read_verilog < Date: Fri, 9 Aug 2019 10:30:53 -0700 Subject: Add alumacc versions of opt_expr tests --- tests/opt/opt_expr.ys | 84 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) (limited to 'tests') diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys index 96ab2f31a..9f5e845ca 100644 --- a/tests/opt/opt_expr.ys +++ b/tests/opt/opt_expr.ys @@ -12,6 +12,7 @@ select -assert-count 1 t:$add r:A_WIDTH=5 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i ########## +# alumacc version of above design -reset read_verilog < Date: Fri, 9 Aug 2019 12:13:17 -0700 Subject: Add $alu tests --- tests/opt/opt_expr.ys | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) (limited to 'tests') diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys index 9f5e845ca..f0306efa1 100644 --- a/tests/opt/opt_expr.ys +++ b/tests/opt/opt_expr.ys @@ -179,3 +179,45 @@ equiv_opt -assert opt_expr -fine design -load postopt select -assert-count 1 t:$alu r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i + +########### + +design -reset +read_verilog -icells < Date: Sat, 10 Aug 2019 17:14:48 +0100 Subject: Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER" --- tests/opt/opt_expr.ys | 148 --------------------------------------------- tests/opt/opt_ff.v | 21 +++++++ tests/opt/opt_ff.ys | 3 + tests/opt/opt_ff_sat.v | 12 ++++ tests/opt/opt_ff_sat.ys | 5 ++ tests/opt/opt_lut.ys | 4 +- tests/opt/opt_rmdff.v | 50 --------------- tests/opt/opt_rmdff.ys | 26 -------- tests/opt/opt_rmdff_sat.v | 12 ---- tests/opt/opt_rmdff_sat.ys | 5 -- tests/various/opt_expr.ys | 148 +++++++++++++++++++++++++++++++++++++++++++++ tests/various/opt_rmdff.v | 50 +++++++++++++++ tests/various/opt_rmdff.ys | 26 ++++++++ tests/various/wreduce.ys | 33 +--------- 14 files changed, 269 insertions(+), 274 deletions(-) delete mode 100644 tests/opt/opt_expr.ys create mode 100644 tests/opt/opt_ff.v create mode 100644 tests/opt/opt_ff.ys create mode 100644 tests/opt/opt_ff_sat.v create mode 100644 tests/opt/opt_ff_sat.ys delete mode 100644 tests/opt/opt_rmdff.v delete mode 100644 tests/opt/opt_rmdff.ys delete mode 100644 tests/opt/opt_rmdff_sat.v delete mode 100644 tests/opt/opt_rmdff_sat.ys create mode 100644 tests/various/opt_expr.ys create mode 100644 tests/various/opt_rmdff.v create mode 100644 tests/various/opt_rmdff.ys (limited to 'tests') diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys deleted file mode 100644 index 0c61ac881..000000000 --- a/tests/opt/opt_expr.ys +++ /dev/null @@ -1,148 +0,0 @@ - -read_verilog < Date: Mon, 12 Aug 2019 12:06:45 -0700 Subject: Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder" This reverts commit c851dc13108021834533094a8a3236da6d9e0161, reversing changes made to f54bf1631ff37a83733c162e6ebd188c1d5ea18f. --- tests/opt/opt_expr.ys | 223 +++++++++++++++++++++++++++++++++++++++++++++ tests/opt/opt_ff.v | 21 ----- tests/opt/opt_ff.ys | 3 - tests/opt/opt_ff_sat.v | 12 --- tests/opt/opt_ff_sat.ys | 5 - tests/opt/opt_lut.ys | 4 +- tests/opt/opt_rmdff.v | 50 ++++++++++ tests/opt/opt_rmdff.ys | 26 ++++++ tests/opt/opt_rmdff_sat.v | 12 +++ tests/opt/opt_rmdff_sat.ys | 5 + tests/various/opt_expr.ys | 223 --------------------------------------------- tests/various/opt_rmdff.v | 50 ---------- tests/various/opt_rmdff.ys | 26 ------ tests/various/wreduce.ys | 33 ++++++- 14 files changed, 349 insertions(+), 344 deletions(-) create mode 100644 tests/opt/opt_expr.ys delete mode 100644 tests/opt/opt_ff.v delete mode 100644 tests/opt/opt_ff.ys delete mode 100644 tests/opt/opt_ff_sat.v delete mode 100644 tests/opt/opt_ff_sat.ys create mode 100644 tests/opt/opt_rmdff.v create mode 100644 tests/opt/opt_rmdff.ys create mode 100644 tests/opt/opt_rmdff_sat.v create mode 100644 tests/opt/opt_rmdff_sat.ys delete mode 100644 tests/various/opt_expr.ys delete mode 100644 tests/various/opt_rmdff.v delete mode 100644 tests/various/opt_rmdff.ys (limited to 'tests') diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys new file mode 100644 index 000000000..f0306efa1 --- /dev/null +++ b/tests/opt/opt_expr.ys @@ -0,0 +1,223 @@ + +read_verilog < Date: Fri, 16 Aug 2019 14:22:46 +0200 Subject: Do not use Verific in tests/various/write_gzip.ys Signed-off-by: Clifford Wolf --- tests/various/write_gzip.ys | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/various/write_gzip.ys b/tests/various/write_gzip.ys index 030ec318e..524ecc33e 100644 --- a/tests/various/write_gzip.ys +++ b/tests/various/write_gzip.ys @@ -1,4 +1,4 @@ -read -vlog2k < Date: Sat, 17 Aug 2019 14:37:07 +0200 Subject: Speed up "make test" and related cleanups Signed-off-by: Clifford Wolf --- tests/fsm/run-test.sh | 2 +- tests/simple_abc9/run-test.sh | 3 ++- tests/various/.gitignore | 1 + tests/various/run-test.sh | 16 ++++++++++++---- tests/various/shregmap.ys | 10 +++++----- 5 files changed, 21 insertions(+), 11 deletions(-) (limited to 'tests') diff --git a/tests/fsm/run-test.sh b/tests/fsm/run-test.sh index cf506470d..fbdcbf048 100755 --- a/tests/fsm/run-test.sh +++ b/tests/fsm/run-test.sh @@ -6,7 +6,7 @@ set -e OPTIND=1 -count=100 +count=50 seed="" # default to no seed specified while getopts "c:S:" opt do diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh index 4935d41ad..49ae23338 100755 --- a/tests/simple_abc9/run-test.sh +++ b/tests/simple_abc9/run-test.sh @@ -18,5 +18,6 @@ if ! which iverilog > /dev/null ; then fi cp ../simple/*.v . +cp ../simple/*.sv . DOLLAR='?' -exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4 -box ../abc.box; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'" +exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-n 300 -p 'hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4 -box ../abc.box; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'" diff --git a/tests/various/.gitignore b/tests/various/.gitignore index 31078b298..4b286fd61 100644 --- a/tests/various/.gitignore +++ b/tests/various/.gitignore @@ -2,3 +2,4 @@ /*.out /write_gzip.v /write_gzip.v.gz +/run-test.mk diff --git a/tests/various/run-test.sh b/tests/various/run-test.sh index 92b905765..ea56b70f0 100755 --- a/tests/various/run-test.sh +++ b/tests/various/run-test.sh @@ -1,12 +1,20 @@ #!/usr/bin/env bash set -e +{ +echo "all::" for x in *.ys; do - echo "Running $x.." - ../../yosys -ql ${x%.ys}.log $x + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../yosys -ql ${x%.ys}.log $x" done for s in *.sh; do if [ "$s" != "run-test.sh" ]; then - echo "Running $s.." - bash $s + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s" fi done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/various/shregmap.ys b/tests/various/shregmap.ys index d644a88aa..5c9c78dd2 100644 --- a/tests/various/shregmap.ys +++ b/tests/various/shregmap.ys @@ -45,7 +45,7 @@ shregmap -tech xilinx stat # show -width -write_verilog -noexpr -norename +# write_verilog -noexpr -norename select -assert-count 1 t:$_DFF_P_ select -assert-count 2 t:$__XILINX_SHREG_ @@ -59,8 +59,8 @@ prep miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports -seq 5 miter -design -load gold -stat +# design -load gold +# stat -design -load gate -stat +# design -load gate +# stat -- cgit v1.2.3 From f5170a7eda6fddaf482896a2ad67da4bb3131d7b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sun, 18 Aug 2019 21:28:45 -0700 Subject: Removal of more `stat` calls from tests --- tests/various/muxpack.ys | 30 +++++++++++++++--------------- tests/various/opt_rmdff.ys | 10 +++++----- tests/various/shregmap.ys | 12 ++++++------ 3 files changed, 26 insertions(+), 26 deletions(-) (limited to 'tests') diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index af23fcec8..3e90419af 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -6,7 +6,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate @@ -21,7 +21,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate @@ -52,7 +52,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 2 t:$pmux design -stash gate @@ -67,7 +67,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate @@ -82,7 +82,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate @@ -97,7 +97,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate @@ -112,7 +112,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate @@ -127,7 +127,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate @@ -142,7 +142,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 7 t:$mux select -assert-count 0 t:$pmux design -stash gate @@ -157,7 +157,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 4 t:$mux select -assert-count 0 t:$pmux design -stash gate @@ -172,7 +172,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 3 t:$mux select -assert-count 0 t:$pmux design -stash gate @@ -204,7 +204,7 @@ prep design -save gold muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 2 t:$pmux design -stash gate @@ -222,7 +222,7 @@ opt -fast -mux_undef select -assert-count 2 t:$pmux muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate @@ -240,7 +240,7 @@ opt -fast -mux_undef select -assert-count 2 t:$pmux muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 2 t:$pmux design -stash gate @@ -258,7 +258,7 @@ opt -fast -mux_undef select -assert-count 2 t:$pmux muxpack opt -stat +#stat select -assert-count 0 t:$mux select -assert-count 2 t:$pmux design -stash gate diff --git a/tests/various/opt_rmdff.ys b/tests/various/opt_rmdff.ys index 081f81782..83a162f44 100644 --- a/tests/various/opt_rmdff.ys +++ b/tests/various/opt_rmdff.ys @@ -19,8 +19,8 @@ hierarchy -top equiv equiv_simple -undef equiv_status -assert -design -load gold -stat - -design -load gate -stat +#design -load gold +#stat +# +#design -load gate +#stat diff --git a/tests/various/shregmap.ys b/tests/various/shregmap.ys index 5c9c78dd2..0e5fe882b 100644 --- a/tests/various/shregmap.ys +++ b/tests/various/shregmap.ys @@ -11,7 +11,7 @@ shregmap -init opt -stat +# stat # show -width select -assert-count 1 t:$_DFF_P_ select -assert-count 2 t:$__SHREG_DFF_P_ @@ -26,11 +26,11 @@ prep miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports -seq 5 miter -design -load gold -stat +#design -load gold +#stat -design -load gate -stat +#design -load gate +#stat ########## @@ -43,7 +43,7 @@ design -save gold simplemap t:$dff t:$dffe shregmap -tech xilinx -stat +#stat # show -width # write_verilog -noexpr -norename select -assert-count 1 t:$_DFF_P_ -- cgit v1.2.3 From 21699e5840b71433eb242d9c60f1635908717f5e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 19 Aug 2019 13:04:57 +0200 Subject: Add *.sv to tests/simple_abc9/.gitignore Signed-off-by: Clifford Wolf --- tests/simple_abc9/.gitignore | 1 + 1 file changed, 1 insertion(+) (limited to 'tests') diff --git a/tests/simple_abc9/.gitignore b/tests/simple_abc9/.gitignore index 598951333..2355aea29 100644 --- a/tests/simple_abc9/.gitignore +++ b/tests/simple_abc9/.gitignore @@ -1,3 +1,4 @@ *.v +*.sv *.log *.out -- cgit v1.2.3